CN116844597A - Spin-orbit-moment-based memory cells, arrays, circuits, and methods - Google Patents

Abstract

The embodiment of the application provides a memory cell, an array, a circuit and a method based on spin orbit torque, wherein the memory cell comprises the following components: a first transistor and a pair of second transistors; and a magnetic tunnel junction including a spin coupling layer, a free layer, a barrier layer, and a fixed layer, which are sequentially stacked. The three transistors and the spin-orbit torque magnetic memory device of the three-port magnetic tunnel junction form a memory unit, and compared with the traditional structure that the two transistors and the spin-orbit torque magnetic memory device of the three-port magnetic tunnel junction form a memory unit, the write-in efficiency is improved, the area is not increased, and the integration level is improved.

Description

Spin-orbit-moment-based memory cells, arrays, circuits, and methods

Technical Field

The present application relates to the field of electronics, and in particular, to a memory cell, an array, a memory circuit, an electronic device, and a method.

Background

With the continuous shrinking of process nodes, the leakage current phenomenon of conventional transistor-based memory devices is gradually aggravated, resulting in an increase in static power consumption. In addition, in a typical computer architecture, the access speed between the logic computation unit and the memory and between the memories of each level is seriously mismatched, so that the data processing bandwidth is greatly reduced. In recent years, a magnetic random access memory (Magnetic random access memory, MRAM) using a magnetic tunnel junction (Magnetic tunnel junction, MTJ) as a core device has been expected to solve the above-described performance bottleneck because of its low power consumption, nonvolatile memory, high writing speed, and the like.

MRAM writing has undergone mainly three generations of revolution. The first generation of MRAM uses a magnetic field to realize data writing, but the required current is high, and the problem of power consumption is aggravated with the shrinking of the size of the magnetic tunnel junction, so that the application prospect is limited. The second generation MRAM uses current to generate spin transfer torque (Spin transfer torque, STT) to realize data writing, so that the defect of the first generation magnetic field writing mode is overcome, but the writing process of the STT-MRAM has longer relaxation delay, and the writing speed is severely restricted. In addition, both the STT write current and the Read current directly pass through the magnetic tunnel junction, which is very prone to reliability problems such as Read disturb (Read disturb) and barrier breakdown (Barrier breakdown). The third-generation MRAM adopts a spin orbit torque (Spin orbit torque, SOT) writing technology, so that relaxation delay can be avoided, and the performance bottleneck of the STT-MRAM can be effectively broken through. Because the write current does not pass through the magnetic tunnel junction, the SOT-MTJ has little risk of barrier breakdown, the reliability and the erasing times are greatly improved, and the read-write path separation enables the read-write performance to be independently optimized. For the currently commonly used magnetic tunnel junctions with perpendicular magnetic anisotropy (Perpendicular magnetic anisotropy, PMA), the writing speed of SOT-MRAM can reach sub-nanoseconds.

However, the memory cell of the SOT-MRAM is generally composed of a write NMOS transistor, a read NMOS transistor and an SOT-MTJ, where the write path is driven by the write NMOS transistor, and as the CMOS process size is reduced, the power supply voltage is reduced, and the on-resistance of the NMOS transistor with the minimum size is increased, so that the driving pressure of the selection transistor is gradually increased, and it is difficult for the NMOS transistor with the single minimum size to meet the driving requirement, and it is required to increase the size, increase the voltage or decrease the speed, which is unfavorable for the performance improvement of the SOT-MRAM.

Disclosure of Invention

In order to solve the problems in the prior art, the application provides a memory cell based on spin orbit torque, a memory cell array formed by the memory cells, a memory circuit and an electronic device, wherein the memory cell comprises: a first transistor and a pair of second transistors; wherein each transistor comprises two non-control poles and a control pole, one non-control pole of each second transistor is respectively coupled with one non-control pole of the first transistor and forms a node, the other non-control pole of each second transistor is coupled to a common bit line, the control pole of the second transistor is coupled with a word line, and the control pole of the first transistor is coupled with an enhanced write word line; and a magnetic tunnel junction including a spin coupling layer, a free layer, a barrier layer, and a fixed layer stacked in this order, one end of the spin coupling layer being coupled to one of the nodes, the other end being coupled to a common source line, the fixed layer being coupled to the other of the nodes, the control electrode of the first transistor, and the enhancement word line. The three transistors and the spin-orbit torque magnetic memory device of the three-port magnetic tunnel junction form a memory unit, and compared with the traditional structure that the two transistors and the spin-orbit torque magnetic memory device of the three-port magnetic tunnel junction form a memory unit, the write-in efficiency is improved, the area is not increased, and the integration level is improved.

One aspect of the present application provides a spin-orbit torque based memory unit comprising:

a first transistor and a pair of second transistors; wherein each transistor comprises two non-control poles and a control pole, one non-control pole of each second transistor is respectively coupled with one non-control pole of the first transistor and forms a node, the other non-control pole of each second transistor is coupled to a common bit line, the control pole of the second transistor is coupled with a word line, and the control pole of the first transistor is coupled with an enhanced write word line; and

the magnetic tunnel junction comprises a spin coupling layer, a free layer, a barrier layer and a fixed layer which are sequentially stacked, wherein one end of the spin coupling layer is coupled with one node, the other end of the spin coupling layer is coupled with a common source line, and the fixed layer is coupled with the other node, the control electrode of the first transistor and the enhanced word line.

In a preferred embodiment, the word lines include a read word line coupled to the control electrode of one of the second transistors and a write word line coupled to the control electrode of the other of the second transistors.

In a preferred embodiment, the first transistor is one of an NMOS transistor and a PMOS transistor.

In a preferred embodiment, each of the second transistors is one of an NMOS transistor and a PMOS transistor.

Another aspect of the present application provides a spin-orbit-torque based memory cell array including a plurality of memory cells arranged in an array, each memory cell including:

a first transistor and a pair of second transistors; wherein each transistor comprises two non-control poles and a control pole, one non-control pole of each second transistor is respectively coupled with one non-control pole of the first transistor and forms a node, the other non-control pole of each second transistor is coupled to a common bit line, the control pole of the second transistor is coupled with a word line, and the control pole of the first transistor is coupled with an enhanced write word line; and

the magnetic tunnel junction comprises a spin coupling layer, a free layer, a barrier layer and a fixed layer which are sequentially stacked, wherein one end of the spin coupling layer is coupled with one node, the other end of the spin coupling layer is coupled with a common source line, and the fixed layer is coupled with the other node, the control electrode of the first transistor and the enhanced word line.

Yet another aspect of the present application provides a memory circuit including at least one memory cell array, each memory cell array including a plurality of memory cells arranged in an array, each memory cell including:

a first transistor and a pair of second transistors; wherein each transistor comprises two non-control poles and a control pole, one non-control pole of each second transistor is respectively coupled with one non-control pole of the first transistor and forms a node, the other non-control pole of each second transistor is coupled to a common bit line, the control pole of the second transistor is coupled with a word line, and the control pole of the first transistor is coupled with an enhanced write word line; and

the magnetic tunnel junction comprises a spin coupling layer, a free layer, a barrier layer and a fixed layer which are sequentially stacked, wherein one end of the spin coupling layer is coupled with one node, the other end of the spin coupling layer is coupled with a common source line, and the fixed layer is coupled with the other node, the control electrode of the first transistor and the enhanced word line.

Yet another aspect of the present application provides a memory comprising a memory circuit comprising at least one memory cell array, each memory cell array comprising a plurality of memory cells arranged in an array, each memory cell comprising:

a first transistor and a pair of second transistors; wherein each transistor comprises two non-control poles and a control pole, one non-control pole of each second transistor is respectively coupled with one non-control pole of the first transistor and forms a node, the other non-control pole of each second transistor is coupled to a common bit line, the control pole of the second transistor is coupled with a word line, and the control pole of the first transistor is coupled with an enhanced write word line; and

the magnetic tunnel junction comprises a spin coupling layer, a free layer, a barrier layer and a fixed layer which are sequentially stacked, wherein one end of the spin coupling layer is coupled with one node, the other end of the spin coupling layer is coupled with a common source line, and the fixed layer is coupled with the other node, the control electrode of the first transistor and the enhanced word line.

Yet another aspect of the present application provides an electronic device comprising a memory and a processor for executing data and/or programs stored in the memory, the memory comprising a memory circuit comprising at least one memory cell array, each memory cell array comprising a plurality of memory cells arranged in an array, each memory cell comprising:

a first transistor and a pair of second transistors; wherein each transistor comprises two non-control poles and a control pole, one non-control pole of each second transistor is respectively coupled with one non-control pole of the first transistor and forms a node, the other non-control pole of each second transistor is coupled to a common bit line, the control pole of the second transistor is coupled with a word line, and the control pole of the first transistor is coupled with an enhanced write word line; and

the magnetic tunnel junction comprises a spin coupling layer, a free layer, a barrier layer and a fixed layer which are sequentially stacked, wherein one end of the spin coupling layer is coupled with one node, the other end of the spin coupling layer is coupled with a common source line, and the fixed layer is coupled with the other node, the control electrode of the first transistor and the enhanced word line.

A further aspect of the present application provides a method of writing to a spin-orbit torque based memory cell, the memory cell being as described above, comprising:

accessing a first voltage to a source line coupled to the spin-coupling layer of the tunnel junction;

accessing a second voltage to a bit line coupled to one of the non-control electrodes of the second transistor in the memory cell;

control voltages are introduced to the write word line, the read word line, and the enhancement word line to control the spin coupling layer of the magnetic tunnel junction in the memory cell to conduct a set direction current, the set direction current being determined based on a voltage difference between the first voltage and the second voltage.

A further aspect of the present application provides a method of reading a spin-orbit torque based memory cell, the memory cell being as described above, comprising:

accessing a third voltage to a source line coupled to the spin-coupling layer of the memory cell magnetic tunnel junction;

accessing a fourth voltage to a bit line coupled to one of the non-control electrodes of the second transistor in the memory cell;

introducing a control voltage to the read word line, and acquiring voltage value information and current value information of the magnetic tunnel junction of the memory cell, wherein the voltage value information is determined based on the differential pressure of the third voltage and the fourth voltage;

and determining the storage information in the storage unit according to the voltage value information and the current value information.

In yet another aspect of the present application, a method for fabricating a memory cell based on spin-orbit torque is provided, comprising:

forming a first transistor and a pair of second transistors on a substrate under the same etching process; wherein each transistor comprises two non-control poles and a control pole;

coupling a non-control electrode of each second transistor with one of the non-control electrodes of the first transistors to form a node, coupling the other non-control electrode of each second transistor to a common bit line, coupling the control electrode thereof with a word line, and coupling the control electrode of the first transistor with an enhanced write word line;

sequentially stacking a spin coupling layer, a free layer, a barrier layer and a fixed layer on the substrate, wherein the spin coupling layer, the free layer, the barrier layer and the fixed layer form a magnetic tunnel junction;

one end of the spin coupling layer is coupled with one of the nodes, the other end is coupled with a common source line, the fixed layer is coupled with the other node, and the control electrode of the first transistor is coupled with the enhanced word line.

As can be seen from the above technical solutions, the present application provides a memory cell, an array, a memory circuit, an electronic device and a method based on spin orbit torque, wherein the memory cell includes: a first transistor and a pair of second transistors; wherein each transistor comprises two non-control poles and a control pole, one non-control pole of each second transistor is respectively coupled with one non-control pole of the first transistor and forms a node, the other non-control pole of each second transistor is coupled to a common bit line, the control pole of the second transistor is coupled with a word line, and the control pole of the first transistor is coupled with an enhanced write word line; and a magnetic tunnel junction including a spin coupling layer, a free layer, a barrier layer, and a fixed layer stacked in this order, one end of the spin coupling layer being coupled to one of the nodes, the other end being coupled to a common source line, the fixed layer being coupled to the other of the nodes, the control electrode of the first transistor, and the enhancement word line. The three transistors and the spin-orbit torque magnetic memory device of the three-port magnetic tunnel junction form a memory unit, and compared with the traditional structure that the two transistors and the spin-orbit torque magnetic memory device of the three-port magnetic tunnel junction form a memory unit, the write-in efficiency is improved, the area is not increased, and the integration level is improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a memory cell according to an embodiment of the present application.

FIG. 2 is a schematic diagram of a memory cell writing and reading method according to an embodiment of the present application.

FIG. 3 is a flowchart illustrating a method for writing a memory cell according to an embodiment of the application.

Fig. 4 is a flowchart illustrating a method for reading a memory cell according to an embodiment of the application.

FIG. 5 is a schematic diagram of a memory cell array according to an embodiment of the present application.

Fig. 6 is a schematic diagram of a memory cell array according to the prior art in an embodiment of the present application.

FIG. 7 is a flow chart of a method of fabricating a memory cell based on spin-orbit torque according to an embodiment of the application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

MRAM writing has undergone mainly three generations of revolution. The first generation of MRAM uses a magnetic field to realize data writing, but the required current is high, and the problem of power consumption is aggravated with the shrinking of the size of the magnetic tunnel junction, so that the application prospect is limited. The second generation MRAM uses current to generate spin transfer torque (Spin transfer torque, STT) to realize data writing, so that the defect of the first generation magnetic field writing mode is overcome, but the writing process of the STT-MRAM has longer relaxation delay, and the writing speed is severely restricted. In addition, both the STT write current and the Read current directly pass through the magnetic tunnel junction, which is very prone to reliability problems such as Read disturb (Read disturb) and barrier breakdown (Barrier breakdown). The third-generation MRAM adopts a spin orbit torque (Spin orbit torque, SOT) writing technology, so that relaxation delay can be avoided, and the performance bottleneck of the STT-MRAM can be effectively broken through. Because the write current does not pass through the magnetic tunnel junction, the SOT-MTJ has little risk of barrier breakdown, the reliability and the erasing times are greatly improved, and the read-write path separation enables the read-write performance to be independently optimized. For the currently commonly used magnetic tunnel junctions with perpendicular magnetic anisotropy (Perpendicular magnetic anisotropy, PMA), the writing speed of SOT-MRAM can reach sub-nanoseconds.

SOT-MRAM, however. The memory cell of the SOT-MRAM is typically composed of a write NMOS transistor, a read NMOS transistor, and an SOT-MTJ, as shown in FIG. 1 (a). The write-in path is driven by the write NMOS transistor, and as the CMOS process size is continuously reduced, the power supply voltage is reduced, and the on-resistance of the NMOS transistor with the minimum size is increased, so that the driving pressure of the selection transistor is gradually increased, the single NMOS transistor with the minimum size is difficult to meet the driving requirement, and the size, the voltage and the speed are required to be increased, so that the performance of the SOT-MRAM is not improved.

In view of the problems in the prior art, the present application provides a spin-orbit torque based memory cell comprising: a pair of memory cells and a first transistor; each memory cell includes a second transistor; the control electrode of the first transistor is coupled to a write word line, wherein one non-control electrode and one non-control electrode are each coupled between the second transistor of a memory cell and the magnetic tunnel junction. The purpose of reducing the driving resistance is achieved through the serial connection and the parallel connection of the first transistor and the second transistor, and meanwhile, the introduced first transistor is reasonably distributed at the interval between the two memory cells, so that the driving capability of the memory cells is improved through reducing the driving resistance under the condition of not increasing the area.

The present application will be described in detail with reference to the accompanying drawings.

In a first aspect of the present application, a memory cell based on spin-orbit torque is provided, as shown in the embodiment (b) of fig. 1, comprising a second transistor N0, a second transistor N1, and a magnetic tunnel junction (the magnetic tunnel junction comprises a spin coupling layer 1, a free layer 2, a barrier layer 3, and a fixed layer 4), and a first transistor N2. In a specific embodiment, the transistor is one of an NMOS transistor and a PMOS transistor, where the three transistors should be of the same type, for example, if the second transistor N0 is an NMOS transistor, the second transistor N1 is also an NMOS transistor, and the first transistor N2 is also an NMOS transistor; if the second transistor N0 is a PMOS transistor, the second transistor N1 is also a PMOS transistor, and the first transistor N2 is also a PMOS transistor. In a specific embodiment, the magnetic tunnel junction is a non-volatile magnetic tunnel junction SOT, that is, the information in the magnetic tunnel junction is still not lost when the memory cell is powered off, for example, the memory resistor is made of a non-conductive material, and reversible conversion is realized between a high resistance state and a low resistance state under the action of an applied electric field, so that one bit information is recorded.

In a specific embodiment, each transistor includes two non-control electrodes and a control electrode; wherein one non-control electrode and the other non-control electrode respectively correspond to the source electrode and the drain electrode of the transistor, for example, if one non-control electrode is the source electrode, the other non-control electrode is the drain electrode; the control electrode corresponds to the gate of the transistor. As shown in fig. 1 (b), the control electrode of the second transistor N0 is coupled to a Read Word Line (RWL), one of the non-control electrodes is coupled to one end of the magnetic tunnel junction through a node 1, and the other non-control electrode is coupled to a common bit line BL; the second transistor N1 has a control electrode coupled to a Write Word Line (WWL), one of the non-control electrodes coupled to one end of the magnetic tunnel junction spin coupling layer, and the other non-control electrode coupled to the common bit line BL. For the first transistor, as shown in fig. 1 (b), the control electrode of the first transistor N2 is coupled to the enhancement word line (enhance word line, EWL), one non-control electrode is coupled to the node 1, and the other non-control electrode is coupled to the node 2.

It can be understood that when the magnitude of the driving voltage applied between the bit line and the source line is unchanged during the writing operation using the memory cell according to the present application, the driving resistance is smaller and the driving capability is stronger. Thus, in a specific embodiment, as shown in FIG. 2 (a), a write operation to a memory device: RWL, EWL and WWL are high potential at the same time, voltage is applied to the two ends of SL and BL, current flows through N1 and N2 (series connection of N0 and N2) respectively, after merging, the current flows through spin coupling layer of SOT-MTJ, shunt current of magnetic tunnel junction is negligible, theoretical on-resistance of transistor is reduced by 1/3, and theoretical driving capability is improved by 50%. Also, as shown in (b) of fig. 2, a read operation of the memory device: RWL is high, EWL and WWL are low, and read current flows from SL to spin-coupled layer, magnetic tunnel junction and N0 of SOT-MTJ, and finally to BL.

As can be seen from the above description, the spin-orbit torque based memory unit provided by the present application has the advantages that the writing efficiency is improved, the area is not increased, and the integration is improved as compared with the conventional structure in which the spin-orbit torque based memory unit using two transistors and one three-port magnetic tunnel junction is formed into one memory unit by forming the spin-orbit torque based memory unit of three transistors and one three-port magnetic tunnel junction.

In a second aspect of the present application, there is provided a method for writing information to a memory cell provided in the first aspect of the present application, as shown in fig. 3, comprising:

s1, connecting a first voltage to a source line coupled with a spin coupling layer of the tunnel junction;

s2, connecting a second voltage to a bit line coupled to one of non-control electrodes of a second transistor in the memory cell;

and S3, introducing control voltages to the write word line, the read word line and the enhanced word line to control the spin coupling layer of the magnetic tunnel junction in the memory cell to conduct a set-direction current, wherein the set-direction current is determined based on the difference between the first voltage and the second voltage.

Specifically, as shown in (a) of fig. 2, a write operation to the memory device: RWL, EWL and WWL are high potential at the same time, voltage is applied to the two ends of SL and BL, current flows through N1 and N2 (series connection of N0 and N2) respectively, after merging, the current flows through spin coupling layer of SOT-MTJ, shunt current of magnetic tunnel junction is negligible, theoretical on-resistance of transistor is reduced by 1/3, and theoretical driving capability is improved by 50%. The voltage difference between the first voltage and the second voltage is generated according to the information to be written, if the bit to be written is 1, the corresponding voltage difference is a positive value, all transistors are turned on, so that current flows from a bit line to a source line through a magnetic tunnel junction, and the magnetic tunnel junction records the bit 1 to be written currently under the action of the current direction; if the bit 0 needs to be written, the corresponding voltage difference is negative, all transistors are turned on, so that current flows from the source line through the magnetic tunnel junction and finally to the bit line, and the magnetic tunnel junction records the bit 0 needing to be written currently under the action of the current direction.

In a third aspect of the present application, there is provided a method for reading information stored in a storage unit according to the first aspect of the present application, as shown in fig. 4, including:

s101: accessing a third voltage to a source line coupled to the spin-coupling layer of the memory cell magnetic tunnel junction;

s102: accessing a fourth voltage to a bit line coupled to one of the non-control electrodes of the second transistor in the memory cell;

s103: introducing a control voltage to the read word line, and acquiring voltage value information and current value information of the magnetic tunnel junction of the memory cell, wherein the voltage value information is determined based on the differential pressure of the third voltage and the fourth voltage;

s104: and determining the storage information in the storage unit according to the voltage value information and the current value information.

Specifically, as shown in (b) of fig. 2, a read operation to the memory device: RWL is high, EWL and WWL are low, and read current flows from SL to spin-coupled layer, magnetic tunnel junction and N0 of SOT-MTJ, and finally to BL.

In a fourth aspect of the present application, there is provided a spin-orbit torque based memory cell array comprising a plurality of memory cells provided in the first aspect of the present application arranged in an array.

Specifically, the memory array is generally a two-dimensional array, fig. 5 is a schematic diagram of a memory cell array based on spin orbit moment according to an embodiment of the present application, and fig. 6 is a schematic diagram of a memory cell array according to the prior art. As can be seen by comparing fig. 5 and 6, the newly added first transistors are at the spacing of the conventional structure, each sharing a source and drain with the adjacent transistors, without an increase in the vertical dimension.

The array structure is shown in the figure, and it can be seen that the newly added first transistors are at intervals of the conventional structure, and each transistor shares a source and a drain with the adjacent transistor. Therefore, the application improves the driving capability of the memory cell without increasing the area.

In a fifth aspect of the present application, there is provided a memory circuit comprising at least one memory cell array provided in the fourth aspect of the present application, each memory cell array comprising a plurality of memory cells provided in the first aspect of the present application arranged in an array. It will be appreciated that the memory circuit includes not only the memory cells for storing information, but also the power supply circuits and associated control circuits for the word lines required to drive the memory cells.

Because the memory module of the memory circuit comprises the memory unit provided by the first aspect of the application, and the memory unit is formed by three transistors and a spin-orbit torque magnetic memory device of a three-port magnetic tunnel junction into one memory unit, compared with the traditional structure that the spin-orbit torque magnetic memory device adopting two transistors and a three-port magnetic tunnel junction forms one memory unit, the memory unit has the advantages of improving the writing efficiency, not increasing the area and being beneficial to improving the integration level. But it allows no change in area by reasonably utilizing the spacing of the conventional structure. The memory circuit formed by the memory cells improves the memory driving capability without increasing the memory circuit area.

A sixth aspect of the present application provides a memory comprising a memory circuit comprising at least one memory cell array provided in the fourth aspect of the present application, each memory cell array comprising a plurality of memory cells provided in the first aspect of the present application arranged in an array. It can be understood that the memory may include an address latch module, a timing generation module, a data buffer module, a memory circuit module, and the like, where the memory circuit module stores information by using the memory unit provided in the first aspect of the present application, so that the memory has the advantage of improving the memory driving capability while not increasing the size of the memory.

In a seventh aspect of the present application, there is provided an electronic device comprising a memory and a processor for executing data and/or programs stored in the memory, the memory comprising a memory circuit comprising at least one memory cell array, each memory cell array comprising a plurality of memory cells arranged in an array. It can be understood that the memory in the electronic device adopts the memory unit provided in the first aspect of the present application to store information, so that the electronic device improves the driving capability of the memory unit in the electronic device without increasing the size of the device.

An eighth aspect of the present application provides a method for manufacturing a memory cell based on spin-orbit torque, as shown in fig. 7, comprising:

s201: forming a first transistor and a pair of second transistors on a substrate under the same etching process; wherein each transistor comprises two non-control poles and a control pole;

s202: coupling a non-control electrode of each second transistor with one of the non-control electrodes of the first transistors to form a node, coupling the other non-control electrode of each second transistor to a common bit line, coupling the control electrode thereof with a word line, and coupling the control electrode of the first transistor with an enhanced write word line;

s203: sequentially stacking a spin coupling layer, a free layer, a barrier layer and a fixed layer on the substrate, wherein the spin coupling layer, the free layer, the barrier layer and the fixed layer form a magnetic tunnel junction;

s204: one end of the spin coupling layer is coupled with one of the nodes, the other end is coupled with a common source line, the fixed layer is coupled with the other node, and the control electrode of the first transistor is coupled with the enhanced word line.

The application provides a manufacturing method of a memory cell based on spin orbit torque, which is characterized in that a memory cell is formed by manufacturing three transistors and a spin orbit torque magnetic memory device with a three-port magnetic tunnel junction on a substrate.

The principles and embodiments of the present application have been described in detail with reference to specific examples, which are provided to facilitate understanding of the method and core ideas of the present application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

Claims (11)

1. A spin-orbit torque based memory cell, comprising:

a first transistor and a pair of second transistors; wherein each transistor comprises two non-control poles and a control pole, one non-control pole of each second transistor is respectively coupled with one non-control pole of the first transistor and forms a node, the other non-control pole of each second transistor is coupled to a common bit line, the control pole of the second transistor is coupled with a word line, and the control pole of the first transistor is coupled with an enhanced write word line; and

the magnetic tunnel junction comprises a spin coupling layer, a free layer, a barrier layer and a fixed layer which are sequentially stacked, wherein one end of the spin coupling layer is coupled with one node, the other end of the spin coupling layer is coupled with a common source line, and the fixed layer is coupled with the other node, the control electrode of the first transistor and the enhanced word line.

2. The spin-orbit torque based memory unit of claim 1, wherein the word line comprises a read word line coupled to the control electrode of one of the second transistors and a write word line coupled to the control electrode of the other of the second transistors.

3. The spin-orbit torque based memory unit of claim 1, wherein the first transistor is one of an NMOS transistor and a PMOS transistor.

4. The spin-orbit torque based memory unit of claim 1, wherein each of the second transistors is one of an NMOS transistor and a PMOS transistor.

5. A spin-orbit-torque-based memory cell array comprising a plurality of memory cells arranged in an array, each memory cell comprising:

a first transistor and a pair of second transistors; wherein each transistor comprises two non-control poles and a control pole, one non-control pole of each second transistor is respectively coupled with one non-control pole of the first transistor and forms a node, the other non-control pole of each second transistor is coupled to a common bit line, the control pole of the second transistor is coupled with a word line, and the control pole of the first transistor is coupled with an enhanced write word line; and

the magnetic tunnel junction comprises a spin coupling layer, a free layer, a barrier layer and a fixed layer which are sequentially stacked, wherein one end of the spin coupling layer is coupled with one node, the other end of the spin coupling layer is coupled with a common source line, and the fixed layer is coupled with the other node, the control electrode of the first transistor and the enhanced word line.

6. A memory circuit comprising at least one memory cell array, each memory cell array comprising a plurality of memory cells arranged in an array, each memory cell comprising:

a first transistor and a pair of second transistors; wherein each transistor comprises two non-control poles and a control pole, one non-control pole of each second transistor is respectively coupled with one non-control pole of the first transistor and forms a node, the other non-control pole of each second transistor is coupled to a common bit line, the control pole of the second transistor is coupled with a word line, and the control pole of the first transistor is coupled with an enhanced write word line; and

the magnetic tunnel junction comprises a spin coupling layer, a free layer, a barrier layer and a fixed layer which are sequentially stacked, wherein one end of the spin coupling layer is coupled with one node, the other end of the spin coupling layer is coupled with a common source line, and the fixed layer is coupled with the other node, the control electrode of the first transistor and the enhanced word line.

7. A memory comprising a memory circuit, the memory circuit comprising at least one memory cell array, each memory cell array comprising a plurality of memory cells arranged in an array, each memory cell comprising:

a first transistor and a pair of second transistors; wherein each transistor comprises two non-control poles and a control pole, one non-control pole of each second transistor is respectively coupled with one non-control pole of the first transistor and forms a node, the other non-control pole of each second transistor is coupled to a common bit line, the control pole of the second transistor is coupled with a word line, and the control pole of the first transistor is coupled with an enhanced write word line; and

the magnetic tunnel junction comprises a spin coupling layer, a free layer, a barrier layer and a fixed layer which are sequentially stacked, wherein one end of the spin coupling layer is coupled with one node, the other end of the spin coupling layer is coupled with a common source line, and the fixed layer is coupled with the other node, the control electrode of the first transistor and the enhanced word line.

8. An electronic device comprising a memory and a processor for executing data and/or programs stored in the memory, the memory comprising a memory circuit comprising at least one array of memory cells, each array of memory cells comprising a plurality of array-arranged memory cells, each memory cell comprising:

a first transistor and a pair of second transistors; wherein each transistor comprises two non-control poles and a control pole, one non-control pole of each second transistor is respectively coupled with one non-control pole of the first transistor and forms a node, the other non-control pole of each second transistor is coupled to a common bit line, the control pole of the second transistor is coupled with a word line, and the control pole of the first transistor is coupled with an enhanced write word line; and

the magnetic tunnel junction comprises a spin coupling layer, a free layer, a barrier layer and a fixed layer which are sequentially stacked, wherein one end of the spin coupling layer is coupled with one node, the other end of the spin coupling layer is coupled with a common source line, and the fixed layer is coupled with the other node, the control electrode of the first transistor and the enhanced word line.

9. A method of writing to a spin-orbit torque based memory cell, wherein the memory cell is as claimed in any one of claims 1 to 4, comprising:

accessing a first voltage to a source line coupled to the spin-coupling layer of the tunnel junction;

accessing a second voltage to a bit line coupled to one of the non-control electrodes of the second transistor in the memory cell;

control voltages are introduced to the write word line, the read word line, and the enhancement word line to control the spin coupling layer of the magnetic tunnel junction in the memory cell to conduct a set direction current, the set direction current being determined based on a voltage difference between the first voltage and the second voltage.

10. A method of reading a spin-orbit torque based memory cell, wherein the memory cell is as claimed in any one of claims 1 to 4, comprising:

accessing a third voltage to a source line coupled to the spin-coupling layer of the memory cell magnetic tunnel junction;

accessing a fourth voltage to a bit line coupled to one of the non-control electrodes of the second transistor in the memory cell;

introducing a control voltage to the read word line, and acquiring voltage value information and current value information of the magnetic tunnel junction of the memory cell, wherein the voltage value information is determined based on the differential pressure of the third voltage and the fourth voltage;

and determining the storage information in the storage unit according to the voltage value information and the current value information.

11. A method of fabricating a memory cell based on spin-orbit torque, comprising:

forming a first transistor and a pair of second transistors on a substrate under the same etching process; wherein each transistor comprises two non-control poles and a control pole;

coupling a non-control electrode of each second transistor with one of the non-control electrodes of the first transistors to form a node, coupling the other non-control electrode of each second transistor to a common bit line, coupling the control electrode thereof with a word line, and coupling the control electrode of the first transistor with an enhanced write word line;

sequentially stacking a spin coupling layer, a free layer, a barrier layer and a fixed layer on the substrate, wherein the spin coupling layer, the free layer, the barrier layer and the fixed layer form a magnetic tunnel junction;

one end of the spin coupling layer is coupled with one of the nodes, the other end is coupled with a common source line, the fixed layer is coupled with the other node, and the control electrode of the first transistor is coupled with the enhanced word line.