CN116841630A - Control method and device for server frequency, computer equipment and storage medium - Google Patents
Control method and device for server frequency, computer equipment and storage medium Download PDFInfo
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- 230000015654 memory Effects 0.000 claims abstract description 32
- 230000004048 modification Effects 0.000 claims description 13
- 238000012986 modification Methods 0.000 claims description 13
- 230000009286 beneficial effect Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000004891 communication Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 2
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4403—Processor initialisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
Abstract
The invention relates to the technical field of servers, and discloses a method and a device for controlling server frequency, computer equipment and a storage medium, wherein the method for controlling the server frequency comprises the following steps: modifying the historical clock output frequency of the clock generator to obtain a target clock output frequency, wherein the target clock output frequency is larger than the historical clock output frequency; modifying the historical clock output frequency in a clock configuration file into a target clock output frequency, wherein the clock configuration file is positioned in the electrically erasable programmable read-only memory; controlling the basic input and output system to start; judging whether the basic input/output system is started successfully or not; if the basic input and output system is started successfully, the server frequency setting is judged to be completed. The invention realizes the control of the frequency without external manual intervention.
Description
Technical Field
The present invention relates to the field of server technologies, and in particular, to a method and apparatus for controlling server frequency, a computer device, and a storage medium.
Background
A server is a special purpose computer that provides a certain service to a Client (Client) in a network environment, and is installed with a network operating system and various server application system software. The server has high-speed CPU operation capability, long-time reliable operation capability, strong external data throughput capability and better expansibility.
Along with popularization of cloud computing, artificial intelligence and the like which require a large amount of computing force, the overall performance requirement on the server is higher and higher, and the frequency of a central processor of the server also meets the use requirement.
At present, according to the working frequency requirement of a central processing unit of a server and the requirement of expansion bus protocol of peripheral expansion bus equipment of the server, the clock frequency provided for the central processing unit and the expansion bus by a server main board is 100Mhz, and the control of the frequency can not be realized under the condition of no external manual intervention.
Disclosure of Invention
In view of the above, the present invention provides a method, apparatus, computer device and storage medium for controlling a server frequency, so as to solve the problem that the control of the frequency can not be achieved without external manual intervention.
In a first aspect, the present invention provides a method for controlling a server frequency, including: modifying the historical clock output frequency of the clock generator to obtain a target clock output frequency, wherein the target clock output frequency is larger than the historical clock output frequency; modifying the historical clock output frequency in a clock configuration file into a target clock output frequency, wherein the clock configuration file is positioned in the electrically erasable programmable read-only memory; controlling the basic input and output system to start; judging whether the basic input/output system is started successfully or not; if the basic input and output system is started successfully, the server frequency setting is judged to be completed.
The beneficial effects are that: the invention modifies the historical clock output frequency of the clock generator into the target clock output frequency by modifying the historical clock output frequency of the clock generator, and the target clock output frequency is larger than the historical clock output frequency. And controlling the starting of the basic input output system, wherein when the starting of the basic input output system is completed, the server main board can work normally under the current frequency, so that whether the basic input output system is started successfully is judged, and if the starting of the basic input output system is successful, the target clock output frequency can be normally used, the completion of the frequency setting of the server is judged. The invention modifies the historical clock output frequency of the clock generator, modifies the historical clock output frequency in the clock configuration file, controls the starting of the basic input output system, confirms that the server main board can normally work under the target clock output frequency, and realizes the control of the server frequency without external manual intervention.
In an alternative embodiment, the historical clock output frequency of the clock generator is read; and configuring a clock generator register, and increasing a preset frequency on the historical clock output frequency to obtain a target clock output frequency.
The beneficial effects are that: the clock generator register is configured to increase the preset frequency on the historical clock output frequency to obtain the target clock output frequency, so that when the output frequency needs to be modified into the historical clock output frequency, the preset frequency is subtracted from the target clock output frequency to obtain the historical clock output frequency.
In an alternative embodiment, the boot success information is received; controlling a clock generator to read a clock configuration file; obtaining a target clock output frequency from a clock configuration file; the control clock generator outputs a target clock output frequency to cause the server to operate at the target clock output frequency.
The beneficial effects are that: after the output frequency of the server is set as the target clock output frequency, the server is controlled to start up, the successful information of start-up is received, the clock generator is controlled to read the clock configuration file, the target clock output frequency is obtained from the clock configuration file, and the clock generator is controlled to output the target clock output frequency so that the server can operate according to the target clock output frequency.
In an alternative embodiment, if the bios fails to start, the clock output frequency is reset so that the server operates at the historical clock output frequency.
The beneficial effects are that: if the basic input/output system fails to start, the server main board can not work normally under the target clock output frequency, so that the clock output frequency is reset, and the clock output frequency is set as the historical clock output frequency again, so that the server operates according to the historical clock output frequency.
In an alternative embodiment, the target clock output frequency of the clock generator is read; configuring a clock generator register, and subtracting a preset frequency from a target clock output frequency to obtain a historical clock output frequency; modifying the target clock output frequency in the clock configuration file to a historical clock output frequency; receiving successful startup information; controlling a clock generator to read the historical clock output frequency in the clock configuration file; the clock generator is controlled to output a historical clock output frequency to cause the server to operate at the historical frequency.
In an alternative embodiment, the power-on success information is received before modifying the historical clock output frequency of the clock generator to obtain the target clock output frequency; the control clock generator reads the historical clock output frequency in the clock configuration file and outputs the historical clock output frequency.
The beneficial effects are that: when the server is powered on for the first time, the server receives the successful startup information, controls the clock generator to read the historical clock output frequency in the clock configuration file and output the historical clock output frequency, operates according to the historical clock output frequency, and then modifies the output frequency on the basis of the historical clock output frequency.
In an alternative implementation mode, judging whether a notification message sent by a basic input/output system is received or not; if a notification message sent by the basic input/output system is received, judging that the basic input/output system is started successfully; and if the notification message sent by the basic input/output system is not received, judging that the basic input/output system fails to start.
The beneficial effects are that: a data path is arranged between the basic input output system and the baseboard management controller, if the basic input output system is started successfully, the baseboard management controller receives the notification message sent by the basic input output system, and if the basic input output system is failed to start, the baseboard management controller does not receive the notification message sent by the basic input output system.
In an alternative embodiment, the boot success information is received; the control clock generator reads the historical clock output frequency in the clock configuration file and outputs the historical clock output frequency; configuring a clock generator register, and increasing a preset frequency on the historical clock output frequency to obtain a target clock output frequency, wherein the target clock output frequency is larger than the historical clock output frequency; modifying the historical clock output frequency in a clock configuration file into a target clock output frequency, wherein the clock configuration file is positioned in the electrically erasable programmable read-only memory; controlling the basic input and output system to start; judging whether the basic input/output system is started successfully or not; if the basic input and output system is started successfully, judging that the frequency setting of the server is completed; receiving successful startup information; controlling a clock generator to read a clock configuration file; obtaining a target clock output frequency from a clock configuration file; the control clock generator outputs a target clock output frequency to cause the server to operate at the target clock output frequency.
The beneficial effects are that: when the server is powered on for the first time, receiving the successful information of startup, controlling the clock generator to read the historical clock output frequency in the clock configuration file and output the historical clock output frequency, firstly operating according to the historical clock output frequency, then modifying the output frequency on the basis of the historical clock output frequency, controlling the clock generator to read the historical clock output frequency in the clock configuration file and output the historical clock output frequency; the clock generator register is configured, the preset frequency is increased on the historical clock output frequency to obtain the target clock output frequency, and the target clock output frequency is larger than the historical clock output frequency. And controlling the starting of the basic input output system, wherein when the starting of the basic input output system is completed, the server main board can work normally under the current frequency, so that whether the basic input output system is started successfully is judged, and if the starting of the basic input output system is successful, the target clock output frequency can be normally used, the completion of the frequency setting of the server is judged. Receiving the successful startup information, controlling the clock generator to read the clock configuration file, acquiring the target clock output frequency from the clock configuration file, controlling the clock generator to output the target clock output frequency so that the server operates according to the target clock output frequency, controlling the server to start up after the output frequency of the server is set to the target clock output frequency, receiving the successful startup information, controlling the clock generator to read the clock configuration file, acquiring the target clock output frequency from the clock configuration file, and controlling the clock generator to output the target clock output frequency so that the server operates according to the target clock output frequency. The invention modifies the historical clock output frequency of the clock generator, modifies the historical clock output frequency in the clock configuration file, controls the starting of the basic input output system, confirms that the server main board can normally work under the target clock output frequency, and realizes the control of the server frequency without external manual intervention.
In a second aspect, the present invention provides a control device for a server frequency, including: the register modification module is used for modifying the historical clock output frequency of the clock generator to obtain a target clock output frequency, wherein the target clock output frequency is larger than the historical clock output frequency; the clock configuration file modification module is used for modifying the historical clock output frequency in the clock configuration file into the target clock output frequency, and the clock configuration file is positioned in the electrically erasable programmable read-only memory; the restarting module is used for controlling the starting of the basic input/output system; the judging module is used for judging whether the basic input/output system is started successfully or not; and the judging module is used for judging that the frequency setting of the server is finished according to the success of starting the basic input/output system.
The beneficial effects are that: the register modification module modifies the historical clock output frequency of the clock generator into the target clock output frequency by modifying the historical clock output frequency of the clock generator, and the target clock output frequency is larger than the historical clock output frequency. The restarting module controls the basic input and output system to start, when the basic input and output system is started, the server main board can work normally under the current frequency, so that the judging module judges whether the basic input and output system is started successfully, if the basic input and output system is started successfully, the target clock output frequency can be normally used, and the judging module judges that the server frequency setting is completed. The invention modifies the historical clock output frequency of the clock generator, modifies the historical clock output frequency in the clock configuration file, controls the starting of the basic input output system, confirms that the server main board can normally work under the target clock output frequency, and realizes the control of the server frequency without external manual intervention.
In a third aspect, the present invention provides a computer device comprising: the processor executes the computer instructions, thereby executing the method for controlling the server frequency according to the first aspect or any one of the embodiments corresponding to the first aspect.
In a fourth aspect, the present invention provides a computer-readable storage medium having stored thereon computer instructions for causing a computer to execute the method for controlling server frequency of the first aspect or any one of the embodiments corresponding thereto.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flow chart of a method for controlling a server frequency according to an embodiment of the present invention;
FIG. 2 is a flow chart of another method for controlling server frequency according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a clock generator according to an embodiment of the invention;
FIG. 4 is a flowchart of a basic input/output system for determining whether a start-up is successful according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of the connection between a platform path controller and a baseboard management controller according to an embodiment of the invention;
FIG. 6 is a flow chart of a method for controlling server frequency according to an embodiment of the present invention;
fig. 7 is a block diagram of a control apparatus of a server frequency according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The embodiment of the invention provides a control method of server frequency, which achieves the effect of controlling the frequency without external manual intervention by modifying the historical clock output frequency of a clock generator.
According to an embodiment of the present invention, there is provided an embodiment of a method for controlling a server frequency, it being noted that the steps shown in the flowcharts of the drawings may be performed in a computer system such as a set of computer executable instructions, and that although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that herein.
In this embodiment, a method for controlling a server frequency is provided, which may be used in the server described above, and fig. 1 is a flowchart of a method for controlling a server frequency according to an embodiment of the present invention, as shown in fig. 1, where the flowchart includes the following steps:
step S101, modifying the historical clock output frequency of the clock generator to obtain a target clock output frequency, wherein the target clock output frequency is larger than the historical clock output frequency.
The default historical clock output frequency is 100MHz, and the historical clock output frequency is the basic frequency of the clock generator.
In the specific implementation, the modified target clock output frequency is greater than the historical clock output frequency, so that the server operates according to the target clock output frequency, and the target clock output frequency is greater than the default clock output frequency, so that the embodiment of the invention can realize the over-frequency operation of the server, thereby exerting the limit performance of the CPU and the peripheral expansion bus equipment of the server.
Illustratively, the historical clock output frequency is 100MHz and the target clock output frequency is 120MHz.
Step S102, the historical clock output frequency in the clock configuration file is modified to the target clock output frequency, and the clock configuration file is located in the EEPROM.
The EEPROM is a Memory chip which does not lose data after power failure, and is stored with a clock configuration file which is used for storing the output frequency of the clock generator.
And step S103, controlling the starting of the basic input/output system.
The basic input output system (Basic Input Output System, BIOS) is controlled to start, namely, the baseboard management controller resets the basic input output system to realize the starting of the basic input output system.
Step S104, judging whether the basic input/output system is started successfully.
In the embodiment of the invention, whether the basic input/output system is started successfully is judged by judging whether the notification message sent by the basic input/output system is received, if the notification message sent by the basic input/output system is received, the starting is successful, and if the notification message sent by the basic input/output system is not received, the starting is failed.
Step S105, if the BIOS is started successfully, the server frequency setting is judged to be completed.
Step S106, if the basic input/output system fails to start, resetting the clock output frequency to enable the server to operate according to the historical clock output frequency.
According to the control method for the server frequency, the historical clock output frequency of the clock generator is modified to be the target clock output frequency by modifying the historical clock output frequency of the clock generator, and the target clock output frequency is larger than the historical clock output frequency. And controlling the starting of the basic input output system, wherein when the starting of the basic input output system is completed, the server main board can work normally under the current frequency, so that whether the basic input output system is started successfully is judged, and if the starting of the basic input output system is successful, the target clock output frequency can be normally used, the completion of the frequency setting of the server is judged. The invention modifies the historical clock output frequency of the clock generator, modifies the historical clock output frequency in the clock configuration file, controls the starting of the basic input output system, confirms that the server main board can normally work under the target clock output frequency, and realizes the control of the server frequency without external manual intervention.
In this embodiment, a method for controlling a server frequency is provided, which may be used in the server described above, and fig. 2 is a flowchart of another method for controlling a server frequency according to an embodiment of the present invention, as shown in fig. 2, where the flowchart includes the following steps:
in step S201, the historical clock output frequency of the clock generator is modified to obtain a target clock output frequency, where the target clock output frequency is greater than the historical clock output frequency. Please refer to step S101 in the embodiment shown in fig. 1 in detail, which is not described herein.
Specifically, the step 201 includes:
in step S2021, the historical clock output frequency of the clock generator is read.
Wherein the clock frequency output by the clock generator is a historical clock output frequency before modifying the output frequency of the clock generator.
In step S2022, the clock generator register is configured to increase the preset frequency to the historical clock output frequency, so as to obtain the target clock output frequency.
Exemplary, if the historical clock output frequency is F (-1) If the preset frequency is Δf, the target clock output frequency fn=f (-1) +Δf, wherein the value of Δf can be customized according to the difference of the target clock output frequency, if the historical clock output frequency is F (-1) The preset frequency deltaf is 20MHz, and the output frequency of the target clock is 120MHz.
In the embodiment of the invention, the preset frequency is added to the historical clock output frequency by configuring the clock generator register to obtain the target clock output frequency, so that when the output frequency needs to be modified to be the historical clock output frequency, the preset frequency is subtracted from the target clock output frequency to obtain the historical clock output frequency.
In some alternative embodiments, before modifying the historical clock output frequency of the clock generator to obtain the target clock output frequency, the power-on success information is received, and the clock generator is controlled to read the historical clock output frequency in the clock configuration file and output the historical clock output frequency.
In the embodiment of the invention, when the server is powered on for the first time, the server receives the successful information of startup, controls the clock generator to read the historical clock output frequency in the clock configuration file and output the historical clock output frequency, operates according to the historical clock output frequency first, and then modifies the output frequency on the basis of the historical clock output frequency.
Step S202, the historical clock output frequency in the clock configuration file is modified to the target clock output frequency, and the clock configuration file is located in the EEPROM. Please refer to step S102 in the embodiment shown in fig. 1 in detail, which is not described herein.
And step S203, controlling the starting of the basic input/output system. Please refer to step S103 in the embodiment shown in fig. 1 in detail, which is not described herein.
Step S204, judging whether the basic input/output system is started successfully. Please refer to step S104 in the embodiment shown in fig. 1 in detail, which is not described herein.
In step S205, if the bios is started successfully, it is determined that the server frequency setting is completed. Please refer to step S105 in the embodiment shown in fig. 1 in detail, which is not described herein.
As shown in fig. 3, a schematic diagram of a Clock Generator is shown, and a first Clock input port, a second Clock input port and a third Clock input port are provided on the Clock Generator (CLK Gen), where the Clock input ports can receive different Clock signals, and in an exemplary embodiment of the present invention, the crystal is connected to the first Clock input port through 50 megaclock signals.
The first clock output port in fig. 3 outputs the first output signal, the second clock output port outputs the second output signal, the third clock output port outputs the third output signal, and ten clock output ports are provided on CLK Gen for output signals.
Three pins, pin 0, pin 1, pin 2, are provided on CLK Gen in fig. 3, and are connected to complex programmable logic devices (Complex Programmable Logic Device, CPLD) through first, second, and third signals, respectively.
The first interface and the second interface are respectively connected with a baseboard management controller (Baseboard Management Controller, BMC), the first interface and the second interface of the BMC are respectively connected with an electrically erasable programmable read-Only Memory (EEPROM), and clock configuration files are stored in the EEPROM.
When the motherboard is powered on for the first time, the clock configuration file in the EEPROM configures the clock output of the CLK Gen to be 100MHz. The BMC configures the registers of the CLK Gen through the I2C interface, thereby configuring the clock output frequency of the CLK Gen. Meanwhile, the BMC can modify the file content in the EEPROM through the I2C interface.
Step S206, receiving the successful information of starting up.
In step S207, the clock generator is controlled to read the clock configuration file.
Step S208, obtaining the target clock output frequency from the clock configuration file.
In step S209, the clock generator is controlled to output the target clock output frequency, so that the server operates according to the target clock output frequency.
In the embodiment of the invention, after the output frequency of the server is set as the target clock output frequency, the server is controlled to start, the successful information of starting is received, the clock generator is controlled to read the clock configuration file, the target clock output frequency is obtained from the clock configuration file, and the clock generator is controlled to output the target clock output frequency so that the server operates according to the target clock output frequency.
Step S2010, if the BIOS fails to start, resetting the clock output frequency to make the server operate according to the historical clock output frequency.
Specifically, the step S2010 includes:
in step S20101, the target clock output frequency of the clock generator is read.
In step S20102, a clock generator register is configured, and a preset frequency is subtracted from the target clock output frequency to obtain a historical clock output frequency.
For example, if the target clock output frequency Fn, the preset frequency Δf, the historical clock output frequency F (-1) ＝Fn-Δf。
In step S20103, the target clock output frequency in the clock configuration file is modified to the historical clock output frequency.
Wherein the target clock output frequency Fn is modified to a historical clock output frequency F (-1) ＝Fn-Δf。
Step S20104, receiving the power-on success information.
In step S20105, the clock generator is controlled to read the historical clock output frequency in the clock configuration file.
In step S20106, the clock generator is controlled to output the history clock output frequency so that the server operates according to the history frequency.
In the embodiment of the invention, if the basic input/output system fails to start, the server main board cannot normally work under the target clock output frequency, so that the clock output frequency is reset, and the clock output frequency is set as the historical clock output frequency again, so that the server operates according to the historical clock output frequency.
In this embodiment, a method for controlling server frequency is provided, which may be used in the server described above, and fig. 4 is a flowchart for determining whether the bios is started successfully according to an embodiment of the present invention, that is, step S104 in fig. 1, as shown in fig. 4, where the flowchart includes the following steps:
step S4041, it is determined whether a notification message sent by the bios is received.
As shown in fig. 5, a schematic diagram of connection between a platform path controller (Platform Controller Hub, PCH) and a baseboard management controller is shown, the two are connected through data communication, a data path is designed between the PCH and the BMC by a server motherboard, the data path can be SPI, eSPI, i c or other data buses, or can be a data path formed by single-ended signals, through which, if a basic input output system (Basic Input Output System, BIOS) is started successfully, the starting process is completed successfully, and the BIOS sends a notification message of completion of the starting to the BMC; if the BIOS fails to start, the BIOS does not send a notification message to the BMC to complete the start, and the start failure includes a failure to start or an incomplete start process.
Step S4042, if the notification message sent by the bios is received, it is determined that the bios is started successfully.
In step S4043, if the notification message sent by the bios is not received, it is determined that the bios fails to start.
Step S404 in fig. 4 is step S104 in fig. 1.
In this embodiment, a method for controlling a server frequency is provided, which may be used in the server described above, and fig. 6 is a flowchart of a method for controlling a server frequency according to another embodiment of the present invention, as shown in fig. 6, where the flowchart includes the following steps:
step S601, receiving the startup success information.
In step S602, the clock generator is controlled to read the historical clock output frequency in the clock configuration file and output the historical clock output frequency.
In step S603, a clock generator register is configured to increase a preset frequency on the historical clock output frequency to obtain a target clock output frequency, where the target clock output frequency is greater than the historical clock output frequency.
In step S604, the historical clock output frequency in the clock configuration file is modified to the target clock output frequency, and the clock configuration file is located in the eeprom.
Step S605, control the basic input output system to start.
Step S606, judging whether the basic input/output system is started successfully.
In step S607, if the bios is started successfully, it is determined that the server frequency setting is completed.
Step S608, receiving the power-on success information.
In step S609, the clock generator is controlled to read the clock configuration file.
In step S6010, the target clock output frequency is obtained from the clock configuration file.
In step S6011, the clock generator is controlled to output the target clock output frequency so that the server operates according to the target clock output frequency.
According to the control method for the server frequency, when the server is powered on for the first time, the server receives the successful startup information, controls the clock generator to read the historical clock output frequency in the clock configuration file and output the historical clock output frequency, firstly operates according to the historical clock output frequency, then modifies the output frequency on the basis of the historical clock output frequency, and controls the clock generator to read the historical clock output frequency in the clock configuration file and output the historical clock output frequency; the clock generator register is configured, the preset frequency is increased on the historical clock output frequency to obtain the target clock output frequency, and the target clock output frequency is larger than the historical clock output frequency. And controlling the starting of the basic input output system, wherein when the starting of the basic input output system is completed, the server main board can work normally under the current frequency, so that whether the basic input output system is started successfully is judged, and if the starting of the basic input output system is successful, the target clock output frequency can be normally used, the completion of the frequency setting of the server is judged. Receiving the successful startup information, controlling the clock generator to read the clock configuration file, acquiring the target clock output frequency from the clock configuration file, controlling the clock generator to output the target clock output frequency so that the server operates according to the target clock output frequency, controlling the server to start up after the output frequency of the server is set to the target clock output frequency, receiving the successful startup information, controlling the clock generator to read the clock configuration file, acquiring the target clock output frequency from the clock configuration file, and controlling the clock generator to output the target clock output frequency so that the server operates according to the target clock output frequency. The invention modifies the historical clock output frequency of the clock generator, modifies the historical clock output frequency in the clock configuration file, controls the starting of the basic input output system, confirms that the server main board can normally work under the target clock output frequency, and realizes the control of the server frequency without external manual intervention.
The embodiment also provides a device for controlling the server frequency, which is used for implementing the foregoing embodiments and preferred embodiments, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
The present embodiment provides a control device for server frequency, as shown in fig. 7, including:
the register modification module 701 is configured to modify a historical clock output frequency of the clock generator to obtain a target clock output frequency, where the target clock output frequency is greater than the historical clock output frequency.
The clock configuration file modification module 702 is configured to modify a historical clock output frequency in a clock configuration file to a target clock output frequency, where the clock configuration file is located in the eeprom.
A restarting module 703, configured to control the bios to start.
And a judging module 704, configured to judge whether the basic input/output system is started successfully.
And the judging module 705 is configured to judge that the server frequency setting is completed according to the success of the starting of the basic input output system.
In some alternative embodiments, register modification module 701 includes:
and the reading unit is used for reading the historical clock output frequency of the clock generator.
And the modifying unit is used for configuring a clock generator register, and increasing a preset frequency on the historical clock output frequency to obtain a target clock output frequency.
In some alternative embodiments, the decision module 705 further includes:
if the basic input and output system fails to start, resetting the clock output frequency so that the server operates according to the historical clock output frequency.
In some alternative embodiments, register modification module 701 further comprises:
and the reading unit is used for reading the target clock output frequency of the clock generator.
And the modifying unit is used for configuring a clock generator register, and subtracting the preset frequency from the target clock output frequency to obtain the historical clock output frequency.
In some alternative embodiments, the clock profile modification module 702 further includes:
the target clock output frequency in the clock configuration file is modified to a historical clock output frequency.
In some alternative embodiments, the determining module 704 further includes:
and the judging unit is used for judging whether the notification message sent by the basic input and output system is received or not.
And the judging unit is used for judging that the basic input/output system is started successfully according to the received notification message sent by the basic input/output system, and judging that the basic input/output system is started failed according to the fact that the notification message sent by the basic input/output system is not received.
In the control device for server frequency provided in the embodiment of the present invention, the register modification module 701 modifies the historical clock output frequency of the clock generator into the target clock output frequency by modifying the historical clock output frequency of the clock generator, and the target clock output frequency is greater than the historical clock output frequency. The restarting module 703 controls the bios to start, when the bios start is completed, it indicates that the server motherboard can work normally under the current frequency, so the judging module 704 judges whether the bios start is successful, if the bios start is successful, which indicates that the target clock output frequency can be used normally, the judging module 705 judges that the server frequency setting is completed. The invention modifies the historical clock output frequency of the clock generator, modifies the historical clock output frequency in the clock configuration file, controls the starting of the basic input output system, confirms that the server main board can normally work under the target clock output frequency, and realizes the control of the server frequency without external manual intervention.
Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.
The control means of the server frequency in this embodiment are presented in the form of functional units, here referred to as ASIC (Application Specific Integrated Circuit ) circuits, processors and memories executing one or more software or fixed programs, and/or other devices that can provide the above described functions.
The embodiment of the invention also provides computer equipment, which is provided with the control device of the server frequency shown in the figure 7.
Referring to fig. 8, fig. 8 is a schematic structural diagram of a computer device according to an alternative embodiment of the present invention, as shown in fig. 8, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 8.
The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.
Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform the methods shown in implementing the above embodiments.
The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.
The computer device also includes a communication interface 30 for the computer device to communicate with other devices or communication networks.
The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.
Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.
Claims (11)
1. A method for controlling server frequency, which is applied to a motherboard management chip, the method comprising:
modifying the historical clock output frequency of a clock generator to obtain a target clock output frequency, wherein the target clock output frequency is greater than the historical clock output frequency;
modifying the historical clock output frequency in a clock configuration file to the target clock output frequency, wherein the clock configuration file is positioned in an electrically erasable programmable read-only memory;
controlling the basic input and output system to start;
judging whether the basic input/output system is started successfully or not;
and if the basic input and output system is started successfully, judging that the server frequency setting is completed.
2. The method of claim 1, wherein modifying the historical clock output frequency of the clock generator to obtain the target clock output frequency comprises:
Reading a historical clock output frequency of the clock generator;
and configuring a clock generator register, and increasing a preset frequency on the historical clock output frequency to obtain the target clock output frequency.
3. The method according to claim 1 or 2, wherein after said determining that the server frequency setting is completed if the basic input output system is started successfully, the method further comprises:
receiving successful startup information;
controlling the clock generator to read a clock configuration file;
obtaining a target clock output frequency from the clock configuration file;
and controlling the clock generator to output the target clock output frequency so that the server operates according to the target clock output frequency.
4. The method according to claim 1 or 2, wherein the determining whether the basic input output system is started successfully, the method further comprising:
and if the starting of the basic input and output system fails, resetting the clock output frequency so that the server operates according to the historical clock output frequency.
5. The method of claim 4, wherein resetting the clock output frequency to cause the server to operate at the historical clock output frequency comprises:
Reading a target clock output frequency of the clock generator;
configuring a clock generator register, and subtracting a preset frequency from the target clock output frequency to obtain the historical clock output frequency;
modifying the target clock output frequency in a clock configuration file to the historical clock output frequency;
receiving successful startup information;
controlling the clock generator to read the historical clock output frequency in the clock configuration file;
and controlling the clock generator to output the historical clock output frequency so that the server operates according to the historical frequency.
6. The method of claim 1 or 2, wherein prior to modifying the historical clock output frequency of the clock generator to obtain the target clock output frequency, the method further comprises:
receiving successful startup information;
and controlling the clock generator to read the historical clock output frequency in the clock configuration file and outputting the historical clock output frequency.
7. The method according to claim 1 or 2, wherein determining whether the basic input output system is started up successfully comprises:
judging whether a notification message sent by the basic input/output system is received or not;
If the notification message sent by the basic input/output system is received, judging that the basic input/output system is started successfully;
and if the notification message sent by the basic input/output system is not received, judging that the basic input/output system fails to start.
8. The method according to claim 1 or 2, characterized in that the method comprises:
receiving successful startup information;
controlling the clock generator to read the historical clock output frequency in the clock configuration file and output the historical clock output frequency;
configuring a clock generator register, and increasing a preset frequency on the historical clock output frequency to obtain a target clock output frequency, wherein the target clock output frequency is larger than the historical clock output frequency;
modifying the historical clock output frequency in a clock configuration file to the target clock output frequency, wherein the clock configuration file is positioned in an electrically erasable programmable read-only memory;
controlling the basic input and output system to start;
judging whether the basic input/output system is started successfully or not;
if the basic input and output system is started successfully, judging that the server frequency setting is completed;
Receiving successful startup information;
controlling the clock generator to read a clock configuration file;
obtaining a target clock output frequency from the clock configuration file;
and controlling the clock generator to output the target clock output frequency so that the server operates according to the target clock output frequency.
9. A control device for server frequency, the device comprising:
the register modification module is used for modifying the historical clock output frequency of the clock generator to obtain a target clock output frequency, and the target clock output frequency is larger than the historical clock output frequency;
the clock configuration file modification module is used for modifying the historical clock output frequency in a clock configuration file into the target clock output frequency, and the clock configuration file is positioned in the electrically erasable programmable read-only memory;
the restarting module is used for controlling the starting of the basic input/output system;
the judging module is used for judging whether the basic input/output system is started successfully or not;
and the judging module is used for judging that the frequency setting of the server is finished according to the successful starting of the basic input/output system.
10. A computer device, comprising:
A memory and a processor, the memory and the processor being communicatively connected to each other, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the method of controlling the frequency of the server of any one of claims 1 to 8.
11. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon computer instructions for causing a computer to execute the control method of the server frequency according to any one of claims 1 to 8.
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| CN202310924704.7A CN116841630A (en) | 2023-07-26 | 2023-07-26 | Control method and device for server frequency, computer equipment and storage medium |
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| CN202310924704.7A CN116841630A (en) | 2023-07-26 | 2023-07-26 | Control method and device for server frequency, computer equipment and storage medium |
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