CN109725940B

CN109725940B - Method for starting computing system and computing system

Info

Publication number: CN109725940B
Application number: CN201711049353.0A
Authority: CN
Inventors: 黄江乐; 张俊; 陈天翔
Original assignee: Huawei Technologies Co Ltd
Current assignee: XFusion Digital Technologies Co Ltd
Priority date: 2017-10-31
Filing date: 2017-10-31
Publication date: 2021-07-09
Anticipated expiration: 2037-10-31
Also published as: CN109725940A

Abstract

The application provides a method for starting a computing system and the computing system, wherein the computing system comprises a main node and at least one slave node, each slave node comprises a processor, a Baseboard Management Controller (BMC) and a Node Controller (NC), the main node comprises a processor, a BMC, an NC and a platform control center (PCH) board, and the method comprises the following steps: the processor in the main node reads the BIOS code of the basic input and output system through the PCH board; the BMC of the master node sends the BIOS code to the BMC of each slave node; or the BMC of each slave node independently updates the BIOS codes in the nonvolatile storage; at startup of the computing system, the processor in each slave node reads the BIOS code directly from non-volatile storage that is suspended by the NC in each slave node. The method for starting the computing system and the computing system can save materials and reduce the space of the whole computer.

Description

Method for starting computing system and computing system

Technical Field

The present application relates to the field of computer technology, and more particularly, to a method and computing system for computing system boot.

Background

When a Cache asymmetric-Non Uniform Memory Access (CC-NUMA) multiprocessor System controlled by a Node Controller (NC) is started, each Node (Node) reads a Basic Input Output System (BIOS) code from a flash Memory of the Node through a Platform Controller Hub (PCH). This requires each node to carry a PCH board itself. The more system nodes, the more PCH boards are needed, thereby causing the problems of increased cost, too much occupied space of the whole machine and the like. Based on this, it is necessary to provide a solution to the above problem.

Disclosure of Invention

The application provides a method for starting a computing system and the computing system, which can reduce the cost and save the space of the whole computer.

In a first aspect, there is provided a method for booting a computing system, the computing system comprising a master node and at least one slave node, each slave node comprising a processor, a baseboard management controller, BMC, and a node controller, NC, the master node comprising a processor, a BMC, NC, and a platform control center, PCH, board, the method comprising:

a processor in the main node reads a Basic Input Output System (BIOS) code through the PCH board;

the master node sends the BIOS codes to the BMC of each slave node through the BMC of the master node;

at startup of the computing system, the processor in each slave node reads the BIOS code directly from non-volatile storage that is hung down by the NC in each slave node.

Optionally, the computing system is a cache asymmetric coherent memory access (CC-NUMA) based system. Optionally, in the embodiment of the present application, the nonvolatile memory may be a flash memory. The nonvolatile storage has the characteristic of nonvolatile.

Optionally, the slave node may also perform a separate upgrade program on the BIOS code in its nonvolatile storage, which is not limited to this.

In the embodiment of the application, the PCH board of the main node is reserved, and the PCH board of the slave node is not needed, so that the cost can be saved, and the material can be reduced. During specific implementation, the master node acquires the BIOS codes through the PCH board, and the slave node directly reads the BIOS codes through the nonvolatile storage hung under the NC board so as to complete the starting process of the system. Optionally, the BMC of the master node may send the BIOS code to the BMC of the slave node, or the BMC of the slave node may separately upgrade the BIOS code in the nonvolatile storage of the slave node, which is not limited herein.

In some possible implementations, before the processor of each slave node reads the BIOS code directly from non-volatile storage that is under the NC in the each slave node at startup of the computing system, the method further comprises:

and the BMC of each slave node writes the BIOS code into the nonvolatile storage corresponding to the slave node.

Specifically, the master node may send the BIOS code to the BMC corresponding to each slave node through an ethernet connection. Correspondingly, the BMC of each slave node writes the BIOS code into the nonvolatile storage corresponding to the slave node.

In some possible implementations, the reading, by the processor in the master node, the BIOS code through the platform controller hub PCH board includes:

and the processor in the main node reads the BIOS code in the nonvolatile storage corresponding to the main node through the PCH board by using a BMC.

In some possible implementations, the non-volatile storage corresponding to each slave node is directly connected to the NC.

In some possible implementations, the method further includes:

and the main node upgrades the BIOS code in the nonvolatile storage corresponding to the main node through the BMC of the main node.

In some possible implementations, the way the processor in each slave node directly reads the BIOS code through the NC is pre-configured.

That is, the computing system may pre-configure the NC with a default access pattern such that a processor in the slave node may access non-volatile storage connected to the NC through the UPI path based on the default access pattern.

In a second aspect, there is provided a computing system comprising:

the system comprises a main node and at least one slave node, wherein each slave node comprises a processor, a Baseboard Management Controller (BMC) and a Node Controller (NC), and the main node comprises a processor, a BMC, an NC and a platform control center (PCH) board;

the processor in the main node is used for reading a Basic Input Output System (BIOS) code through the PCH board;

the master node is used for sending the BIOS codes to the BMC of each slave node through the BMC of the master node;

the processor in each slave node is configured to read the BIOS code directly from non-volatile storage that is suspended by the NC in each slave node at startup of the computing system.

Optionally, the computing system is a cache asymmetric coherent memory access (CC-NUMA) based system.

In the embodiment of the application, the PCH board of the main node is reserved, and the PCH board of the slave node is not needed, so that the cost can be saved, and the material can be reduced. During specific implementation, the master node acquires the BIOS codes through the PCH board, and the slave node directly reads the BIOS codes through the nonvolatile storage hung under the NC board so as to complete the starting process of the system. Optionally, the BMC of the master node may send the BIOS code to the BMC of the slave node, or the BMC of the slave node may separately upgrade the BIOS code in the nonvolatile storage, which is not limited herein.

In some possible implementations, the processor of each slave node is specifically configured to:

writing the BIOS code into the nonvolatile storage corresponding to the slave node through the BMC of each slave node.

In some possible implementations, the processor in the master node is specifically configured to:

and reading the BIOS code in the nonvolatile storage corresponding to the main node through the PCH board by using the BMC.

In some possible implementations, the master node is further to:

upgrading the BIOS code in the nonvolatile storage corresponding to the main node through the BMC of the main node.

In a third aspect, a master node is provided for performing the method of the first aspect or any possible implementation manner of the first aspect. In particular, the master node comprises means or an element for performing the method of the master node of the above first aspect or any possible implementation manner of the first aspect.

In a fourth aspect, a slave node is provided for performing the method of the first aspect described above or any possible implementation manner of the first aspect. In particular, the slave node comprises means or an element for performing the method of the slave node in the first aspect or any possible implementation of the first aspect.

In a fifth aspect, there is provided a computing system arranged to perform the method of the first aspect or any possible implementation manner of the first aspect. The computing system comprises a master node of the third aspect and a slave node of the fourth aspect.

In a sixth aspect, there is provided a computer readable storage medium storing a program for causing a computing system to perform the method of the first aspect, and any of its various implementations.

In a seventh aspect, a computer program product containing instructions is provided, which when run on a computer, causes the computer to perform the method of the first aspect or any possible implementation thereof.

Drawings

FIG. 1 is a schematic block diagram of a CC-NUMA system.

FIG. 2 is a schematic block diagram of a method for computing system boot-up according to an embodiment of the present application.

FIG. 3 is a schematic block diagram of a computing system according to an embodiment of the present application.

Fig. 4 is a schematic flow chart of an example of application of the embodiments of the present application.

FIG. 5 is a schematic block diagram of a computing system according to an embodiment of the present application.

Detailed Description

The technical solution in the present application will be described below with reference to the accompanying drawings.

The technical scheme of the embodiment of the application can be applied to a computing system, such as a computer system based on Cache coherence-Non Uniform Memory Access (CC-NUMA). A cache asymmetric coherent memory access CC-NUMA system may include a plurality of nodes (nodes) including a master Node and a slave Node. At the time of the CC-NUMA System startup, each node needs to read Basic Input Output System (BIOS) code. The BIOS code is a set of programs that are fixed in a nonvolatile memory on a computer motherboard, directly controls the hardware level of the input/output devices in the computer system, and provides a basis for establishing connections between other software programs and the hardware devices. The BIOS is a program executed first after the computer is powered on, and completes functions of initializing, setting, testing, and the like of each hardware device of the system, so as to ensure that the system can normally operate.

FIG. 1 shows a schematic block diagram of a CC-NUMA system. As shown in FIG. 1, the CC-NUMA system may include N nodes. The N nodes are composed of a master node and at least one slave node. Specifically, each node may include n Central Processing Units (CPUs). Each Node has a corresponding Platform Controller Hub (PCH) board, flash memory, Node Controller (NC), and Baseboard Management Controller (BMC). Taking node 1 as an example, when the CC-NUMA system starts, node 1 reads BIOS code of the BIOS through a PCH board to a nonvolatile memory (such as a nonvolatile flash memory norflash) in the node.

If the scheme in the prior art is adopted, each node needs to carry a PCH board, and the BIOS codes are read through the PCH board. In addition, the BIOS codes and the BMC interactively complete the configuration of the CPU and the NC, and the nodes can only realize in-band access to the NC through the UPI in the starting process of the system.

The application proposes a management scheme of a single PCH board, only the PCH board on the main node is reserved, so that the cost is reduced, and the space of the whole machine is saved.

FIG. 2 shows a schematic block diagram of a method 200 for computing system boot-up according to an embodiment of the present application. The computing system comprises a main node and at least one slave node, wherein each slave node comprises a processor, a Baseboard Management Controller (BMC) and a Node Controller (NC), and the main node comprises a processor, a BMC, an NC and a platform control center (PCH) board. As shown in fig. 2, the method 200 includes:

s201, a processor in the main node reads a Basic Input Output System (BIOS) code through a platform controller center (PCH) board. Alternatively, if multiple processors are included in the master node, the BIOS code is read using the master processor. Alternatively, the processor may represent a CPU, such as CPU0 in node 1 of FIG. 1.

The BIOS code may be used for system start-up, system initialization, system boot, upgrade, or test, and the like.

Specifically, the processor in the master node reads the BIOS code in a nonvolatile storage (such as norflash) corresponding to the master node through the PCH board using the BMC of the master node.

S202, the master node sends the BIOS codes to the BMC of each slave node through the BMC of the master node.

Specifically, the BMC of the master node may send the BIOS code to the BMC of the baseboard management controller corresponding to each slave node through an ethernet connection. Correspondingly, the BMC of each slave node writes the BIOS code into the nonvolatile storage corresponding to the slave node. The nonvolatile storage has the characteristic of nonvolatile. Non-volatile storage may also be referred to as non-volatile storage media.

Here, the method for obtaining the BIOS code from the slave node is not limited, and the BIOS code may be distributed to the nonvolatile storage of each slave node through the network after the BMC of the master node is powered on, or the nonvolatile storage of each slave node may be separately upgraded and programmed, which is not limited in the embodiment of the present application.

S203, when the computing system is started, the processor in each slave node directly reads the BIOS codes from the nonvolatile storage hung under the node controller NC in each slave node.

Alternatively, if a plurality of processors are included in the slave node, the processor in the slave node represents a master processor in the slave node. Alternatively, the processor in the slave node may also be a CPU.

Alternatively, the NC may be a chip. Optionally, the non-volatile storage corresponding to each slave node is directly connected to the NC. For example, the non-volatile storage and NC are directly connected through a Serial Peripheral Interface (SPI). It should be understood that the connection between the nonvolatile memory and the NC is not limited to the SPI interface, and may be other possible interfaces, and here, the SPI interface is merely used as an example for description, and the embodiment of the present application is not limited.

For example, a CPU in the slave node reads BIOS instructions through an NC in-band via a User Program Interface (UPI).

Optionally, the processor in each slave node is preconfigured by directly reading the BIOS code through the NC. That is, the NC may be preconfigured with a default access pattern such that a processor in the slave node may access non-volatile storage connected to the NC via the UPI path based on the default access pattern.

Specifically, the processor in the master node reads the BIOS code in the nonvolatile storage in the master node through the PCH board, and the processor in the master node sends the BIOS code to the BMC of the slave node through the BMC of the master node. The BMC of the slave node writes the BIOS code to a non-volatile storage in the slave node. Here, only the PCH board in the master node is reserved in the computing system, and the PCH board in the slave node does not need to be reserved. When the computing system is started, the processor in the slave node directly reads the BIOS code in the nonvolatile storage corresponding to the slave node through the corresponding node controller NC. Therefore, the method for starting the computing system can save cost, reduce materials and save the space of the whole computer.

In the embodiment of the application, the PCH board of the main node is reserved, and the PCH board of the slave node is not needed, so that the cost can be saved, and the material can be reduced. During specific implementation, the master node acquires the BIOS codes through the PCH board, and the slave node directly reads the BIOS codes from the non-volatile storage hung under the NC board so as to complete the starting process of the system.

It should be noted that, in the embodiment of the present application, the number of slave nodes is not limited, and a single PCH board may implement management of multiple nodes. That is to say, in this embodiment of the present application, a single PCH may manage nodes of different granularities, and what granularity is specifically adopted may be configured accordingly as needed. For example, one PCH manages 1 node, or one PCH manages 2 nodes, or one PCH manages 4 nodes. Therefore, limited hard partition requirements are met, materials can be saved, and the space of the whole machine is saved.

Optionally, the method 200 further comprises:

and the main node updates the BIOS code in the nonvolatile storage of the main node through the BMC of the main node.

Specifically, the master node updates the BIOS code through the BMC of the master node, and then sends the updated BIOS code to the slave node. In this way, the master node may also control BIOS upgrades of other nodes.

In the embodiment of the present application, the communication method between the master node and the slave node is not limited to ethernet, and may be other communication methods such as a high-speed SERializer/DESerializer (serdes), and the like, which is not limited herein.

Optionally, in this embodiment of the present application, the configuration of the CPU and the NC in the slave node is implemented by the BIOS. For a master node or slave node: the BIOS is responsible for starting the whole system, and the BMC in the node is responsible for managing the whole system. When the system is started, the BMC only needs to carry out power-on management.

In order to facilitate those skilled in the art to understand the technical solutions of the embodiments of the present application, the following description will be made with reference to the example in fig. 3. FIG. 3 shows a schematic block diagram of a computing system according to an embodiment of the present application. As shown in fig. 3, the computing system includes cluster 1 and cluster 2. The cluster 1 comprises 2 nodes (respectively a node 1 and a node 2), and each node comprises n CPUs (central processing units); cluster 2 includes 2 nodes (node 3 and node 4, respectively). Each node includes n CPUs. Each node has a corresponding BMC, non-volatile storage, and NC. Wherein, the node 1 is a master node, and the nodes 2, 3 and 4 are slave nodes. The connection between each node is established through a switch (Swtich). Node 1 differs from nodes 2, 3 and 4 in that the PCH board is reserved in node 1, but not in nodes 2, 3 and 4. The non-volatile storage in node 2, node 3 and node 4 is directly connected to the NC through the SPI port. The CPUs in node 2, node 3 and node 4 can directly read the BIOS code in the nonvolatile storage through the NC. Wherein a link may be established between NCs of different nodes (which may be an NC of any two of node 1, node 2, node 3, and node 4). The link of the NC between the nodes 1 and 2, and the link of the NC between the nodes 3 and 4 are exemplarily shown in fig. 3, and are not limited.

Specifically, node 1 reads the BIOS code in the nonvolatile storage of node 1 via the BMC in node 1 and sends it to the BMC of node 2, the BMC of node 3, and the BMC of node 4 via the Ethernet connection. Taking node 2 as an example, the BMC in node 2 writes the BIOS code to the non-volatile storage in node 2. Thus, when the system starts, taking node 2 as an example, node 2 may read the BIOS code directly from the nonvolatile storage through the NC in node 2 without setting a corresponding PCH board in node 2. Similarly, nodes 3 and 4 can read the code in the same manner as node 2.

It should be understood that the computing system may have a plurality of nodes, and fig. 3 is only described by way of example in which the computing system includes 4 nodes, and the number of nodes is not limited.

It should also be understood that the above description is only given by taking 2 nodes in the cluster as an example, and the number of nodes included in the cluster is not limited in practice.

Therefore, as can be seen from the example in fig. 3, the scheme of the embodiment of the application can save materials, reduce cost and save the space of the whole machine.

The scheme of the embodiment of the present application will be described below with reference to a specific flow chart in fig. 4. It should be understood that the steps in fig. 4 that are the same as those in the conventional flow are not described in detail. As shown in fig. 4, the process includes:

41, powering on the CC-NUMA system. For example, the system power-on voltage is a standby (standby) voltage of 5 v.

And 42, configuring topology information and clock configuration.

Specifically, after the CC-NUMA system is powered on, information such as a topology structure and a clock of the network can be configured.

43, the PCH node is configured to read the BIOS code from a Direct Media Interface (DMI) port; a PCH-free node is configured to read BIOS code from a UPI or Quick Path Interface (QPI). Alternatively, the read may be through an Application Programming Interface (API), which is not limited thereto.

Here, the CC-NUMA system may pre-configure a mode of reading the BIOS code from the node, where the specific configuration includes: the nodes with the PCH boards read the BIOS codes from the DMI port, and the nodes without the PCH boards read the BIOS codes from the UPI port or the API port.

And 44, carrying out health self-check by the CC-NUMA system.

After the CC-NUMA system is configured, the health of the system can be self-checked. The health self-check here is mainly used for detecting at least one item of: the in-place situation of the system device, whether each subsystem in the system has a short circuit situation, whether the main part has damage, errors and the like.

45, service electricity on the CC-NUMA system.

Here, the service power on means that the management module powers on the computing system.

And 46, finishing the link establishment (namely link establishment) by the CPU and the CPU, and the CPU and the NC. Optionally, after the link is completely established, go to step 49, or continue to execute step 47.

The link establishment here includes: the CC-NUMA system establishes a link between the CPU and the CPU, and a link between the CPU and the NC.

47, the NC completes self-configuration. Here, the NC also needs to configure itself to fit the corresponding node.

And 48, completing chain establishment between NCs.

Here, a link also needs to be established between the NC and the NC to enable communication between the respective nodes.

49, the host node acquires the BIOS code from the DMI port; the slave node obtains the BIOS code through the NC.

Here, the embodiment of the present application only reserves the PCH board of the master node. Therefore, the master node acquires the BIOS code through the DMI port, and the slave node acquires the BIOS code directly from the nonvolatile storage through the NC.

50, executing the BIOS code.

The CC-NUMA system may begin executing BIOS code for each node read.

51, whether the links between the CPU and between the CPU and the NC need to switch the rate.

Alternatively, the CC-NUMA system may determine whether the link between the CPU and the CPU, and the link between the CPU and the NC require a switch rate. If the rate needs to be switched, go to step 52; if no rate switching is required, go to step 57. For example, the rate is switched from high speed to low speed, or from low speed to high speed. In any case, the link needs to be established again after the handover is completed.

And 52, completing the link establishment again after switching the rate.

Here, when the link between the CPU and the link between the CPU and the NC require a switching rate, the link establishment needs to be performed again.

53, the NC completes the self-configuration.

Similarly, after the link between the CPU and the NC switches rates, the NC needs to self-configure again.

And 54, establishing a link between the NC and the NC.

Similarly, when the link between the CPU and the NC is switched in rate, the link needs to be established again between the node and the NC of the node.

55, executing the BIOS code.

And the CC-NUMA system executes the BIOS codes acquired by the main node and the slave node, or continues to execute the BIOS codes after switching the speed.

And 56, BIOS merging the system.

And 57, executing the BIOS code.

And 58, starting the CC-NUMA system into the interface shell.

After the CCNUMA system executes the code and starts, the system enters a user interface shell.

59, the CC-NUMA System starts into the Operating System (OS).

Therefore, the above flow describes in detail the method for starting the CC-NUMA system after applying the embodiment of the present application, and after only the PCH board of the master node is reserved, step 43 configures the way in which the master node reads the BIOS code and the way in which the slave node reads the BIOS code, so that the master node and the slave node read the BIOS code in the configured way to complete the start of the CC-NUMA system. It should be understood that in the above-described flow, for the sake of brevity, some steps similar to those of the prior art are not specifically described, and are within the knowledge of one skilled in the art.

Having described a method for computing system boot-up in accordance with an embodiment of the present application, a computing system in accordance with an embodiment of the present application will now be described.

FIG. 5 shows a schematic block diagram of a computing system 500 according to an embodiment of the present application. As shown in fig. 5, the computing system 500 includes:

a master node 510, at least one slave node 520, each slave node 520 comprising a processor 521, a baseboard management controller BMC and a node controller NC, the master node 510 comprising a processor 511, an NC and a platform control center PCH board 512;

a processor 511 in the master node 510, configured to read BIOS code through the PCH board 512;

the master node 510 is configured to send the BIOS code to each slave node 520 through a BMC of the master node 510;

the processor 521 in each slave node 520 is configured to read the BIOS code directly from non-volatile storage that is suspended by the NC in each slave node 520 at startup of the computing system.

In the embodiment of the application, the BIOS code is read through a PCH board in the master node, and the BIOS code is read directly from the non-volatile storage hung down by the NC by the slave node, so as to complete the startup of the computing system. In the computing system 500, only the PCH board of the master node 510 is reserved, and the PCH board does not need to be reserved from the slave node, so that materials can be saved, the space of the whole computer can be reduced, and the cost can be saved.

Optionally, the processor 521 of each slave node 520 is specifically configured to:

writing the BIOS code to the non-volatile storage corresponding to the slave node by the BMC of each slave node 520.

Optionally, the processor 511 in the master node 510 is specifically configured to:

and reading the BIOS code in the nonvolatile storage corresponding to the main node 510 through the PCH board by using the BMC.

Optionally, the nonvolatile storage corresponding to each slave node 520 is directly connected to the NC.

Optionally, the master node 510 is further configured to:

upgrading the BIOS code in the nonvolatile storage corresponding to the master node 510 by the BMC of the master node.

Optionally, the processor 521 in each slave node 520 is preconfigured by directly reading the BIOS code through the NC.

Therefore, only the PCH board of the master node 510 is reserved in the computing system 500, and the PCH board does not need to be reserved on the slave node, so that materials can be saved, the space of the whole computer can be reduced, and the cost can be saved.

It should be understood that in the above-mentioned computing system 500, the main node 510 may have a plurality of processors, and only one processor 511 is shown in the figure (the processor 511 may be understood as a main processor of the main node 510), but the embodiment of the present application is not limited thereto. Similarly, the slave node 520 may have a plurality of processors, only one processor 521 is shown (the processor 521 may be understood as the master processor of the slave node 520).

It should also be understood that the number of slave nodes in the computing system 500 is not limited in the embodiments of the present application, and there may be a plurality of slave nodes 520. Here, regardless of the number of slave nodes, only the PCH board in the master node 510 remains in the computing system 500.

Alternatively, the non-volatile storage in the slave node 520 may be non-volatile memory that can be hung on the NC. For example, the non-volatile memory may include: nonvolatile memories such as Programmable Read Only Memories (PROMs), Phase Change Memories (PCMs), Resistive Random Access Memories (RRAMs), Magnetic Random Access Memories (MRAMs), Ferroelectric Random Access Memories (FRAMs), and Electrically Erasable Programmable Read Only Memories (EEPROMs).

In the embodiments of the present application, it is understood that a Central Processing Unit (CPU) is merely one example of a processor, and an operating system and other software programs are executed by the CPU. In addition to a Central Processing Unit (CPU), the processor may also be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The Processor may be a general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable Logic Device, a discrete Gate or transistor Logic Device, a discrete hardware component, a System On Chip (SoC), a Central Processing Unit (CPU), a Network Processor (NP), a Digital Signal Processor (DSP), a microcontroller (Micro Controller Unit, MCU), a Programmable Logic Device (PLD) or other Integrated Chip. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in a Random Access Memory (RAM), a flash Memory, a Read-Only Memory (ROM), a programmable ROM, an electrically erasable programmable Memory, a register, or other storage media that are well known in the art. The storage medium is located in a memory, and a processor reads instructions in the memory and combines hardware thereof to complete the steps of the method.

It should also be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a U disk, a removable hard disk, a read-only memory ROM, a random access memory RAM, a magnetic disk, or an optical disk.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for computing system boot-up, the computing system comprising a master node and at least one slave node, each slave node comprising a processor, a baseboard management controller, BMC, and a node controller, NC, the master node comprising a processor, a BMC, NC, and a platform control center, PCH, board, the method comprising:

at the time of the computing system startup, the processor in each slave node reads the BIOS code directly from non-volatile storage that is hung down by the NC in each slave node;

before the processor of each slave node reads the BIOS code directly from non-volatile storage that is under-hung by the NC in the each slave node, the method further comprises:

the BMC of each slave node writes the BIOS code into the nonvolatile storage of the slave node.

2. The method of claim 1, wherein reading the BIOS code through the PCH board by a processor in the master node comprises:

the processor in the host node reads the BIOS code in the non-volatile storage of the host node through the PCH board using a BMC.

3. The method of claim 1, wherein the non-volatile storage corresponding to each slave node is directly connected to the NC.

4. The method of claim 1, further comprising:

5. The method of claim 1, wherein the processor in each slave node is preconfigured to read the BIOS code directly through the NC.

6. A computing system, comprising:

the processor in each slave node is used for directly reading the BIOS codes from the nonvolatile storage hung under the NC in each slave node when the computing system is started;

each slave node is specifically configured to:

writing the BIOS code to a non-volatile storage of the slave node by the BMC of each slave node.

7. The computing system of claim 6, wherein the processor in the master node is specifically configured to:

8. The computing system of claim 6, wherein the non-volatile storage corresponding to each slave node is directly connected to the NC.

9. The computing system of claim 6, wherein the processor in the master node is further configured to:

upgrading the BIOS code in the nonvolatile storage of the main node through the BMC of the main node.

10. The computing system of claim 6, wherein the processor in each slave node is preconfigured to read the BIOS code directly through the NC.