CN116825896A - Preparation method of TOPCON battery with back selective passivation layer - Google Patents

Preparation method of TOPCON battery with back selective passivation layer Download PDF

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Publication number
CN116825896A
CN116825896A CN202310875562.XA CN202310875562A CN116825896A CN 116825896 A CN116825896 A CN 116825896A CN 202310875562 A CN202310875562 A CN 202310875562A CN 116825896 A CN116825896 A CN 116825896A
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Prior art keywords
back surface
film
passivation layer
topcon battery
selective passivation
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CN202310875562.XA
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Chinese (zh)
Inventor
张明明
付少剑
郭世成
范询
郭小飞
侯良培
熊亮
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Chuzhou Jietai New Energy Technology Co ltd
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Chuzhou Jietai New Energy Technology Co ltd
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Abstract

The invention provides a preparation method of a TOPCON battery with a back selective passivation layer, and relates to the technical field of TOPCON battery processing. The preparation of the TOPCON battery with the back surface selective passivation layer mainly comprises the steps of silicon wafer texturing, boron diffusion doping, back surface pickling and polishing, front and back surface growth of a poly silicon layer, long-time high doping phosphorus expansion of the back surface, laser perforation of a non-emitter grid line area of the back surface, front and back surface pickling and alkali washing, front and back surface deposition of Al 2 O 3 Thin film, front surface, back surface deposition of Si x N y /SiON y Film, electrode printing and the like. The invention overcomes the defects of the prior art, and the psg layer of the non-emitter region is perforated by laser after the back surface is heavily P dopedAnd then normal cleaning is carried out to form a selective emitter electrode passivation structure, so that the conversion efficiency and the contact capability can be greatly improved.

Description

Preparation method of TOPCON battery with back selective passivation layer
Technical Field
The invention relates to the technical field of TOPCON battery processing, in particular to a preparation method of a TOPCON battery with a back selective passivation layer.
Background
In recent years, with the continuous expansion of the capacity of topcon batteries, the installation cost of power stations can be effectively reduced due to the higher conversion efficiency and the higher double-sided rate of double-sided batteries compared with perc batteries, and the battery assembly is more and more favored by market terminals. However, there are still some problems in the aspect of the efficiency of the current topcon battery, especially the problems of long-wave optics and recombination caused by the introduction of a poly silicon layer on the back of the battery have a great influence on the efficiency, so the development of an efficient and stable back passivation battery is particularly urgent.
At present, the topcon battery needs to form a good back contact layer through P-extension heavy doping due to the fact that the back poly si layer is added, however, electrons can be easily captured by redundant P atoms in the back heavy doping, more composite centers are formed, efficiency is affected, long waves can be absorbed by the back poly si layer, internal reflection capacity is reduced, efficiency is also affected, and accordingly the efficiency improvement in the prior art is greatly limited.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a preparation method of a TOPCON battery with a back selective passivation layer, which is characterized in that after the back surface is heavily P-doped, a psg layer of a non-emitter region is perforated by laser and then is normally cleaned, so that a selective emitter electrode passivation structure is formed, and the conversion efficiency and the contact capability can be greatly improved.
In order to achieve the above object, the technical scheme of the present invention is realized by the following technical scheme:
a method for preparing a TOPCON battery with a back surface selective passivation layer, the method comprising the steps of:
(1) Texturing the silicon wafer, and forming a nanoscale textured surface on the surface of the silicon wafer;
(2) Boron diffusion doping, wherein a P+ layer is doped on the front surface of the silicon wafer;
(3) Washing the back surface with acid to remove BSG, and then performing alkaline washing and polishing on the back surface;
(4) Forming a SiO layer on the front side and the back side at high temperature and then growing a poly silicon layer;
(5) Performing long-time high-doped phosphorus expansion on the back surface to form a high-doped N+ layer;
(6) Carrying out laser opening treatment on the non-emitter grid line area on the back surface to destroy the PSG layer, wherein other contact areas are N+ layers, and the PSG layer is still reserved;
(7) Removing BSG and PSG on the front side and the back side by acid washing and alkali washing, simultaneously removing poly silicon on the front side, and simultaneously removing excessive poly in a non-emitter region on the back side to obtain an emitter selective passivation back side structure;
(8) Front and back side deposition of Al using ALD 2 O 3 A film;
(9) Deposition of Si on front surface by PECVD x N y /SiON y A film;
(10) Deposition of Si on the back surface by PECVD x N y /SiON y A film;
(11) Electrode printing is performed on the front and back surfaces.
Preferably, the silicon wafer in the step (1) is a phosphorus doped N-type monocrystalline silicon wafer.
Preferably, in the step (2), the boron diffusion doping mode is to introduce BCl3 or BBr3 gas into the front surface of the silicon wafer to dope the silicon wafer to form a P+ layer.
Preferably, the thickness of the poly silicon layer in the step (4) is 80-130nm.
Preferably, the long-time high-doped phosphorus diffusion in the step (5) is carried out for 300-600s, the deposition temperature is 780-810 ℃, the large nitrogen flow is 500-1000sccm, the small nitrogen flow is 1000-1400sccm, the oxygen flow is 500-1000sccm, the temperature is increased to 880-900 ℃ in the phosphorus diffusion process, the phosphorus diffusion process is carried out, the temperature is reduced to 700-750 ℃ after the advancing process, the tube is cooled, and the square resistance of the obtained N-type silicon wafer is 20-40 omega.
Preferably, the laser spot size of the laser hole opening treatment in the step (6) is 100-300um.
Preferably, al is deposited in the step (8) 2 O 3 The mode of the film is that water/TMA/N is introduced after the temperature is raised in a vacuum environment 2 Deposition is performed.
Preferably, si is deposited in the step (9) x N y /SiON y The mode of the film is that NH is introduced into the vacuum environment 3 、N 2 O、SiH 4 Formation of Si x N y /SiON y A film.
Preferably, si is deposited in the step (10) x N y /SiON y The mode of the film is that NH is introduced into the vacuum environment 3 、N 2 O、SiH 4 Formation of Si x N y /SiON y A film.
The invention provides a preparation method of a TOPCON battery with a back selective passivation layer, which has the advantages that compared with the prior art:
(1) According to the invention, the passivation contact technology of the topcon battery is fully utilized, and on the existing poly silicon structure, the passivation region is selectively manufactured on the newly generated poly silicon, so that the high conductivity of the emission electrode region is pertinently improved, and the composivity of the non-emitter region is reduced; and under the current mass production topcon route, through the optimization of related process structures and the increase of procedures, tunneling layer silicon oxide and a poly silicon layer are firstly deposited on the back surface after intrinsic silicon is polished, after phosphorus doping is carried out in situ, a laser opening treatment is carried out on the non-contact part of a back metal auxiliary grid line and the deposited poly silicon and the vicinity thereof to remove psg layers, high-concentration doping is carried out on the area of a transmitting electrode, after acid washing and alkali washing are carried out, the non-treated area is not protected by psg, the poly layer is removed by alkali corrosion, thus a selective passivation structure is obtained, the contact resistance of the poly silicon and the electrode is improved, the recombination of the surface of the non-contact area is reduced, the minority carrier lifetime is improved, the short circuit current and the filling factor are both better improved, meanwhile, the laser selectivity does not damage the intrinsic silicon, the damage recombination of the intrinsic silicon is reduced, the conversion efficiency is greatly improved, and the relative efficiency is greatly improved.
(2) The improvement of the invention is deduced through an electrical mechanism, expensive materials or complex process methods are not used, the invention has larger mass production practicability, has obvious effect on improving efficiency, and greatly reduces the production cost.
Description of the drawings:
fig. 1 is a schematic diagram of a TOPCON cell structure with a back selective passivation layer according to embodiment 1 of the present invention;
fig. 2 is a schematic diagram of the structure of a conventional TOPCON battery according to a comparative example of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described in the following in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Examples:
preparation of a rear selective passivation layer TOPCON cell as shown in fig. 1:
(1) Texturing an N-type silicon wafer, and forming a nanoscale textured surface on the surface of the silicon wafer;
(2) Boron diffusion doping, and introducing BCl on the front surface of the silicon wafer 3 Forming a P+ layer by gas doping;
(3) Washing the back surface with acid to remove BSG, and then performing alkaline washing and polishing on the back surface to form a flat surface structure;
(4) Forming a SiO layer on the front side and the back side at high temperature, and then growing a poly silicon layer, wherein the thickness of the poly silicon layer is 115nm;
(5) Phosphorus diffusion is carried out on the back surface to form a highly doped N+ layer: carrying out long-time high doping on the phosphorus expansion; specifically, the back light and high impurity is mainly deposited for 500s at a deposition temperature of 805 ℃, a large nitrogen flow of 800sccm, a small nitrogen flow of 1100sccm and an oxygen flow of 700sccm. Then heating to 885 ℃ for pushing, cooling to 750 ℃ after pushing, and then cooling the pipe out to obtain the N-type silicon wafer with the square resistance of 30Ω;
(6) Carrying out laser perforation treatment on the non-emitter grid line area on the back surface to destroy psg layers, wherein the laser spot size is 200um, other contact areas are N+ layers, and psg layers are still protected;
(7) Removing BSG and PSG on the front and back surfaces by acid and alkali washing, simultaneously removing poly silicon on the front surface, and removing excessive poly silicon in a non-emitter region on the back surface, so as to obtain a back surface structure with an emitter selectively passivated;
(8) Front and back side deposition of Al using ALD 2 O 3 Film under vacuum at 300℃by introducing water/TMA/N 2 Deposition of 4nm Al 2 O 3 A film;
(9) Deposition of Si on front surface by PECVD x N y Or SiON y A film, NH is introduced under vacuum 3 、N 2 O、SiH 4 Formation of Si x N y Or SiON y Film, film thickness is 72nm;
(10) Deposition of Si on the back surface by PECVD x N y /SiON y A film, NH is introduced under vacuum 3 、N 2 O、SiH 4 Formation of Si x N y /SiON y A film with a thickness of 80nm;
(11) The front and back sides were subjected to Ag electrode printing, followed by sintering and light decay to obtain a battery structure as shown in fig. 1.
Comparative example:
preparation of a conventional TOPCON cell as shown in fig. 2:
(1) Texturing an N-type silicon wafer, and forming a nanoscale textured surface on the surface of the silicon wafer;
(2) Boron diffusion doping, namely introducing BCl3 gas doping into the front surface of the silicon wafer to form a P+ layer;
(3) Washing the back surface with acid to remove BSG, and then performing alkaline washing and polishing on the back surface;
(4) The SiO layer is formed on the front and back surfaces at high temperature, then the poly silicon layer is grown, and the thickness of the poly silicon layer is 115nm
(5) Phosphorus diffusion is carried out on the back surface to form an N+ layer;
(6) Removing BSG and PSG on the front and back surfaces by acid and alkali washing on the front and back surfaces, and simultaneously removing poly silicon on the front surface;
(7) Front and back side deposition of Al using ALD 2 O 3 Film under vacuum at 300℃by introducing water/TMA/N 2 Deposition of 4nm Al 2 O 3 A film;
(8) Deposition of Si on front surface by PECVD x N y Or SiON y A film, NH is introduced under vacuum 3 、N 2 O、SiH 4 Formation of Si x N y Or SiON y Film, film thickness is 72nm;
(9) Deposition of Si on the back surface by PECVD x N y /SiON y A film, NH is introduced under vacuum 3 、N 2 O、SiH 4 Formation of Si x N y /SiON y A film with a thickness of 80nm;
(10) The front and back sides were subjected to Ag electrode printing, followed by sintering and light decay to obtain a battery structure as shown in fig. 2.
And (3) detection:
the batteries prepared in the above examples and comparative examples were subjected to performance tests, and specific results are shown in the following table:
from the above table and test, the example topcon cell was 0.226% higher than the conventional topcon cell in the comparative example, specifically 1.7mV higher in open voltage (uoc), 75ma higher in short current (isc), 0.03mΩ lower in rs (resistance), 0.1% higher in filling (ff), and the mechanism was consistent with the expectations of the improvement performance.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (9)

1. A method for preparing a TOPCON battery with a back surface selective passivation layer, which is characterized by comprising the following steps:
(1) Texturing the silicon wafer, and forming a nanoscale textured surface on the surface of the silicon wafer;
(2) Boron diffusion doping, wherein a P+ layer is doped on the front surface of the silicon wafer;
(3) Washing the back surface with acid to remove BSG, and then performing alkaline washing and polishing on the back surface;
(4) Forming a SiO layer on the front side and the back side at high temperature and then growing a poly silicon layer;
(5) Performing long-time high-doped phosphorus expansion on the back surface to form a high-doped N+ layer;
(6) Carrying out laser opening treatment on the non-emitter grid line area on the back surface to destroy the PSG layer, wherein other contact areas are N+ layers, and the PSG layer is still reserved;
(7) Removing BSG and PSG on the front side and the back side by acid washing and alkali washing, simultaneously removing poly silicon on the front side, and simultaneously removing excessive poly in a non-emitter region on the back side to obtain an emitter selective passivation back side structure;
(8) Front and back side deposition of Al using ALD 2 O 3 A film;
(9) Deposition of Si on front surface by PECVD x N y /SiON y A film;
(10) Deposition of Si on the back surface by PECVD x N y /SiON y A film;
(11) Electrode printing is performed on the front and back surfaces.
2. The method for preparing the TOPCON battery with the back selective passivation layer according to claim 1, wherein the method comprises the following steps: the silicon wafer in the step (1) is a phosphorus doped N-type monocrystalline silicon wafer.
3. The method for preparing the TOPCON battery with the back selective passivation layer according to claim 1, wherein the method comprises the following steps: the boron diffusion doping mode in the step (2) is to introduce BCl on the front surface of the silicon wafer 3 Or BBr 3 The gas doping forms a p+ layer.
4. The method for preparing the TOPCON battery with the back selective passivation layer according to claim 1, wherein the method comprises the following steps: the thickness of the poly silicon layer in the step (4) is 80-130nm.
5. The method for preparing the TOPCON battery with the back selective passivation layer according to claim 1, wherein the method comprises the following steps: and (3) the long-time high-doped phosphorus diffusion in the step (5) is carried out for 300-600s, the deposition temperature is 780-810 ℃, the large nitrogen flow is 500-1000sccm, the small nitrogen flow is 1000-1400sccm, the oxygen flow is 500-1000sccm, the temperature is increased to 880-900 ℃ in the phosphorus diffusion process, the phosphorus diffusion process is carried out, the pipe is cooled after the temperature is reduced to 700-750 ℃, and the square resistance of the obtained N-type silicon wafer is 20-40 omega.
6. The method for preparing the TOPCON battery with the back selective passivation layer according to claim 1, wherein the method comprises the following steps: and (3) performing laser perforation treatment in the step (6) to obtain a laser spot size of 100-300um.
7. The method for preparing the TOPCON battery with the back selective passivation layer according to claim 1, wherein the method comprises the following steps: depositing Al in the step (8) 2 O 3 The mode of the film is that water/TMA/N is introduced after the temperature is raised in a vacuum environment 2 Deposition is performed.
8. The method for preparing the TOPCON battery with the back selective passivation layer according to claim 1, wherein the method comprises the following steps: depositing Si in the step (9) x N y /SiON y The mode of the film is that NH is introduced into the vacuum environment 3 、N 2 O、SiH 4 Formation of Si x N y /SiON y A film.
9. The method for preparing the TOPCON battery with the back selective passivation layer according to claim 1, wherein the method comprises the following steps: depositing Si in the step (10) x N y /SiON y The mode of the film is that NH is introduced into the vacuum environment 3 、N 2 O、SiH 4 Formation of Si x N y /SiON y A film.
CN202310875562.XA 2023-07-18 2023-07-18 Preparation method of TOPCON battery with back selective passivation layer Pending CN116825896A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117438481A (en) * 2023-12-20 2024-01-23 淮安捷泰新能源科技有限公司 Photovoltaic module and preparation method thereof, and preparation method of N-TOPCO battery piece

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117438481A (en) * 2023-12-20 2024-01-23 淮安捷泰新能源科技有限公司 Photovoltaic module and preparation method thereof, and preparation method of N-TOPCO battery piece
CN117438481B (en) * 2023-12-20 2024-04-09 淮安捷泰新能源科技有限公司 Photovoltaic module and preparation method thereof, and preparation method of N-TOPCO battery piece

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