CN116820898B - Method and system for monitoring running state of eMMC and computer readable storage medium - Google Patents
Method and system for monitoring running state of eMMC and computer readable storage medium Download PDFInfo
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Abstract
The application discloses an operation state monitoring method, a system, a device and a computer readable storage medium of an embedded multimedia card eMMC, wherein the method comprises the following steps: communication is carried out between an SOC chip and the eMMC through an eMMC protocol, and first instruction information is sent to the eMMC through the SOC chip to acquire the eMMC state information; detecting the eMMC state information, and sending second instruction information for warning adjustment to the eMMC through the SOC chip when judging that the eMMC state information is abnormal so as to debug the eMMC. In this way, the running state information of the eMMC can be timely obtained through the SOC chip, the accuracy of the obtained eMMC state information is improved, and the running state of the eMMC can be timely adjusted according to the eMMC state information.
Description
Technical Field
The present disclosure relates to the field of data monitoring technologies, and in particular, to an eMMC operation state monitoring method, system, and computer readable storage medium.
Background
An embedded multimedia card (embedded Multi Media Card, eMMC) is a main storage device in mobile terminals such as mobile phones and tablet computers, and uses a NAND Flash memory (NAND Flash) as a storage medium to store software, data, and the like in the mobile terminals. With the wide application of eMMC memory chips in terminal products such as televisions, set-top boxes, tablet computers or mobile phones, the performance and reliability requirements of eMMC memory chips are higher and higher, wherein it is most important to ensure that data stored in eMMC is stable and reliable.
The operation health state and the service life of the eMMC can affect the use experience of the end user, and if the eMMC state is not good, the firmware needs to intervene in time to adjust the internal mechanism, so as to ensure the reliable operation of the eMMC data. In the current prior art, the configuration and performance information of the eMMC are read, and the total byte number writing amount (Total Bytes Written, TBW) of the eMMC is estimated through the Extended CSD (ECSD) Type a/Type B jump, but the central processing unit (Central Processing Unit, CPU) of the SOC (System-on-Chip) cannot count the writing data amount of the host in real time, and only the value of the jump of polling ECSD Type A/Type B can be used, so that timeliness and accuracy are poor, and the CPU cannot grasp the running state of the eMMC in time, and cannot make corresponding running adjustment.
Disclosure of Invention
An object of the present application is to provide a method, a system, a device and a computer readable storage medium for monitoring an operation state of an eMMC of an embedded multimedia card, which can timely acquire operation state information of the eMMC through an SOC chip, improve accuracy of the acquired eMMC state information, and facilitate timely adjusting the operation state of the eMMC according to the eMMC state information.
To achieve the above object:
in a first aspect, an embodiment of the present application provides a method for monitoring an operation state of an embedded multimedia card eMMC, which is applied to an SOC chip, and the method includes the following steps:
communication is carried out between an SOC chip and the eMMC through an eMMC protocol, and first instruction information is sent to the eMMC through the SOC chip to acquire the eMMC state information;
detecting the eMMC state information, and sending second instruction information for warning adjustment to the eMMC through the SOC chip when judging that the eMMC state information is abnormal so as to debug the eMMC.
Optionally, the communication between the SOC chip and the eMMC through an eMMC protocol, and the sending, by the SOC chip, first instruction information to the eMMC to obtain the eMMC state information includes:
transmitting first instruction information for acquiring eMMC state information to the eMMC through a processor of the SOC chip; the first instruction information comprises a custom command and parameter data;
and indexing according to the parameter data, and determining storage space address information related to the eMMC state information corresponding to the first instruction so as to acquire the eMMC state information in the storage space.
Optionally, the eMMC status information includes an operation status of the eMMC and metadata information corresponding to the operation status,
the detecting the eMMC status information, and when determining that the eMMC status information is abnormal, sending, by the SOC chip, second instruction information for warning adjustment to the eMMC to debug the eMMC includes:
detecting whether metadata information corresponding to the running state is in the range of set standard state information, and judging the running state of the eMMC;
and if the state information is not in the range of the standard state information, determining that the state information corresponding to the metadata is abnormal, wherein the operation state of the eMMC is abnormal.
In a second aspect, an embodiment of the present application provides a method for monitoring an operation state of an eMMC of an embedded multimedia card, which is applied to eMMC, and the method includes the following steps:
presetting a storage space for storing eMMC state information in a memory in the eMMC;
communicating with the SOC chip through the eMMC protocol, and sending the eMMC state information to the SOC chip in the storage space through the received first instruction information;
and when judging that the eMMC state information is abnormal, entering a debugging mode according to the second instruction information so as to recover the normal operation of the eMMC.
Optionally, the presetting a storage space for storing eMMC state information in the memory in the eMMC includes:
determining at least one storage space in the eMMC according to the set address information, and updating state information of the eMMC in real time in the storage space;
and acquiring the eMMC state information, and classifying according to the data type of the eMMC state information so as to distribute the eMMC state information to different storage spaces for storage.
Optionally, when the eMMC state information is determined to be abnormal, entering a debug mode according to second instruction information to restore normal operation of the eMMC, including:
when judging that the running state of the eMMC is abnormal, receiving second instruction information sent by the SOC chip;
after receiving the second instruction information, the eMMC writes the data of the second instruction information into a control register of the eMMC and enters a debugging mode so as to adjust the state of the eMMC according to the second instruction information and restore the normal working state of the eMMC.
In a third aspect, an embodiment of the present application provides an eMMC operation state monitoring system, where the system includes an SOC chip, eMMC, and a memory DRAM, where,
The system comprises an SOC chip, an eMMC (state of charge) module and an eMMC controller, wherein the SOC chip is used for communicating between the SOC chip and the eMMC through an eMMC protocol and sending first instruction information to the eMMC through the SOC chip to acquire the eMMC state information; detecting the eMMC state information, and sending second instruction information for warning adjustment to the eMMC through the SOC chip when judging that the eMMC state information is abnormal so as to debug the eMMC;
an eMMC for presetting a storage space for storing eMMC state information in a memory in the eMMC; communicating with the SOC chip through the eMMC protocol, and sending the eMMC state information to the SOC chip in the storage space through the received first instruction information; and when judging that the eMMC state information is abnormal, entering a debugging mode according to the second instruction information so as to recover the normal operation of the eMMC.
Optionally, the SOC chip is specifically configured to:
transmitting first instruction information for acquiring eMMC state information to the eMMC through a processor of the SOC chip; the first instruction information comprises a custom command and parameter data;
and indexing according to the parameter data, and determining storage space address information related to the eMMC state information corresponding to the first instruction so as to acquire the eMMC state information in the storage space.
Optionally, the eMMC status information includes an operation status of the eMMC and metadata information corresponding to the operation status,
the SOC chip is specifically used for:
detecting whether metadata information corresponding to the running state is in the range of set standard state information, and judging the running state of the eMMC;
and if the state information is not in the range of the standard state information, determining that the state information corresponding to the metadata is abnormal, wherein the operation state of the eMMC is abnormal.
Optionally, the eMMC is specifically configured to:
determining at least one storage space in the eMMC according to the set address information, and updating state information of the eMMC in real time in the storage space;
and acquiring the eMMC state information, and classifying according to the data type of the eMMC state information so as to distribute the eMMC state information to different storage spaces for storage.
Optionally, the eMMC is specifically configured to:
when judging that the running state of the eMMC is abnormal, receiving second instruction information sent by the SOC chip;
after receiving the second instruction information, the eMMC writes the data of the second instruction information into a control register of the eMMC and enters a debugging mode so as to adjust the state of the eMMC according to the second instruction information and restore the normal working state of the eMMC.
In a fourth aspect, an embodiment of the present application discloses an eMMC operation state monitoring device, which specifically includes:
a processor;
a memory for storing the processor-executable instructions;
the processor is configured to execute the instructions, and is configured to execute the method for monitoring the operation state of the eMMC according to the first aspect and the second aspect.
In a fifth aspect, embodiments of the present application provide a computer-readable storage medium, in which a computer program is stored, which when executed by a processor of an electronic device, enables the electronic device to implement the method for monitoring an operation state of eMMC according to the first and second aspects.
The method, system, device and computer readable storage medium for monitoring the operation state of the eMMC provided by the embodiment of the application comprise the following steps: communication is carried out between an SOC chip and the eMMC through an eMMC protocol, and first instruction information is sent to the eMMC through the SOC chip to acquire the eMMC state information; detecting the eMMC state information, and sending second instruction information for warning adjustment to the eMMC through the SOC chip when judging that the eMMC state information is abnormal so as to debug the eMMC. In this way, the running state information of the eMMC can be timely obtained through the SOC chip, the accuracy of the obtained eMMC state information is improved, and the running state of the eMMC can be timely adjusted according to the eMMC state information.
Drawings
Fig. 1 is a schematic flow chart of an eMMC operation state monitoring method applied to an SOC chip according to a preferred embodiment of the present invention;
FIG. 2 is a layout diagram of an operating system of an eMMC memory according to a preferred embodiment of the present invention;
fig. 3 is a schematic flow chart of an eMMC operation state monitoring method according to a preferred embodiment of the present invention;
fig. 4 is a schematic diagram of a storage space storing eMMC status information in an eMMC status monitoring method according to a preferred embodiment of the present invention;
fig. 5 is a specific flow chart of an eMMC operation state monitoring method according to a preferred embodiment of the present invention;
FIG. 6 is a schematic diagram of an eMMC operation status monitoring system according to a preferred embodiment of the present invention;
fig. 7 is a schematic structural diagram of an eMMC operation state monitoring device according to a preferred embodiment of the present invention.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
In the embodiment provided by the application, the memory device eMMC can be applied to a terminal using the memory device eMMC, such as a smart phone (such as an Android mobile phone, an iOS mobile phone, etc.), a tablet personal computer, a palm computer, a mobile internet device (Mobile Internet Devices, MID), a PAD, etc., and the memory device eMMC comprises an eMMC controller and one or more NAND Flash chips, wherein the one or more NAND Flash chips are memory media for storing data, the eMMC controller is responsible for controlling and communicating the memory media from inside to outside, mainly controlling the read, write, erase operation and address space management of the memory media from inside to outside, mainly responsible for communicating with a host from outside, receiving and responding to a command of the host, realizing storing data to be stored by the host onto the corresponding memory media, and taking out and sending the data to be read by the host from the corresponding memory media to the host.
Here, the terminal product includes an SOC and a memory device eMMC main part, wherein the SOC part mainly includes: CPU central processing unit and system software; the memory device eMMC mainly includes: the main control, NAND Flash and running Firmware, where, for example, an ARM CPU is capable of running controller software, commonly referred to as Firmware (FW). The main function of the firmware is to take charge of bad block management of NAND Flash, garbage collection (Garbage Collection, GC), early warning, performance improvement and service life improvement, and reliable use of NAND Flash is ensured. The SOC software part mainly includes: uboot, linux Kernel, android OS, APP, etc.
Referring to fig. 1, in an embodiment of the present application, an operation state monitoring method of an eMMC may be executed by an operation state monitoring system of an eMMC provided in the embodiment of the present application, where the operation state monitoring system of the eMMC may be implemented in a software and/or hardware manner, and in the embodiment, the operation state monitoring method of the eMMC is applied to an SOC chip as an example, and the operation state monitoring method of the eMMC provided in the embodiment includes the following steps:
step S101: and the SOC chip is communicated with the eMMC through an eMMC protocol, and the first instruction information is sent to the eMMC through the SOC chip to acquire the eMMC state information.
Specifically, the system software part is stored inside the eMMC, and the central processing unit CPU of the SOC chip communicates with the eMMC memory chip through the eMMC protocol. Here, after the system starts Power ON normally, the CPU reads the start code from the eMMC memory chip through the eMMC protocol, and at this time, the eMMC memory chip is in a normal working mode, so that the CPU performs data transmission and information exchange between the CPU and the eMMC memory chip.
In an embodiment, after the eMMC is powered on and started, the firmware first completes the initialization action, and manages the NAND Flash through the Toggle or ONFI interface. The firmware management NAND Flash comprises normal data read-write, bad block management, garbage collection, code segment maintenance, data table segment update and other operations. After the internal main control firmware starts to perform operation such as initialization after the eMMC particle is powered on, the CPU reads a system Image file from the memory device eMMC, where the layout of an operating system Image (OS Image) of the memory device eMMC is shown in fig. 2, and mainly includes two major parts, namely a Host OS Image and an eMMC FW, where the Host OS Image is a Host system including Bootloader, uboot, linux Kernel, android, user Data, and the like, where if any part of the Data is lost, the system may not be normally used, and the other components are eMMC FW, that is, a firmware part responsible for communication response between eMMC and Host, where eMMC FW includes BOOT firmware 1 (FW BOOT 1) of eMMC and BOOT firmware 2 (FW BOOT 2) of eMMC, where FW BOOT 1 is a part responsible for booting and loading an operating system or other firmware during device startup, and is usually located in an initial part of the memory device, so as to ensure that the system can be properly loaded during startup. FW BOOT 2 is typically used to restore the system when a problem occurs during BOOT. If the part of the firmware data is damaged or lost, the eMMC cannot respond to the read-write operation of HOST, so that the system or firmware inside the eMMC is damaged, and the OS Image or eMMC firmware needs to be updated and upgraded.
In an embodiment, the communicating between the SOC chip and the eMMC through an eMMC protocol, and sending, by the SOC chip, first instruction information to the eMMC to obtain the eMMC state information includes:
transmitting first instruction information for acquiring eMMC state information to the eMMC through a processor of the SOC chip; the first instruction information comprises a custom command and parameter data;
and indexing according to the parameter data, and determining storage space address information related to the eMMC state information corresponding to the first instruction so as to acquire the eMMC state information in the storage space.
Specifically, the processor of the SOC chip sends first instruction information for acquiring the eMMC state information to the memory chip eMMC, where when the memory chip eMMC receives the first instruction information, it is determined whether the received first instruction information is a specific instruction customized according to a user requirement, if it is determined that the specific instruction is a specific instruction, correct eMMC running state information is sent to the SOC CPU according to the received first instruction information, if it is determined that the memory chip eMMC receives an instruction that the first instruction information is not a specific instruction or is wrong, the corresponding eMMC running state information is not sent. Here, the first instruction information includes a custom command and parameter data, and when it is determined that the received first instruction information is a specific instruction, address data of eMMC state information is indexed according to the parameter data in the first instruction information, and corresponding state information is determined.
Step S102: detecting the eMMC state information, and sending second instruction information for warning adjustment to the eMMC through the SOC chip when judging that the eMMC state information is abnormal so as to debug the eMMC.
Specifically, metadata information in the eMMC state information is detected, and whether the data information of the eMMC is abnormal is determined to determine an operation state of the eMMC. Here, when detecting that the eMMC running state is abnormal, the eMMC is alerted, that is, the second instruction information is sent out, so that the eMMC state is debugged according to the second instruction information.
In one embodiment, the eMMC state information includes an operation state of the eMMC and metadata information corresponding to the operation state,
the detecting the eMMC status information, and when determining that the eMMC status information is abnormal, sending, by the SOC chip, second instruction information for warning adjustment to the eMMC to debug the eMMC includes:
detecting whether metadata information corresponding to the running state is in the range of set standard state information, and judging the running state of the eMMC;
and if the state information is not in the range of the standard state information, determining that the state information corresponding to the metadata is abnormal, wherein the operation state of the eMMC is abnormal.
Specifically, the range of standard state information of each state information related to the normal state of the eMMC is preset, metadata information (Table Block) in the eMMC state information is obtained, the obtained metadata information is compared with the range of the set standard state information, if the obtained metadata information is not in the range of the set standard state information, the state information corresponding to the metadata information is determined to be abnormal, and if the obtained metadata information is in the range of the set standard state information, the state information corresponding to the metadata information is determined to be normal.
In summary, in the method for monitoring the operation state of the eMMC provided in the foregoing embodiment, the SOC chip may obtain the operation state information of the eMMC in time, so that accuracy of the obtained eMMC state information is improved, and adjustment of the operation state of the eMMC according to the eMMC state information in time is facilitated.
Based on the same inventive concept as the foregoing embodiments, referring to fig. 3, for an operation state monitoring method of an eMMC of an embedded multimedia card provided in this embodiment, the operation state monitoring method of an eMMC in this embodiment is applied to eMMC as an example, and the operation state monitoring method of an eMMC provided in this embodiment includes the following steps:
S201: a memory space for storing eMMC state information is preset in a memory in eMMC.
Specifically, a fixed address storage space is preset in a master control firmware end NAND of the eMMC, so that state information of an eMMC running state is stored through the preset storage space, and the state information of the eMMC is updated in real time.
In an embodiment, the presetting a storage space for storing eMMC status information in the memory in the eMMC includes:
determining at least one storage space in the eMMC according to the set address information, and updating state information of the eMMC in real time in the storage space;
and acquiring the eMMC state information, and classifying according to the data type of the eMMC state information so as to distribute the eMMC state information to different storage spaces for storage.
Specifically, in the firmware operation process, the operation state information generated in the process of exchanging data between the eMMC and the CPU is stored in a specific logical Block address (LBAxxx) preset in the NAND Flash through a storage medium NAND Flash, as shown in fig. 4, at least one storage space is determined through a fixed logical Block address, so as to classify according to the data type of the obtained eMMC state information, and the eMMC state information is allocated to different storage spaces for storage, where the operation state information of the eMMC includes an operation state of the eMMC and metadata information (Table Block) information corresponding to the operation state. In the eMMC state information distribution diagram shown in fig. 4, data in which 512 bytes can be stored, including bits (i.e., state information) for indicating a valid operation state, are set, and the data bits of the eMMC state information are recorded through the valid operation state bits.
Wherein, the state information of the eMMC may be a health state of the eMMC, including: indexes such as bad block number, residual life, erasure count and the like are used for evaluating the service life and the data information of the performance of the memory; the read-write state of the eMMC may be a read-write state of the eMMC, including a read-write speed of NAND in the current eMMC for data information, for evaluating performance of the memory; may be power supply voltage and current information, power supply information of eMMC, including voltage and current, in order to monitor stability of the power supply, etc.
S202: and communicating with the SOC chip through the eMMC protocol, and sending the eMMC state information to the SOC chip in the storage space through the received first instruction information.
Specifically, the eMMC and the SOC chip communicate through an eMMC protocol, and according to the received first instruction information, corresponding eMMC state information is obtained in a storage space preset in the eMMC, and the state information is sent to the SOC chip.
S203: and when judging that the eMMC state information is abnormal, entering a debugging mode according to the second instruction information so as to recover the normal operation of the eMMC.
Specifically, when determining that the eMMC state information is abnormal, that is, the eMMC running state is abnormal, entering a debug mode according to the acquired second instruction information, and performing corresponding debug according to the abnormal eMMC state information specifically indicated by the second instruction information, so that the eMMC state information is restored to be normal, and normal running of the eMMC is realized.
In an embodiment, when the eMMC status information is determined to be abnormal, entering a debug mode according to second instruction information to resume normal operation of eMMC, including:
when judging that the running state of the eMMC is abnormal, receiving second instruction information sent by the SOC chip;
after receiving the second instruction information, the eMMC writes the data of the second instruction information into a control register of the eMMC and enters a debugging mode so as to adjust the state of the eMMC according to the second instruction information and restore the normal working state of the eMMC.
Specifically, after receiving the second instruction information, the eMMC writes parameter data of the second instruction information into a control register of the eMMC, and performs a debug mode. The second instruction information includes abnormal eMMC state information, parameter data corresponding to the abnormal eMMC running state, a specific debugging module, parameter data to be debugged, and the like. Here, in the debug mode of eMMC, the fault may be eliminated in the form of upgrading the firmware with the interface, limiting the read-write function, performing algorithm adjustment, etc. according to the second instruction information, or the state of eMMC may be optimally adjusted to restore the normal operation of eMMC and the normal operation function of the system.
In summary, in the method for monitoring the operation state of the eMMC provided in the foregoing embodiment, the SOC chip may obtain the operation state information of the eMMC in time, so that accuracy of the obtained eMMC state information is improved, and adjustment of the operation state of the eMMC according to the eMMC state information in time is facilitated.
Referring to fig. 5, a specific method for interaction between an SOC chip and an eMMC storage device after starting operation in the method for monitoring an operation state of an eMMC according to an embodiment of the present application includes:
the specific operation modes of the eMMC memory device include:
s301: and powering up and starting the eMMC.
S302: the eMMC master control firmware starts to run.
Specifically, the operation works such as initializing the internal main control firmware after the eMMC particles are electrified, including: master control initialization, flash memory initialization, bad block management, file system initialization, power management and performance optimization. The firmware manages the NAND Flash through a Toggle or ONFI interface, and the NAND Flash for firmware management comprises normal data reading and writing, bad block management, garbage collection, code segment maintenance, data table segment updating and other operations.
S303: and the eMMC master control firmware internally runs and performs NAND management.
Specifically, when the master firmware of eMMC runs internally, it is responsible for managing the entire storage system, including management of Flash memory chips (NAND Flash), for example: bad block management, error Checking and Correction (ECC), write amplification (Write Amplification) management, garbage collection and balancing, data partitioning and logic management, performance optimization and cache management, temperature and power management, and the like.
S304: and the eMMC master control firmware internally runs and performs NAND management to update state information.
Specifically, the controller of the eMMC monitors the internal running state of the master control firmware of the eMMC in real time, writes state information such as available space, data index and the like of the internal running state of the master control firmware of the eMMC into a storage space preset in a memory in the eMMC and used for storing the state information of the eMMC, and realizes real-time update of the state information in the storage space.
S305: the eMMC main control receives instruction information sent by the CPU and adjusts the running state in time.
Specifically, after the eMMC receives the instruction information, parameter data of the instruction information is written into a control register of the eMMC, and a debug mode is performed. Here, in the debug mode of eMMC, the firmware is upgraded with the interface, the read-write function is limited, the algorithm adjustment is performed, and the like to eliminate the fault according to the acquired instruction information, or the state of eMMC is optimally adjusted to restore the normal operation of eMMC and the normal working function of the system.
The specific operation mode of the SOC chip comprises the following steps:
s401: and the SOC CPU is powered on and started.
S402: the CPU reads the system image file from the eMMC.
Specifically, the operating system Image (OS Image) of the memory device eMMC mainly includes two major parts, namely a Host OS Image and an eMMC FW, where the Host OS Image is a Host system, including Bootloader, uboot, linux Kernel, android, user Data, and the like, where if any part of the Data is lost, it may cause the system to be not used normally, and the other component is an eMMC FW, that is, a firmware part responsible for the communication response between the eMMC and the Host, where the eMMC FW includes a BOOT firmware 1 (FW BOOT 1) of the eMMC and a BOOT firmware 2 (FW BOOT 2) of the eMMC, where the FW BOOT 1 is a part responsible for booting and loading the operating system or other firmware during the device startup process, and is usually located in the initial part of the memory device to ensure that the system can be loaded correctly at the time of startup. FW BOOT 2 is typically used to restore the system when a problem occurs during BOOT. If the part of the firmware data is damaged or lost, the eMMC cannot respond to the read-write operation of HOST, so that the system or firmware inside the eMMC is damaged, and the OS Image or eMMC firmware needs to be updated and upgraded.
S403: the CPU system normally starts Boot OK.
S404: the SOC CPU reads eMMC state information.
Specifically, communication is performed between an SOC chip and the eMMC through an eMMC protocol, and instruction information for acquiring state information is transmitted to the eMMC through the SOC chip to acquire the eMMC state information in the storage space.
The processor of the SOC chip sends instruction information for obtaining the eMMC state information to the memory chip eMMC, where the instruction information is a specific instruction customized according to a user requirement, and when the memory chip eMMC receives the instruction information, the memory chip determines whether the received instruction information is the specific instruction, if it is determined that the instruction information is the specific instruction, sends correct eMMC running state information to the SOC CPU according to the received instruction information, and if it is determined that the memory chip eMMC receives the instruction information which is not the specific instruction or is an error instruction, the memory chip eMMC does not send corresponding eMMC running state information. The command information includes a custom command and parameter data, and when the received command information is determined to be a specific command, the address data of the eMMC state information is indexed according to the parameter data in the first command information, so as to determine the corresponding state information.
S405: the SOC CPU sends a Command (CMD) to eMMC.
Specifically, metadata information in the eMMC state information is detected, and whether the data information of the eMMC is abnormal is determined to determine an operation state of the eMMC. Here, when detecting that the eMMC operation state is abnormal, an alert is given to the eMMC, that is, a command is issued to debug the eMMC state according to the command.
Here, the range of standard state information of each state information related to the normal state of eMMC is preset, metadata information (Table Block) in the eMMC state information is acquired, the acquired metadata information is compared with the range of the set standard state information, if the acquired metadata information is not within the range of the set standard state information, the state information corresponding to the metadata information is determined to be abnormal, and if the acquired metadata information is within the range of the set standard state information, the state information corresponding to the metadata information is determined to be normal.
S406: keep the system running normally and solving by Issue.
In summary, in the method for monitoring the operation state of the eMMC provided in the foregoing embodiment, the SOC chip may obtain the operation state information of the eMMC in time, so that accuracy of the obtained eMMC state information is improved, and adjustment of the operation state of the eMMC according to the eMMC state information in time is facilitated.
Referring to fig. 6, an eMMC operation state monitoring system according to an embodiment of the present application includes an SOC chip, eMMC, and a memory DRAM, where,
the system comprises an SOC chip, an eMMC (state of charge) module and an eMMC controller, wherein the SOC chip is used for communicating between the SOC chip and the eMMC through an eMMC protocol and sending first instruction information to the eMMC through the SOC chip to acquire the eMMC state information; detecting the eMMC state information, and sending second instruction information for warning adjustment to the eMMC through the SOC chip when judging that the eMMC state information is abnormal so as to debug the eMMC;
an eMMC for presetting a storage space for storing eMMC state information in a memory in the eMMC; communicating with the SOC chip through the eMMC protocol, and sending the eMMC state information to the SOC chip in the storage space through the received first instruction information; and when judging that the eMMC state information is abnormal, entering a debugging mode according to the second instruction information so as to recover the normal operation of the eMMC.
In one embodiment, the SOC chip is specifically configured to:
transmitting first instruction information for acquiring eMMC state information to the eMMC through a processor of the SOC chip; the first instruction information comprises a custom command and parameter data;
And indexing according to the parameter data, and determining storage space address information related to the eMMC state information corresponding to the first instruction so as to acquire the eMMC state information in the storage space.
Specifically, the processor of the SOC chip sends first instruction information for acquiring the eMMC state information to the memory chip eMMC, where when the memory chip eMMC receives the first instruction information, it is determined whether the received first instruction information is a specific instruction customized according to a user requirement, if it is determined that the specific instruction is a specific instruction, correct eMMC running state information is sent to the SOC CPU according to the received first instruction information, if it is determined that the memory chip eMMC receives an instruction that the first instruction information is not a specific instruction or is wrong, the corresponding eMMC running state information is not sent. Here, the first instruction information includes a custom command and parameter data, and when it is determined that the received first instruction information is a specific instruction, address data of eMMC state information is indexed according to the parameter data in the first instruction information, and corresponding state information is determined.
In one embodiment, the SOC chip is specifically configured to:
detecting whether metadata information corresponding to the running state is in the range of set standard state information, and judging the running state of the eMMC;
And if the state information is not in the range of the standard state information, determining that the state information corresponding to the metadata is abnormal, wherein the operation state of the eMMC is abnormal.
Specifically, the range of standard state information of each state information related to the normal state of the eMMC is preset, metadata information (Table Block) in the eMMC state information is obtained, the obtained metadata information is compared with the range of the set standard state information, if the obtained metadata information is not in the range of the set standard state information, the state information corresponding to the metadata information is determined to be abnormal, and if the obtained metadata information is in the range of the set standard state information, the state information corresponding to the metadata information is determined to be normal.
In one embodiment, the eMMC is specifically configured to:
determining at least one storage space in the eMMC according to the set address information, and updating state information of the eMMC in real time in the storage space;
and acquiring the eMMC state information, and classifying according to the data type of the eMMC state information so as to distribute the eMMC state information to different storage spaces for storage.
Specifically, in the firmware operation process, through a storage medium NAND Flash, operation state information generated in the process of exchanging data between the eMMC and the CPU exists in a preset specific logical Block address of the NAND Flash, at least one storage space is determined through a fixed logical Block address, so that the obtained data types of the eMMC state information are classified, the eMMC state information is distributed to different storage spaces to be stored, where the operation state information of the eMMC includes an operation state of the eMMC and metadata information (Table Block) information corresponding to the operation state.
Wherein, the state information of the eMMC may be a health state of the eMMC, including: indexes such as bad block number, residual life, erasure count and the like are used for evaluating the service life and the data information of the performance of the memory; the read-write state of the eMMC may be a read-write state of the eMMC, including a read-write speed of NAND in the current eMMC for data information, for evaluating performance of the memory; may be power supply voltage and current information, power supply information of eMMC, including voltage and current, in order to monitor stability of the power supply, etc.
In one embodiment, the eMMC is specifically configured to:
when judging that the running state of the eMMC is abnormal, receiving second instruction information sent by the SOC chip;
After receiving the second instruction information, the eMMC writes the data of the second instruction information into a control register of the eMMC and enters a debugging mode so as to adjust the state of the eMMC according to the second instruction information and restore the normal working state of the eMMC.
Specifically, after receiving the second instruction information, the eMMC writes parameter data of the second instruction information into a control register of the eMMC, and performs a debug mode. The second instruction information includes abnormal eMMC state information, parameter data corresponding to the abnormal eMMC running state, a specific debugging module, parameter data to be debugged, and the like. Here, in the debug mode of eMMC, the fault may be eliminated in the form of upgrading the firmware with the interface, limiting the read-write function, performing algorithm adjustment, etc. according to the second instruction information, or the state of eMMC may be optimally adjusted to restore the normal operation of eMMC and the normal operation function of the system.
In summary, in the operation state monitoring system of eMMC provided in the above embodiment, the storage space of the eMMC state information is determined by the processing module, the communication between the SOC chip and the eMMC is established by the communication module to obtain the eMMC state information, the operation state of the eMMC is determined by detecting the eMMC state information by the detection module, the accuracy of the obtained eMMC state information is improved, and the operation state of the eMMC is adjusted in time according to the eMMC state information.
The method provided in the foregoing embodiments will be described in detail by way of a specific example based on the same inventive concept as the foregoing embodiments.
As shown in fig. 6, three major components of the peripheral circuit in the end product, namely, a central processing unit CPU, a memory DRAM, and a storage device eMMC are determined. The SOC CPU communicates with the eMMC through the eMMC protocol, sends instruction information for obtaining eMMC state information to the eMMC, and, correspondingly, after receiving the instruction information, the Host Controller (Host Controller) in the eMMC obtains the eMMC state information stored in the NAND flash memory chip through the NAND Bus (NAND Bus), and feeds back the obtained eMMC state information to the SOC CPU. Here, the SOC CPU stores the acquired eMMC state information in a memory DRAM after receiving the eMMC state information, where the memory may be a DDR or an LPDDR. Meanwhile, the acquired eMMC state information is judged, the running state of the eMMC is determined, if the state information of the eMMC is detected to be abnormal, an alarm command is sent to the eMMC through the SOC CPU, and the eMMC enters a debugging mode when receiving the alarm command correspondingly, so that faults are eliminated through modes of upgrading firmware, adjusting an algorithm and the like, and normal operation of the eMMC and normal operation functions of a system are recovered.
Based on the same inventive concept as the previous embodiments, an embodiment of the present invention provides an eMMC operation state monitoring device, as shown in fig. 7, including: a processor 510 and a memory 511 in which a computer program is stored; the number of processors 510 illustrated in fig. 7 is not used to refer to one processor 510, but is merely used to refer to a positional relationship of the processors 510 with respect to other devices, and in practical applications, the number of processors 510 may be one or more; likewise, the memory 511 illustrated in fig. 7 is also used in the same sense, that is, only to refer to the positional relationship of the memory 511 with respect to other devices, and in practical applications, the number of the memories 511 may be one or more. When the processor 510 runs the computer program, an operation state monitoring method of the eMMC applied to the above-described device is implemented.
The apparatus may further include: at least one network interface 512. The various components in the device are coupled together by a bus system 513. It is appreciated that the bus system 513 is operable to facilitate connective communication between the components. The bus system 513 includes a power bus, a control bus, and a status signal bus in addition to the data bus. But for clarity of illustration, the various buses are labeled as bus system 513 in fig. 7.
The memory 511 may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. Wherein the nonvolatile Memory may be Read Only Memory (ROM), programmable Read Only Memory (PROM, programmable Read-Only Memory), erasable programmable Read Only Memory (EPROM, erasable Programmable Read-Only Memory), electrically erasable programmable Read Only Memory (EEPROM, electrically Erasable Programmable Read-Only Memory), magnetic random access Memory (FRAM, ferromagnetic random access Memory), flash Memory (Flash Memory), magnetic surface Memory, optical disk, or compact disk Read Only Memory (CD-ROM, compact Disc Read-Only Memory); the magnetic surface memory may be a disk memory or a tape memory. The volatile memory may be random access memory (RAM, random Access Memory), which acts as external cache memory. By way of example, and not limitation, many forms of RAM are available, such as static random access memory (SRAM, static Random Access Memory), synchronous static random access memory (SSRAM, synchronous Static Random Access Memory), dynamic random access memory (DRAM, dynamic Random Access Memory), synchronous dynamic random access memory (SDRAM, synchronous Dynamic Random Access Memory), double data rate synchronous dynamic random access memory (ddr SDRAM, double Data Rate Synchronous Dynamic Random Access Memory), enhanced synchronous dynamic random access memory (ESDRAM, enhanced Synchronous Dynamic Random Access Memory), synchronous link dynamic random access memory (SLDRAM, syncLink Dynamic Random Access Memory), direct memory bus random access memory (DRRAM, direct Rambus Random Access Memory). The memory 511 described in embodiments of the present invention is intended to comprise, without being limited to, these and any other suitable types of memory.
The memory 511 in the embodiment of the present invention is used to store various types of data to support the operation of the apparatus. Examples of such data include: any computer program for operating on the device, such as an operating system and application programs; contact data; telephone book data; a message; a picture; video, etc. The operating system includes various system programs, such as a framework layer, a core library layer, a driver layer, and the like, for implementing various basic services and processing hardware-based tasks. The application programs may include various application programs such as a Media Player (Media Player), a Browser (Browser), etc. for implementing various application services. Here, a program for implementing the method of the embodiment of the present invention may be included in an application program.
Based on the same inventive concept as the previous embodiments, the present embodiment further provides a computer readable storage medium having a computer program stored therein, where the computer readable storage medium may be a Memory such as a magnetic random access Memory (FRAM, ferromagnetic random access Memory), a Read Only Memory (ROM), a programmable Read Only Memory (PROM, programmable Read-Only Memory), an erasable programmable Read Only Memory (EPROM, erasable Programmable Read-Only Memory), an electrically erasable programmable Read Only Memory (EEPROM, electrically Erasable Programmable Read-Only Memory), a Flash Memory (Flash Memory), a magnetic surface Memory, a compact disc, or a compact disc Read Only Memory (CD-ROM, compact Disc Read-Only Memory); but may be a variety of devices including one or any combination of the above-described memories, such as a mobile phone, computer, tablet device, personal digital assistant, or the like. The method for monitoring the operation state of the eMMC applied to the above device is implemented when a computer program stored in the computer-readable storage medium is executed by a processor. The specific step flow implemented when the computer program is executed by the processor is described with reference to the embodiment shown in fig. 1, and will not be described herein.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
In this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a list of elements is included, and may include other elements not expressly listed.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. The method for monitoring the running state of the embedded multimedia card eMMC is applied to an SOC chip and is characterized by comprising the following steps of:
communication is carried out between an SOC chip and the eMMC through an eMMC protocol, and first instruction information is sent to the eMMC through the SOC chip so as to determine storage space address information corresponding to the first instruction and related to eMMC state information, so that eMMC state information in the storage space is obtained;
Detecting the eMMC state information, and sending second instruction information for warning adjustment to the eMMC through the SOC chip when judging that the eMMC state information is abnormal so as to debug the eMMC.
2. The method according to claim 1, wherein the communicating between the SOC chip and the eMMC through an eMMC protocol and sending, by the SOC chip, first instruction information to the eMMC to determine memory space address information related to eMMC state information corresponding to the first instruction, to obtain eMMC state information in the memory space, includes:
transmitting first instruction information for acquiring eMMC state information to the eMMC through a processor of the SOC chip;
the first instruction information comprises a custom command and parameter data;
and indexing according to the parameter data, and determining storage space address information related to the eMMC state information corresponding to the first instruction so as to acquire the eMMC state information in the storage space.
3. The method of claim 1, wherein the eMMC status information includes an operation status of the eMMC and metadata information corresponding to the operation status, the detecting the eMMC status information, and when determining that the eMMC status information is abnormal, sending, by the SOC chip, second instruction information for warning adjustment to the eMMC to debug the eMMC, including:
Detecting whether metadata information corresponding to the running state is in the range of set standard state information, and judging the running state of the eMMC;
and if the state information is not in the range of the standard state information, determining that the state information corresponding to the metadata is abnormal, wherein the operation state of the eMMC is abnormal.
4. An operation state monitoring method of an embedded multimedia card eMMC, which is applied to the eMMC, is characterized by comprising the following steps:
presetting a storage space for storing eMMC state information in a memory in the eMMC;
communication is carried out through an eMMC protocol, communication is carried out with an SOC chip, storage space address information related to eMMC state information corresponding to a first instruction is determined through received first instruction information, and the eMMC state information is sent to the SOC chip in the storage space;
and when judging that the eMMC state information is abnormal, entering a debugging mode according to the second instruction information so as to recover the normal operation of the eMMC.
5. The method of claim 4, wherein presetting a memory space for storing eMMC status information in the memory in the eMMC comprises:
determining at least one storage space in the eMMC according to the set address information, and updating state information of the eMMC in real time in the storage space;
And acquiring the eMMC state information, and classifying according to the data type of the eMMC state information so as to distribute the eMMC state information to different storage spaces for storage.
6. The method of claim 4, wherein the entering a debug mode according to second instruction information to resume normal operation of eMMC when the eMMC state information is determined to be abnormal, comprises:
when judging that the running state of the eMMC is abnormal, receiving second instruction information sent by the SOC chip;
after receiving the second instruction information, the eMMC writes the data of the second instruction information into a control register of the eMMC and enters a debugging mode so as to adjust the state of the eMMC according to the second instruction information and restore the normal working state of the eMMC.
7. An eMMC operation state monitoring system is characterized in that the system comprises an SOC chip, an eMMC and a memory DRAM, wherein,
the system comprises an SOC chip, an eMMC (state of charge) module and an eMMC controller, wherein the SOC chip is used for communicating between the SOC chip and the eMMC through an eMMC protocol and sending first instruction information to the eMMC through the SOC chip to acquire the eMMC state information; detecting the eMMC state information, and sending second instruction information for warning adjustment to the eMMC through the SOC chip when judging that the eMMC state information is abnormal so as to debug the eMMC;
A memory device eMMC for presetting a memory space for storing eMMC state information in a memory in the eMMC; communication is carried out through an eMMC protocol, communication is carried out with an SOC chip, storage space address information related to eMMC state information corresponding to a first instruction is determined through received first instruction information, and the eMMC state information is sent to the SOC chip in the storage space; and when judging that the eMMC state information is abnormal, entering a debugging mode according to the second instruction information so as to recover the normal operation of the eMMC.
8. The system according to claim 7, characterized in that said SOC chip is in particular adapted to:
transmitting first instruction information for acquiring eMMC state information to the eMMC through a processor of the SOC chip;
the first instruction information comprises a custom command and parameter data;
and indexing according to the parameter data, and determining address information of a storage space related to the eMMC state information corresponding to the first instruction information so as to acquire the eMMC state information in the storage space.
9. An eMMC operation state monitoring device, comprising:
a processor;
a memory for storing the processor-executable instructions;
Wherein the processor is configured to execute the instructions to implement the method of monitoring an operational state of an eMMC according to any one of claims 1-6.
10. The computer-readable storage medium, wherein the instructions in the computer-readable storage medium, when executed by a processor, implement the method of monitoring an operational state of an eMMC according to any one of claims 1-6.
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