CN116801479A - Circuit board and processing method thereof - Google Patents
Circuit board and processing method thereof Download PDFInfo
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- CN116801479A CN116801479A CN202210255937.8A CN202210255937A CN116801479A CN 116801479 A CN116801479 A CN 116801479A CN 202210255937 A CN202210255937 A CN 202210255937A CN 116801479 A CN116801479 A CN 116801479A
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- solder resist
- resist ink
- hole
- ink block
- processed
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- 238000003672 processing method Methods 0.000 title claims abstract description 18
- 229910000679 solder Inorganic materials 0.000 claims abstract description 169
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims abstract description 121
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 90
- 229910052802 copper Inorganic materials 0.000 claims abstract description 78
- 239000010949 copper Substances 0.000 claims abstract description 78
- 229910052763 palladium Inorganic materials 0.000 claims abstract description 63
- 238000005553 drilling Methods 0.000 claims abstract description 28
- 238000000576 coating method Methods 0.000 claims abstract description 26
- 239000011248 coating agent Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims description 36
- 238000007747 plating Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 9
- 239000012670 alkaline solution Substances 0.000 claims description 8
- 238000005238 degreasing Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 7
- 238000003825 pressing Methods 0.000 claims description 7
- 238000009713 electroplating Methods 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- 238000003486 chemical etching Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 239000011889 copper foil Substances 0.000 description 12
- 230000000694 effects Effects 0.000 description 8
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- -1 palladium ions Chemical class 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 239000000084 colloidal system Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 239000004925 Acrylic resin Substances 0.000 description 4
- 229920000178 Acrylic resin Polymers 0.000 description 4
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 4
- 229910001431 copper ion Inorganic materials 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 238000005562 fading Methods 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- 238000001035 drying Methods 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 208000015181 infectious disease Diseases 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- UIIMBOGNXHQVGW-DEQYMQKBSA-M Sodium bicarbonate-14C Chemical compound [Na+].O[14C]([O-])=O UIIMBOGNXHQVGW-DEQYMQKBSA-M 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 150000001450 anions Chemical class 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000009545 invasion Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The application discloses a circuit board and a processing method thereof, wherein the processing method of the circuit board comprises the following steps: obtaining a plate to be treated, wherein the plate to be treated comprises a first solder resist ink block and a second solder resist ink block which are correspondingly arranged; drilling through holes on the obtained plate to be treated, wherein the through holes penetrate through the first solder resist ink block and the second solder resist ink block; palladium is applied to the wall of the drilled through hole, and oil removal treatment is carried out on the first solder resist ink block and the second solder resist ink block, so that the wall of the through hole is free of palladium at the positions of the first solder resist ink block and the second solder resist ink block; and (3) coating copper on the hole wall of the through hole subjected to oil removal treatment, wherein the hole wall of the through hole is not coated with copper at the palladium-free position. According to the circuit board processing method, the hole wall of the metallized hole is selectively coated with copper in the copper coating process of forming the metallized hole, back drilling treatment is not needed for the through hole after copper coating, and the problem that the electric connection between the multilayer circuit board and the board is influenced by the residual end due to the back drilling precision problem is avoided.
Description
Technical Field
The application relates to the technical field of circuit board processing and manufacturing, in particular to a circuit board and a processing method thereof.
Background
The printed circuit board (Printed Circuit Boards, PCB) is a support for the electronic components and also a carrier for the electrical connections between the electronic components. In multilayer PCB boards, metallized holes (plated through hole, PTH) are typically used to make electrical connections to different signal layers.
In the related art, in forming a metallization hole, a through hole is generally directly drilled on a PCB board, and then electroless copper plating and electroplating are performed on the inner wall of the through hole to form a metal layer for connecting signal layers. Wherein the formed metallized holes do not need to electrically connect all conductive layers. Copper removal is required for the metallized holes between conductive layers that do not need to be electrically connected, and in particular copper removal is typically performed by back drilling, which is not used for signal transmission. As shown in fig. 1, the circuit board shown in fig. 1 has 4 layers of copper foils from top to bottom, and when the upper two layers of copper foils in the 4 layers of copper foils need to be electrically connected and the lower two layers of copper foils need not to be electrically connected, back drilling treatment is required to be performed on the part of the metallized hole, and the back drilling is to perform depth control drilling by using a drill bit with a larger hole diameter than the through hole so as to remove a hole wall copper layer in a certain depth. However, in practical application, due to the influence of the precision of the processing drill, when the back drilling operation is performed on the multi-layer PCB board, there is a back drilling stub easily, that is, the portion marked with a in fig. 1, and the back drilling of the copper layer of the portion cannot be removed completely, so that the connection effect of the PCB layers can be affected.
Disclosure of Invention
The application mainly solves the technical problem of providing a circuit board and a processing method thereof, which can effectively solve the problem that when a multilayer PCB board carries out back drilling on a metallized hole, the residual end affects the electrical connection between the multilayer circuit board and the board due to the back drilling precision problem.
In order to solve the technical problems, a first technical scheme adopted by the application is to provide a circuit board processing method, which comprises the following steps: obtaining a plate to be treated, wherein the plate to be treated comprises a first solder resist ink block and a second solder resist ink block which are correspondingly arranged; drilling through holes on the obtained plate to be treated, wherein the through holes penetrate through the first solder resist ink block and the second solder resist ink block; palladium is applied to the wall of the drilled through hole, and oil removal treatment is carried out on the first solder resist ink block and the second solder resist ink block, so that the wall of the through hole is free of palladium at the positions of the first solder resist ink block and the second solder resist ink block; and (3) coating copper on the hole wall of the through hole subjected to oil removal treatment, wherein the hole wall of the through hole is not coated with copper at the palladium-free position.
The diameters of the first solder resist ink block and the second solder resist ink block are larger than the diameter of the through hole.
Wherein, obtain the board that waits to handle, wait to handle the step that board includes first solder mask printing ink piece and second solder mask printing ink piece that corresponds the setting, specifically include: obtaining a first plate to be processed, and printing solder resist ink at a first preset position on the first plate to be processed to form a first solder resist ink block; obtaining a second plate to be processed, and printing solder resist ink at a second preset position on the second plate to be processed to form a second solder resist ink block; and performing pressing treatment on the first plate to be processed and the second plate to be processed, and enabling the first solder resist ink block to correspond to the second solder resist ink block so as to obtain the plate to be processed.
Wherein, before carrying out the pressfitting processing to first plate to be processed and second plate to be processed to make first solder mask ink piece correspond with second solder mask ink piece, in order to obtain the step of waiting to process the panel, still include: and carrying out browning treatment on the first plate to be processed and the second plate to be processed.
The palladium plating step is carried out on the wall of the drilled through hole, and specifically comprises the following steps: and plating palladium on the walls of the drilled through holes by adopting chemical palladium plating.
The method comprises the steps of carrying out oil removal treatment on a first solder resist ink block and a second solder resist ink block to ensure that the hole wall of a through hole is palladium-free at the positions of the first solder resist ink block and the second solder resist ink block, and specifically comprises the following steps: and dissolving the first solder resist ink block and the second solder resist ink block by using alkaline solution, so that the hole wall of the through hole is palladium-free at the positions of the first solder resist ink block and the second solder resist ink block.
The method comprises the steps of coating copper on the hole wall of the through hole subjected to palladium coating treatment, wherein the hole wall of the through hole is not coated with copper at a palladium-free position, and the method specifically comprises the following steps of: and carrying out electroless copper deposition on the hole wall of the through hole subjected to palladium deposition treatment, wherein copper is not deposited on the hole wall of the through hole at the position without palladium, and electroplating the hole wall of the through hole subjected to electroless copper deposition treatment.
Wherein, still include: etching the hole wall of the through hole after copper coating treatment to remove copper between the first solder resist ink block and the second solder resist ink block on the hole wall of the through hole.
The method for removing copper on the through hole wall comprises the following steps of etching the through hole wall after copper coating treatment to remove copper between a first solder resist ink block and a second solder resist ink block on the through hole wall, and specifically comprises the following steps: and carrying out chemical etching treatment on the hole wall of the through hole after copper coating treatment to remove copper between the first solder resist ink block and the second solder resist ink block on the hole wall of the through hole. In order to solve the technical problems, a second technical scheme adopted by the application is to provide a circuit board which is processed by any one of the circuit board processing methods.
The beneficial effects of the application are as follows: compared with the prior art, the circuit board processing method and the circuit board provided by the application have the advantages that the multilayer circuit board provided with the solder resist ink blocks is obtained, the through holes are controlled to penetrate through the solder resist ink blocks during the through holes, palladium is applied to the through holes and the oil is removed, the solder resist ink blocks can be dissolved in the oil removing process, meanwhile, palladium in the corresponding area of the solder resist ink blocks can be removed along with the solder resist ink blocks through the through holes, copper is not covered at the preset position of the through holes preset with quick solder resist ink when the through holes subjected to the oil removing process are coated with copper again, the selective copper coating of the appointed area of the through holes is realized by the circuit board processing method, back drilling treatment is not needed after metallized holes are manufactured, back drilling stubbles are not generated, and the PCB connecting effect of each layer is not influenced by the existence of stubbles.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:
fig. 1 is a schematic diagram of a structure of a multilayer PCB through hole after back drilling in the prior art;
FIG. 2 is a schematic flow chart of an embodiment of a circuit board processing method according to the present application;
FIG. 3 is a flowchart of an embodiment of a method for obtaining the sheet material to be processed in S11 in the flowchart of FIG. 2;
FIG. 4 is a schematic view showing the structure of an embodiment of the board to be processed obtained in the embodiment of FIG. 3 according to the present application;
fig. 5 is a schematic view of the structure of the board to be processed obtained in fig. 4 after drilling a through hole.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to fall within the scope of the present application.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plurality" generally includes at least two, but does not exclude the case of at least one.
It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
It should be understood that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
The electrical connection between the plates of the multi-layer PCB is generally achieved through the metallized holes on the multi-layer PCB, after the metallized holes are formed, copper in the corresponding areas of the PCB, which are not required to be connected together, is generally removed through back drilling, however, the back drilling is easy to cause the existence of back drilling stubs due to the influence of processing precision, and the existence of stubs can influence the connection effect of the PCB of each layer.
Based on the above problems, the present application provides a circuit board and a processing method thereof, which can cover copper on a designated area of a through hole of a multilayer circuit board, the through hole between boards which are not required to be connected on the multilayer circuit board is not covered with copper, no additional back drilling operation is required after copper is covered, no residual end is generated, and the problems can be effectively solved.
The circuit board and the processing method thereof provided by the application are described in detail below with reference to the accompanying drawings and embodiments.
Referring to fig. 2, fig. 2 is a flow chart of an embodiment of a circuit board processing method according to the present application, as shown in fig. 2, in this embodiment, the method includes:
s11: and obtaining a plate to be treated, wherein the plate to be treated comprises a first solder resist ink block and a second solder resist ink block which are correspondingly arranged.
In this embodiment, the board to be processed is obtained by laminating a plurality of PCB boards.
Specifically, referring to fig. 3, fig. 3 is a flow chart of an embodiment of a method for obtaining the board to be processed in S11. As shown in fig. 3, in the present embodiment, the method includes:
s21: and obtaining a first plate to be processed, and printing solder resist ink at a first preset position on the first plate to be processed to form a first solder resist ink block.
In the present embodiment, the main components of the solder resist ink are epoxy resin and acrylic resin, wherein specific types of the epoxy resin and the acrylic resin are not limited. The first plate to be processed is a substrate with patterned copper foil on both sides, and the substrate is a dielectric layer. The first solder resist ink block is formed by printing solder resist ink on a preset position on one surface of a first plate to be processed, drying the solder resist ink, and evaporating solvent contained in the solder resist ink to solidify the solder resist ink to form the first solder resist ink block.
The number of the first preset positions is at least one, and the specific number of the first preset positions can be determined according to the number of the metallized holes which need to be formed on the board to be processed later.
S22: and obtaining a second plate to be processed, and printing solder resist ink at a second preset position on the second plate to be processed to form a second solder resist ink block.
Specifically, the main components of the solder resist ink are epoxy resin and acrylic resin, wherein the specific types of the epoxy resin and the acrylic resin are not limited. The second plate to be processed is a substrate with patterned copper foil on both sides, and the substrate is a dielectric layer. The second solder resist ink block is formed by printing solder resist ink on a preset position on one surface of the second plate to be processed, drying the solder resist ink, and evaporating the solvent contained in the solder resist ink to solidify the solder resist ink to form the second solder resist ink block.
Wherein, the second preset position is at least one, and the specific number of the second preset position is the same as the number of the first preset position. The number of the metallized holes to be formed in the sheet to be processed can be determined according to the subsequent need, and the application is not limited thereto.
S23: and performing pressing treatment on the first plate to be processed and the second plate to be processed, and enabling the first solder resist ink block to correspond to the second solder resist ink block so as to obtain the plate to be processed.
Specifically, the first plate to be processed and the second plate to be processed are both substrates with copper foils coated with patterns on both sides. The pressing refers to combining two or more layers of the same or different materials into a whole by heating and pressurizing with or without an adhesive, sequentially laminating a first plate to be processed, a non-conductive medium bonding layer and a second plate to be processed, and riveting and fixing after hot melting. In this embodiment, after the first plate to be processed and the second plate to be processed are pressed together, the plate to be processed includes a non-conductive medium layer between the two plates, and the obtained plate to be processed has four copper foil layers respectively located on two sides of the first plate to be processed and the second plate to be processed. And when the pressing operation is performed, controlling the two sides of the two plates to be processed, on which the solder resist ink blocks are formed, to be relatively close to the pressing.
In this embodiment, before the first to-be-processed plate and the second to-be-processed plate are pressed, the first to-be-processed plate and the second to-be-processed plate are required to be browned.
Specifically, the surface of the copper foil of the first plate to be processed and the surface of the copper foil of the second plate to be processed are microetched by using a brown liquid to generate a layer of extremely thin and uniform organic metal conversion film, so that the surface of the copper is enabled to obtain a stable micro-rugged surface shape.
Referring to fig. 4, fig. 4 is a schematic structural diagram of an embodiment of a board to be processed obtained in the embodiment of fig. 3 according to the present application.
As shown in fig. 4, the board to be processed includes a first board to be processed 401, a second board to be processed 402, and a dielectric layer 403 between the first board to be processed and the second board to be processed.
Wherein, copper foils (not labeled) are coated on two sides of the first plate to be processed, copper foils are coated on two sides of the second plate to be processed, and the first solder resist ink block 405 on one side of the first plate to be processed and the second solder resist ink block 404 on one side of the second plate to be processed are correspondingly arranged.
S12: and drilling through holes on the obtained plate to be processed, wherein the through holes penetrate through the first solder resist ink block and the second solder resist ink block.
The diameters of the first solder resist ink block and the second solder resist ink block are larger than the diameter of the through hole.
In the embodiment, through hole processing is performed on the plate to be processed by machining or laser ablation, in the through hole drilling process, the diameter of the through hole is controlled to be smaller than the diameters of the first solder resist ink block and the second solder resist ink block, and the through hole penetrates through the first solder resist ink block and the second solder resist ink block. Specifically, a schematic structural diagram of the board to be processed obtained in fig. 4 after drilling a through hole is shown in fig. 5.
S13: and (3) palladium is applied to the wall of the drilled through hole, and oil removal treatment is carried out on the first solder resist ink block and the second solder resist ink block, so that the wall of the through hole is free of palladium at the positions of the first solder resist ink block and the second solder resist ink block.
The palladium plating step is carried out on the wall of the drilled through hole, and specifically comprises the following steps: and plating palladium on the walls of the drilled through holes by adopting chemical palladium plating. The electroless palladium plating is to soak the through holes with a solution containing palladium to make the through holes absorb palladium. In this embodiment, before electroless palladium plating is performed on the walls of the drilled through-holes, the through-holes must first be alkaline degreased to remove plate surface oil stains, fingerprints, oxides, and hole dust. The pore wall is adjusted from negative charge to positive charge, which is convenient for the adsorption of colloid palladium in the subsequent process. The alkaline degreasing process is a desmutting process, so that the solder resist ink is selected to be desmutted by an alkaline solvent in the previous process for avoiding the complete falling of the solder resist ink block. After the through holes are subjected to the contamination removal treatment, the plate to be treated is placed into a palladium tank containing palladium solution for the infection treatment, so that anions on the walls of the through holes adsorb positively charged palladium. Note that prior to this process, a pre-dip treatment is required, which is to first wet the sheet material to be treated with a palladium-containing solution. The pre-invasion treatment avoids the plate to be treated from directly invading the palladium tank, can avoid the pollution of palladium liquid in the palladium tank, and prolongs the service life of the palladium tank. After the plate to be treated is placed into a palladium tank containing palladium for infection treatment, palladium is adsorbed on the wall of a through hole of the plate to be treated, wherein the palladium contains colloidal palladium and ionic palladium, and colloid palladium in the plate is required to be treated by de-colloid to remove stannous ions wrapped outside colloid palladium particles, so that palladium cores in the colloid particles are exposed, and the palladium adsorbs copper ions in the subsequent copper coating process.
After palladium treatment, palladium ions are adsorbed on the hole walls of the through holes of the plates to be treated, palladium ions are also adsorbed at the positions corresponding to the first solder resist ink blocks and the second solder resist ink blocks, and then oil removal treatment is required for the through holes, so that the first solder resist ink blocks and the second solder resist ink blocks are dissolved, and palladium ions adsorbed in the areas of the first solder resist ink blocks and the second solder resist ink blocks on the hole walls of the through holes are removed.
The step of degreasing the first solder resist ink block and the second solder resist ink block to ensure that the hole wall of the through hole is palladium-free at the positions of the first solder resist ink block and the second solder resist ink block comprises the following steps: and dissolving the first solder resist ink block and the second solder resist ink block by using alkaline solution, so that the hole wall of the through hole is palladium-free at the positions of the first solder resist ink block and the second solder resist ink block. Specifically, in the present embodiment, the alkaline solute contained in the alkaline solution for degreasing is sodium hydroxide, and in other embodiments, the solute of the alkaline solution may be sodium bicarbonate, potassium hydroxide, or the like, which is not limited in the present application. Note that, in order to avoid the alkaline solution from damaging other areas of the through hole wall when the first solder resist ink stick and the second solder resist ink stick are rinsed, the solder resist ink forming the solder resist ink in this embodiment has a good rinsing function, and the rinsing time is controlled to be not more than 50 minutes, and in this embodiment, the rinsing time is preferably 40 minutes. Meanwhile, the minimum oil fading temperature is not lower than 25 ℃, and the maximum oil fading temperature is not higher than 95 ℃. It is easy to understand that increasing the temperature has a positive effect on the dissolution effect of the solder resist ink, and solder resist ink blocks below 25 ℃ are difficult to dissolve in alkaline solution, so that the temperature needs to be set to be higher than 25 ℃ and cannot be higher than 95 ℃ to prevent palladium ions in other areas of the hole walls of the through holes from being washed away due to the high temperature. In this embodiment, the fade temperature is preferably 50 ℃.
S14: and (3) coating copper on the hole wall of the through hole subjected to oil removal treatment, wherein the hole wall of the through hole is not coated with copper at the palladium-free position.
Wherein, the step of covering copper on the hole wall of the through hole which is treated by palladium, and the hole wall of the through hole is not attached with copper at the position without palladium comprises the following steps: and carrying out electroless copper deposition on the hole wall of the through hole subjected to the palladium plating treatment, wherein copper is not deposited on the hole wall of the through hole at the position without palladium, and electroplating the hole wall of the through hole subjected to the electroless copper deposition treatment. Specifically, the chemical copper deposition is to soak the hole wall of the through hole with copper ion-containing solution, and the negative palladium ions on the hole wall of the through hole adsorb the positive copper ions in the solution, so that the hole wall of the through hole is covered with a layer of thin copper. Since the step S13 is performed after palladium is deposited on the wall of the through hole, the degreasing and washing-out process is performed on the first solder mask ink block and the second solder mask ink block on the wall of the through hole, and palladium ions adsorbed on the surface of the solder mask ink block are removed at the same time. The corresponding area of the hole wall of the through hole is palladium-free after treatment, and copper ions cannot be adsorbed in the palladium-free area in the chemical copper deposition process of the step, so that a layer of thin copper cannot be covered. Accordingly, subsequent electroplating of this area with no conductive thin copper also results in failure to form a copper layer.
Through the mode, the selective copper coating is realized on the hole wall of the through hole of the multilayer circuit board. Copper is coated between circuit boards which are required to be electrically connected by the multi-layer circuit board. And a solder resist ink block is arranged between circuit boards which do not need to be electrically connected in the multilayer circuit board, and is removed by alkaline solution after palladium on the wall of the through hole in the copper coating process, so that palladium does not exist at the solder resist ink fast position of the wall of the through hole at a preset position, and copper cannot be coated in the subsequent copper coating process. The selective copper coating method ensures that the subsequent back drilling operation is not needed to remove copper in certain areas of the metallized holes after the metal through holes are formed, so that no stub is generated, and the problem that the connection of each layer of PCB is affected due to the existence of the stub is avoided.
In this embodiment, after the copper-clad processing is performed on the wall of the through hole, the method further includes: etching the wall of the through hole after copper coating treatment to remove copper between the first solder resist ink block and the second solder resist ink block on the wall of the through hole, comprising: and carrying out chemical etching treatment on the hole wall of the through hole after copper coating treatment to remove copper between the first solder resist ink block and the second solder resist ink block on the hole wall of the through hole. Specifically, etching away copper between the first solder resist ink stick and the second solder resist ink stick can further ensure that the first plate to be processed and the second plate to be processed are in a state of no electrical connection.
Note that in this embodiment, the obtained board to be processed includes a first solder resist ink block and a second solder resist ink block. A dielectric layer is arranged between the first solder resist ink block and the second solder resist ink block of the hole wall of the through hole, copper is covered between the first solder resist ink block and the second solder resist ink block during copper covering treatment, the existence of copper in the region does not influence the electric connection effect between circuit boards, and the subsequent removal of copper between the two solder resist ink blocks through etching can be selected, so that the state that the first plate to be processed and the second plate to be processed are not electrically connected is further ensured. In other embodiments, the thickness of the first solder resist ink block and the second solder resist ink block may be adjusted by controlling the thickness of the printing solder resist ink, or the thickness of the dielectric layer may be controlled, so that after the first board to be processed and the second board to be processed are pressed together, the first solder resist ink block and the second solder resist ink block are in complete contact, and no dielectric layer is formed therebetween, and after the subsequent degreasing treatment, copper is covered on the metallized holes between the first board to be processed and the second board to be processed, so that the non-electrically connected state is achieved.
In this embodiment, the obtained plate to be processed is formed by pressing the first plate to be processed and the second plate to be processed. In other embodiments, the board to be processed may further include a third board to be processed and a fourth board to be processed. The metallization holes may also be realized by selectively coating copper after forming solder resist ink bumps between the plates that do not require electrical connection so that some two layers are not electrically connected. The present application is not particularly limited herein.
Further, in this embodiment, parameters related to the formation and degreasing process of the solder resist ink are controlled, so that the subsequent selective copper coating has a better effect, as shown in the following table 1.
TABLE 1
For example, when the total thickness of the obtained plates to be treated is greater than 0.025mm and less than or equal to 0.8 mm, the thickness of the solder resist ink block is controlled to be not less than 20um and not more than 30um when the solder resist ink block is formed, so that copper-free coverage of a designated area where the thickness of the solder resist ink block with enough thickness forms a metallized hole can be ensured, and the two plates are ensured not to be electrically connected. When the total thickness of the obtained plate to be treated is more than 0.025mm and less than or equal to 0.8 mm, controlling the weight percentage of the oil removal liquid NaOH to be not less than 0.01% and not more than 30%; the oil fading temperature is not less than 25 ℃ and not more than 85 ℃; the oil fading time is not less than 0.01min and not more than 30min; this setting can guarantee to hinder and weld the effect of washing of printing ink piece and can not cause the palladium on the through-hole pore wall to drop again.
Correspondingly, the application provides a circuit board which is manufactured by the processing method.
Compared with the prior art, the metallized holes of the circuit board of the embodiment are partially disconnected through selective copper coating, back drilling treatment of the metallized holes is not needed, no residual ends exist, the electrical connection effect of the boards of the multilayer board is better, dust in the back drilling process is not generated, and the influence on equipment and human health is avoided.
The foregoing description is only of embodiments of the present application and is not intended to limit the scope of the application, and all equivalent structures or equivalent principle changes made by the specification and drawings of the present application, or direct or indirect application in other related technical fields are included in the scope of the present application.
Claims (10)
1. The circuit board processing method is characterized by comprising the following steps of:
obtaining a plate to be treated, wherein the plate to be treated comprises a first solder resist ink block and a second solder resist ink block which are correspondingly arranged;
drilling through holes in the obtained plate to be processed, wherein the through holes penetrate through the first solder resist ink blocks and the second solder resist ink blocks;
palladium is carried out on the wall of the drilled through hole, and oil removal treatment is carried out on the first solder resist ink block and the second solder resist ink block, so that palladium does not exist on the wall of the through hole at the positions of the first solder resist ink block and the second solder resist ink block;
and coating copper on the hole wall of the through hole subjected to oil removal treatment, wherein the hole wall of the through hole is not coated with copper at the palladium-free position.
2. The method for manufacturing a circuit board according to claim 1, wherein,
the diameters of the first solder resist ink block and the second solder resist ink block are larger than the diameter of the through hole.
3. The method for processing a circuit board according to claim 1, wherein the step of obtaining a board to be processed, the board to be processed includes a first solder resist ink block and a second solder resist ink block which are correspondingly arranged, specifically includes:
obtaining a first plate to be processed, and printing solder resist ink at a first preset position on the first plate to be processed to form a first solder resist ink block;
obtaining a second plate to be processed, and printing the solder resist ink at a second preset position on the second plate to be processed to form a second solder resist ink block;
and carrying out pressing treatment on the first plate to be processed and the second plate to be processed, and enabling the first solder resist ink block to correspond to the second solder resist ink block so as to obtain the plate to be processed.
4. The method for processing a circuit board according to claim 3, further comprising, before the step of performing a press-fit process on the first board to be processed and the second board to be processed and associating the first solder resist ink block with the second solder resist ink block to obtain the board to be processed:
and carrying out browning treatment on the first plate to be processed and the second plate to be processed.
5. The method for processing a circuit board according to claim 1, wherein the step of applying palladium to the wall of the drilled through hole specifically comprises:
and plating palladium on the wall of the drilled through hole by adopting chemical palladium plating.
6. The method for processing a circuit board according to claim 1, wherein said step of degreasing said first solder resist ink stick and said second solder resist ink stick to make said through hole wall free of palladium at said first solder resist ink stick and said second solder resist ink stick comprises:
and dissolving the first solder resist ink block and the second solder resist ink block by using alkaline solution, so that the hole wall of the through hole is palladium-free at the positions of the first solder resist ink block and the second solder resist ink block.
7. The method for processing a circuit board according to claim 1, wherein the step of copper coating the through hole wall subjected to the palladium coating treatment, the through hole wall not coated with copper at the palladium-free place, specifically comprises the steps of:
and carrying out electroless copper deposition on the hole wall of the through hole subjected to palladium deposition treatment, wherein copper is not deposited on the hole wall of the through hole at the position without palladium, and electroplating the hole wall of the through hole subjected to electroless copper deposition treatment.
8. The method for processing a circuit board according to claim 1, further comprising:
etching the hole wall of the through hole after copper coating treatment to remove copper between the first solder resist ink block and the second solder resist ink block on the hole wall of the through hole.
9. The method for processing a circuit board according to claim 8, wherein the step of etching the via wall after the copper-clad treatment to remove copper between the first solder resist ink stick and the second solder resist ink stick on the via wall specifically comprises:
and carrying out chemical etching treatment on the hole wall of the through hole after copper coating treatment, and removing copper between the first solder resist ink block and the second solder resist ink block on the hole wall of the through hole.
10. A wiring board, characterized in that the wiring board is processed by the wiring board processing method according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210255937.8A CN116801479A (en) | 2022-03-15 | 2022-03-15 | Circuit board and processing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210255937.8A CN116801479A (en) | 2022-03-15 | 2022-03-15 | Circuit board and processing method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN116801479A true CN116801479A (en) | 2023-09-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210255937.8A Pending CN116801479A (en) | 2022-03-15 | 2022-03-15 | Circuit board and processing method thereof |
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| Country | Link |
|---|---|
| CN (1) | CN116801479A (en) |
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2022
- 2022-03-15 CN CN202210255937.8A patent/CN116801479A/en active Pending
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