CN116798375A - Scan driving circuit and display panel - Google Patents
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Abstract
The embodiment of the application discloses a scanning driving circuit and a display panel. The scan driving unit includes a first output module and a second output module, the first output module outputs a scan signal when the scan driving circuit executes a first scan frequency, the second output module outputs a scan signal when the scan driving circuit executes a second scan frequency, and the first output module and the second output module output the scan signal simultaneously when the scan driving circuit executes a third scan frequency. By setting the first output module and the second output module to output the scanning signals singly or in combination according to different scanning frequencies, the stability of the scanning driving unit for outputting the scanning signals is improved.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a scan driving circuit and a display panel.
Background
The Gate Driver Less technology (GDL) is to use the original array process of the liquid crystal display panel to manufacture the driving circuit of the horizontal scanning line on the substrate around the display area, so as to replace the external integrated circuit board (Integrated Circuit, IC) to complete the driving of the horizontal scanning line. The GDL technology can reduce the welding procedure of an external IC, and can make the liquid crystal display panel more suitable for manufacturing display products with narrow frames or without frames.
At present, the refresh frequency requirement of the display panel is higher and higher, the energy saving effect of low-frequency refresh is required to be met, the visual experience of high-frequency refresh is also required to be met, the switching tube for controlling the output of the scanning signal in the scanning driving circuit needs high output capacity to meet the high-frequency refresh due to the fact that the refresh frequency span of the display panel is overlarge, the output capacity is usually improved by increasing the channel width of the switching tube, but when the display panel is refreshed at low frequency, the output capacity and the output stability of the scanning signal are poor, and further the display effect is poor, so that the problem of effectively improving the output stability of the scanning signal under the condition of compatibility of low-frequency refresh and high-frequency refresh is needed to be solved.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present application provides a scan driving circuit and a display panel capable of effectively improving the stability of outputting scan signals.
The application provides a scanning driving circuit, which comprises n cascaded scanning driving units, wherein n is an integer larger than 1, n scanning driving units are used for sequentially outputting corresponding scanning signals, the scanning signals are used for controlling a pixel unit to receive data signals for image display to display images, the scanning driving unit comprises a first output module and a second output module, when the scanning driving circuit executes a first scanning frequency, the first output module outputs the scanning signals, when the scanning driving circuit executes a second scanning frequency, the second output module outputs the scanning signals, when the scanning driving circuit executes a third scanning frequency, the first output module and the second output module simultaneously output the scanning signals, and the first scanning frequency is smaller than the second scanning frequency and the second scanning frequency is smaller than the third scanning frequency.
Optionally, the scan driving circuit further includes a pull-up module and a first node, where the pull-up module, the first output module and the second output module are connected to the first node; the pull-up module is used for pulling up the potential of the first node to a preset potential, and when the first node is positioned at the preset potential, the first output module and/or the second output module control the output of the scanning signal.
Optionally, the first output module is further connected to a clock signal end, a first control end and a scanning signal output end, and when the potential of the first node is at the preset potential, the first output module receives a clock signal from the clock signal end and outputs the scanning signal from the scanning signal output end according to a first control signal output by the first control end; the second output module is further connected to the clock signal end, the second control end and the scanning signal output end, and when the potential of the first node is at the preset potential, the second output module receives the clock signal from the clock signal end and outputs the scanning signal from the scanning signal output end according to a second control signal output by the second control end.
Optionally, when the scan driving circuit executes the first scan frequency, the first control end outputs the first control signal, and the first output module outputs the scan signal according to the first control signal; when the scanning driving circuit executes the second scanning frequency, the second control end outputs the second control signal, and the second output module outputs the scanning signal according to the second control signal; when the scanning driving circuit executes the third scanning frequency, the first control end outputs the first control signal, the second control end outputs the second control signal, and the first output module and the second output module output the scanning signal at the same time.
Optionally, the scan driving circuit further includes a voltage stabilizing module and a pull-down module, where the voltage stabilizing module is connected to the first node and the first output module and/or the second output module, and is configured to maintain voltage stability when the first output module and/or the second output module outputs the scan signal; the pull-down module is connected to the first node and the scanning signal output end and is used for pulling down the electric potentials of the first node and the scanning signal output end to a first electric potential.
Optionally, the pull-up module includes a first switching tube, the first output module includes a second switching tube and a third switching tube, a gate and a source of the first switching tube are connected to a start signal end, a drain of the first switching tube is connected to the first node, and is used for receiving a start signal according to the start signal end and pulling up the potential of the first node to the preset potential; the grid electrode of the second switching tube is connected with the first node, the source electrode of the second switching tube is connected with the clock signal end, the drain electrode of the second switching tube is connected with the source electrode of the third switching tube, and the second switching tube is used for being conducted when the first node is located at the preset potential so as to receive the clock signal from the clock signal end; the grid electrode of the third switching tube is connected to the first control end, the drain electrode of the third switching tube is connected to the scanning signal output end and is used for being conducted when the first control signal is received, and the received clock signal is output through the scanning signal output end.
Optionally, the second output module includes a fourth switching tube and a fifth switching tube, where a gate of the fourth switching tube is connected to the first node, a source of the fourth switching tube is connected to the clock signal end, and a drain of the fourth switching tube is connected to a source of the fifth switching tube, and is configured to be turned on when the first node is at the preset potential, so as to receive the clock signal from the clock signal end; the grid electrode of the fifth switching tube is connected to the second control end, the drain electrode of the fifth switching tube is connected to the scanning signal output end and is used for being conducted when the second control signal is received, and the received clock signal is output through the scanning signal output end.
Optionally, the second switching tube and the fourth switching tube are transistors, the second switching tube and the fourth switching tube are manufactured by adopting a same process, the channel width of the second switching tube is a first width, the channel width of the fourth switching tube is a second width, and the second width is 1.5 times of the first width.
Optionally, the pull-down module includes a sixth switching tube and a seventh switching tube, where a gate of the sixth switching tube is connected to a reset end, a source of the sixth switching tube is connected to the first node, and a drain of the sixth switching tube is connected to a low voltage end, and is used for being turned on when receiving a reset signal from the reset end so as to pull down the potential of the first node to the first potential;
the grid electrode of the seventh switching tube is connected to the reset end, the source electrode of the seventh switching tube is connected to the scanning signal output end, the drain electrode of the seventh switching tube is connected to the low-voltage end, and the drain electrode of the seventh switching tube is used for being conducted when the reset signal is received from the reset end so as to control the scanning signal output end to stop outputting the scanning signal.
The application also provides a display panel which comprises a plurality of pixel units arranged in a display area and arranged in a matrix, a data driving circuit arranged in a non-display area, a time sequence control circuit and the scanning driving circuit, wherein the scanning driving circuit is used for jointly driving the pixel units to display images according to a grid output control signal output by the time sequence control circuit and a source output control signal output by the time sequence control circuit in cooperation with the data driving circuit.
Compared with the prior art, the application sets the first output module and the second output module to output the scanning signals singly or in combination according to different scanning frequencies, so that the load of the first output module and the second output module in the scanning driving unit is effectively reduced, the problems of overload and overheating of the output modules are avoided when the image display with high refresh rate is performed, and the stability of the scanning signals output by the scanning driving unit is improved when the image display with low refresh rate is performed, thereby improving the overall display effect of the display panel.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a display device according to a first embodiment of the present application;
FIG. 2 is a schematic side view of the display panel of FIG. 1;
FIG. 3 is a schematic plan layout of the display panel of FIG. 2;
FIG. 4 is a schematic diagram of the scan driving circuit shown in FIG. 3;
FIG. 5 is an equivalent circuit schematic diagram of the scan driving unit in FIG. 4;
FIG. 6 is a diagram showing the output timing of the scan signal in FIG. 5.
Reference numerals illustrate: the display device comprises a display device 100, a display panel 10, a power module 20, a support frame 30, a display area 10a, a non-display area 10b, a time sequence control circuit 11, a data driving circuit 12, a scanning driving circuit 13, a pixel unit P, a backlight module 17, an array substrate 10c, a display medium layer 10e, a counter substrate 10d, a first direction F1, a second direction F2, m data lines S1-Sm, n scanning lines G1-Gn, a clock signal CLK, a start signal STV, a reset signal R, a scanning driving unit GDL, a pull-up module 130, a first output module 131, a second output module 132, a voltage stabilizing module 133, a pull-down module 134, a first node Q1, a scanning signal output end Gout, a first switching tube T1, a second switching tube T2, a third switching tube T3, a first switching tube T4, a fifth switching tube T5, a sixth switching tube T6, a seventh switching tube T6, a first switching tube CN 1-CN, a second switching tube CN2, a third switching tube CN 1-CN, a third period of time period 2-CN.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. The drawings illustrate preferred embodiments of the application. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the application may be practiced. The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The term "coupled" as used herein includes both direct and indirect coupling (coupling), unless otherwise indicated. Directional terms, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side", etc., in the present application are merely referring to the directions of the attached drawings, and thus, directional terms are used for better, more clear explanation and understanding of the present application, rather than indicating or implying that the apparatus or element being referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; may be a mechanical connection; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art. It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and in the drawings are used for distinguishing between different objects and not for describing a particular sequential order.
Furthermore, the terms "comprises," "comprising," "includes," "including," or "having," when used in this specification, are intended to specify the presence of stated features, operations, elements, etc., but do not limit the presence of one or more other features, operations, elements, etc., but are not limited to other features, operations, elements, etc. Furthermore, the terms "comprises" or "comprising" mean that there is a corresponding feature, number, step, operation, element, component, or combination thereof disclosed in the specification, and that there is no intention to exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof. Furthermore, when describing embodiments of the application, use of "may" means "one or more embodiments of the application. Also, the term "exemplary" is intended to refer to an example or illustration.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a display device according to a first embodiment of the present application. The display device 100 includes a display panel 10, a power module 20 and a supporting frame 30, wherein the display panel 10 and the power module 20 are fixed on the supporting frame 30, and the power module 20 is disposed on a back surface of the display panel 10, i.e. a non-display surface of the display panel 10. The power module 20 is used for providing power voltage for the display panel 10 to display images, and the support frame 30 provides fixing and protecting functions for the display panel 10 and the power module 20.
In other embodiments of the present application, the display device 100 may not need to be provided with the supporting frame 30, for example, a portable electronic device, such as a mobile phone, a tablet computer, etc.
Referring to fig. 2, fig. 2 is a schematic side view of the display panel in fig. 1.
The display panel 10 includes an array substrate 10c, an opposite substrate 10d, and a display medium layer 10e sandwiched between the array substrate 10c and the opposite substrate 10 d. The driving elements disposed on the array substrate 10c and the opposite substrate 10d generate corresponding electric fields according to the Data signals (Data), so as to drive the display medium in the display medium layer 10e to emit light with corresponding brightness, so as to execute image display. Wherein the display medium may be liquid crystal molecules, miniLED, micro-LED, OLED, etc., which the present application is not limited to.
Taking the liquid crystal display panel as an example, the display medium in the display medium layer 10e is liquid crystal molecules, and the display panel 10 further includes a backlight module 17 (Back light Module, BM), wherein the backlight module 17 is configured to provide light for display to the display medium layer 10e, and the liquid crystal molecules deflect by an opposite angle according to the data signal, so as to emit the light transmitted by the backlight module 17 to the opposite substrate to perform image display.
Referring to fig. 3, fig. 3 is a schematic plan layout structure of the display panel in fig. 2.
As shown in fig. 3, the display panel 10 further includes a timing control circuit 11, a data driving circuit 12, and a scan driving circuit 13. The timing control circuit 11, the data driving circuit 12, and the scan driving circuit 13 are provided in the non-display region 10b of the display panel 10.
M data lines (Source lines) S1 to Sm and n scanning lines (Gate lines) G1 to Gn are provided in a grid-like arrangement in the display region 10a of the display panel 10. Wherein, m data lines S1-Sm extend along a first direction F1, and n scanning lines G1-Gn extend along a second direction F2. Wherein the first direction F1 and the second direction F2 are perpendicular to each other. The pixel units P are provided at intersections of the n scanning lines G1-Gn and the data lines S1-Sm.
The timing control circuit 11 receives an image signal representing image information, a clock signal CLK for synchronization, a horizontal synchronization signal Hsyn, and a vertical synchronization signal Vsyn from an external signal source, and outputs a gate output control signal Cg for controlling the scan driving circuit 13, a source output control signal Cs for controlling the data driving circuit 12, and a data signal representing image information. In this embodiment, the timing control circuit 11 performs data adjustment processing on the original data signal to obtain a data signal, and transmits the data signal to the data driving circuit 12.
The m data lines S1 to Sm are connected to the data driving circuit 11 for receiving the data signals stored and transmitted in the form of gray scale values supplied from the data driving circuit 12, and the n scan lines G1 to Gn are connected to the scan driving circuit 13 for receiving the scan signals from the scan driving circuit 13.
The pixel unit P receives data voltages corresponding to gray scale values in the data signals provided by the data lines S1 to Sm in a predetermined period under the control of the n scan lines G1 to Gn, and drives the display medium layer 10e to deflect by a corresponding angle accordingly, so that the received backlight emits light rays with corresponding brightness according to the deflected corresponding angle, and image display is performed by emitting the light rays with corresponding brightness according to the image signals.
The scan driving circuit 13 receives the gate output control signal Cg output from the timing control circuit 11, and outputs scan signals to the respective scan lines G1 to Gn. The data driving circuit 12 receives the source output control signal Cs output from the timing control circuit 11, and outputs data signals for performing image display to the driving elements in the respective pixel units P in the display area 10a to the respective data lines S1 to Sm. Wherein the data signal provided to the display panel 10 is a gray scale voltage in analog form. The scan driving circuit 13 outputs a scan signal to control the pixel unit P to receive the data signal output from the data driving circuit 12, so as to control the pixel unit P to display a corresponding image.
Referring to fig. 4, fig. 4 is a schematic circuit diagram of the scan driving circuit in fig. 3.
As shown in fig. 4, the scan driving circuit 13 includes n cascaded scan driving units GDL1 to GDLn, eight clock signals CLK1 to CLK8, a start signal STV, a reset signal R, and a low voltage terminal Vss, where n is an integer greater than or equal to 1.
In the exemplary embodiment, the clock signal may also be set to other numbers according to specific needs, and the present application is not limited.
In the scan driving circuit 13, each GDL unit correspondingly outputs a scan signal to one scan line in the display area 10a, and n GDL units sequentially output n scan signals G (1) to G (n) during one frame of image display.
Eight clock signals CLK1-CLK8 are used to provide scan drive timing for the GDL unit output scan signals. The start signal STV is an initial start signal of the first scan driving unit GDL1, and the other scan driving units use the stage signal output by the cascade scan unit as a start signal. The low voltage terminal Vss is used to supply a low voltage to the node in the scan driving unit.
Referring to fig. 5, fig. 5 is an equivalent circuit schematic diagram of the scan driving unit in fig. 4.
As shown in fig. 5, the scan driving unit GDL includes a pull-up module 130, a first output module 131, a second output module 132, and a first node Q1, wherein the pull-up module 130 is connected to the first node Q1 for charging the first node Q1 to pull up the potential of the first node Q1. The first output module 131 and the second output module 132 are connected to the first node Q1 and the scan signal output terminal Gout, and when the potential of the first node Q1 rises to a preset potential, the first output module 131 and/or the second output module 132 outputs a scan signal from the scan signal output terminal Gout.
The first output module 131 is further connected to the clock signal terminal CK and the first control terminal CN1, and when the potential of the first node Q1 is at the preset potential, the first output module 131 receives the clock signal from the clock signal terminal CK and outputs the scan signal through the scan signal output terminal Gout according to the first control signal output by the first control terminal CN 1.
The second output module 132 is further connected to the clock signal terminal CK and the second control terminal CN2, and when the potential of the first node Q1 is at the preset potential, the second output module 132 receives the clock signal from the clock signal terminal CK and outputs the scan signal through the scan signal output terminal Gout according to the second control signal output by the second control terminal CN 2.
When the scan driving circuit 13 performs the image display at the first frequency, the first output module 131 receives the first control signal from the first control terminal CN1 and outputs the scan signal through the scan signal output terminal Gout, when the scan driving circuit 13 performs the image display at the second frequency, the second output module 132 receives the second control signal from the second control terminal CN2 and outputs the scan signal through the scan signal output terminal Gout, and when the scan driving circuit 13 performs the image display at the third frequency, the first output module 131 and the second output module 132 respectively receive the first control signal and the second control signal and simultaneously output the scan signal through the scan signal output terminal Gout. Wherein the first frequency, the second frequency and the third frequency are sequentially increased. The frequency is the refresh rate of the display panel, i.e. the number of frames in which the display panel displays images per unit time.
In the exemplary embodiment, a plurality of other output modules than the first output module 131 and the second output module 132 may be provided and turned on simultaneously or not simultaneously by the plurality of output modules to realize that the scan driving circuit 13 performs different scan frequencies. For example, the scan driving unit GDL further includes a third output module (not shown), and when the scan driving circuit 13 performs scanning at a third frequency, the first output module and the third output module may be controlled to simultaneously output the scan signal from the scan signal output terminal Gout, and when the scan driving circuit 13 performs scanning at a fourth frequency, the second output module and the third output module may be controlled to simultaneously output the scan signal from the scan signal output terminal Gout, and when the scan driving circuit 13 performs scanning at a fifth frequency, the first output module, the second output module and the third output module may be controlled to simultaneously output the scan signal from the scan signal output terminal Gout.
The scanning driving unit GDL has the advantages that different output modules are arranged for outputting scanning signals singly or in combination according to different scanning frequencies, so that the load of the output modules in the scanning driving unit GDL is effectively reduced, the problems of overload and overheating of the output modules are avoided when the image with high refresh rate is displayed, the stability of the scanning signals output by the scanning driving unit GDL is improved when the image with high refresh rate is refreshed at low frequency, and the overall display effect of the display panel is improved.
The scan driving unit GDL further includes a voltage stabilizing module 133 and a pull-down module 134, where the voltage stabilizing module 133 is connected to the first node Q1 and the second output module 132, and is configured to maintain the voltage of the second output module 132 stable when the second output module 132 outputs the scan signal. The pull-down module 134 is connected to the first node Q1, the scan signal output terminal Gout and the low voltage terminal Vss, and is configured to pull down the potential of the first node Q1 and the potential of the scan signal output terminal to a low potential.
Specifically, the pull-up module 130 includes a first switching tube T1, where a gate and a source of the first switching tube T1 are connected to the start signal terminal STV, and a drain of the first switching tube T1 is connected to the first node Q1, for pulling up the potential of the first node Q1 to a preset potential under the control of the start signal.
The first output module 131 includes a second switching tube T2 and a third switching tube T3, where a gate of the second switching tube T2 is connected to the first node Q1, a source is connected to the clock signal terminal CK, a drain is connected to a source of the third switching tube T3, a gate of the third switching tube T3 is connected to the first control terminal CN1, and a drain of the third switching tube T3 is connected to the scan signal output terminal Gout. When the potential of the first node Q1 is a preset potential, the second switching tube T2 receives a clock signal from the clock signal terminal CK and transmits the clock signal to the third switching tube T3, and the third switching tube T3 outputs the received clock signal as a scan signal from the scan signal output terminal Gout under the control of the first control signal.
The second output module 132 includes a fourth switching tube T4 and a fifth switching tube T5, where a gate of the fourth switching tube T4 is connected to the first node Q1, a source is connected to the clock signal terminal CK, a drain is connected to a source of the fifth switching tube T5, a gate of the fifth switching tube T5 is connected to the second control terminal CN2, and a drain of the fifth switching tube T5 is connected to the scan signal output terminal Gout. When the potential of the first node Q1 is a preset potential, the fourth switching tube T4 receives a clock signal from the clock signal terminal CK and transmits the clock signal to the fifth switching tube T5, and the fifth switching tube T5 outputs the received clock signal as a scan signal from the scan signal output terminal Gout under the control of the second control signal.
The second switching tube T2 and the fourth switching tube T4 are N-type MOS tubes, the channel width of the second switching tube T2 is a first width, the channel width of the fourth switching tube T4 is a second width, the first width is smaller than the second width, the channel width of the second switching tube T2 is suitable for the scan driving unit GDL to output the scan signal at the first frequency, the channel width of the fourth switching tube T4 is suitable for the scan driving circuit GDL to output the scan signal at the second frequency, and when the second switching tube T2 and the fourth switching tube T4 are turned on simultaneously, the scan driving circuit GDL can output the scan signal at the third frequency.
In an exemplary embodiment, the channel width of the fourth switching tube T4 may be set to be 1.5 times the channel width of the second switching tube T2, that is, the second width may be set to be 1.5 times the first width, which is of course not limited according to specific needs.
For example, when the refresh rate of the display panel 10 is 60Hz, 120Hz, and 240Hz, respectively, that is, the first frequency is 60Hz, the second frequency is 120Hz, the third frequency is 240Hz, and since the refresh rate is the first frequency, that is, 60Hz, the first output module 131 controls the output of the scan signal, and at this time, the channel width of the second switching tube T2 in the first output module 131 may be set to 8000nm, and at the second frequency, that is, 120Hz, the second output module 132 controls the output of the scan signal, and at this time, the channel width of the fourth switching tube in the second output module may be set to 12000nm.
Because the driving capability required by the second switching tube T2 and the fourth switching tube T4 are similar, the difference in manufacturing is small, so that the same manufacturing process can be adopted for the second switching tube T2 and the fourth switching tube T4, and the same photomask is used for manufacturing, thereby saving the cost. When the refresh rate is 240Hz, only the first output module 131 and the second output module 132 are required to control the scan signal output at the same time, and no corresponding output module is required to be set according to the high refresh rate, thereby further saving the cost. Of course, the first frequency, the second frequency and the third frequency can also be set to other values according to the needs, and the channel widths of the corresponding second switching tube T2 and fourth switching tube T4 are also set to corresponding widths.
The voltage stabilizing module 133 includes a voltage stabilizing capacitor C, where the voltage stabilizing capacitor C is connected to the first node Q1 and the drain of the fourth switching tube, and is used for maintaining the voltage stability of the fourth switching tube T4 when the fourth switching tube T4 transmits the clock signal, and of course, the voltage stabilizing capacitor C may also be connected to the drain of the second switching tube T2, and is used for maintaining the voltage stability of the second switching tube T2 when the second switching tube T2 transmits the clock signal, or the voltage stabilizing capacitor C is simultaneously connected to the drain of the second switching tube T2 and the drain of the fourth switching tube T4.
The pull-down module 134 includes a sixth switching tube T6 and a seventh switching tube T7, where a gate of the sixth switching tube T6 is connected to the reset terminal R, a source is connected to the first node Q1, a drain is connected to the low voltage terminal Vss, and when the sixth switching tube T6 receives the reset signal from the reset terminal R, the pull-down module is turned on to turn on the first node Q1 and the low voltage terminal Vss, and is used for pulling down the potential of the first node Q1 to the first potential. The seventh switching tube T7 has a gate connected to the reset terminal R, a source connected to the scan signal output terminal Gout, and a drain connected to the low voltage terminal Vss, and is used for being turned on when receiving the reset signal from the reset terminal R, so as to turn on the scan signal output terminal Gout and the low voltage terminal Vss, and for pulling down the potential of the scan signal output terminal Gout, that is, stopping the scan signal output terminal Gout from outputting the scan signal.
Referring to fig. 6, fig. 6 is a timing chart of the scan signal output in fig. 5.
As shown in fig. 6, in the first period t1, the start signal STV is input for precharging the first node Q1, and the potential of the first node Q1 rises from the first potential V1 to the second potential V2. In the second period T2, the potential of the first node Q1 rises from the second potential V2 to the third potential V3 and is maintained at the third potential V3, and at this time, the second switching transistor T2 and/or the fourth switching transistor T4 are turned on to receive the clock signal from the clock signal terminal CK and output the scan signal from the scan signal output terminal Gout. In the third period T3, the reset terminal R outputs a reset signal, the sixth switching tube T6 and the seventh switching tube T7 are turned on, the potential of the first node Q1 drops from the third potential V3 to the first potential V1, and the second switching tube T2 and the fourth switching tube T4 stop receiving the clock signal.
If the first frequency is 60Hz, the second frequency is 120Hz, the third frequency is 240Hz, the time for scanning one row of pixel units by the scanning signal outputted by the scanning driving unit GDL is 1H when the refresh rate of the display panel 10 is 60Hz, and the time for scanning one row of pixel units by the scanning signal is 0.5H when the refresh rate of the display panel 10 is 120Hz, and the time for scanning one row of pixel units by the scanning signal is 0.25H when the refresh rate of the display panel 10 is 240Hz, which is the first frequency.
It is to be understood that the application is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.
Claims (10)
1. The scanning driving circuit comprises n cascaded scanning driving units, wherein n is an integer greater than 1, and n scanning driving units are used for sequentially outputting corresponding scanning signals which are used for controlling pixel units to receive data signals for image display so as to display images;
the scanning driving unit is characterized by comprising a first output module and a second output module, wherein the first output module outputs the scanning signal when the scanning driving circuit executes a first scanning frequency, the second output module outputs the scanning signal when the scanning driving circuit executes a second scanning frequency, and the first output module and the second output module simultaneously output the scanning signal when the scanning driving circuit executes a third scanning frequency, the first scanning frequency is smaller than the second scanning frequency, and the second scanning frequency is smaller than the third scanning frequency.
2. The scan drive circuit of claim 1, further comprising a pull-up module and a first node, the pull-up module, the first output module, and the second output module being connected to the first node;
the pull-up module is used for pulling up the potential of the first node to a preset potential, and when the first node is positioned at the preset potential, the first output module and/or the second output module control the output of the scanning signal.
3. The scan driving circuit according to claim 2, wherein,
the first output module is further connected to a clock signal end, a first control end and a scanning signal output end, and when the potential of the first node is at the preset potential, the first output module receives a clock signal from the clock signal end and outputs the scanning signal through the scanning signal output end according to a first control signal output by the first control end;
the second output module is further connected to the clock signal end, the second control end and the scanning signal output end, and when the potential of the first node is at the preset potential, the second output module receives the clock signal from the clock signal end and outputs the scanning signal through the scanning signal output end according to a second control signal output by the second control end.
4. The scan driving circuit according to claim 3, wherein,
when the scanning driving circuit executes the first scanning frequency, the first control end outputs the first control signal, and the first output module outputs the scanning signal according to the first control signal;
when the scanning driving circuit executes the second scanning frequency, the second control end outputs the second control signal, and the second output module outputs the scanning signal according to the second control signal;
when the scanning driving circuit executes the third scanning frequency, the first control end outputs the first control signal, the second control end outputs the second control signal, and the first output module and the second output module output the scanning signal at the same time.
5. The scan driving circuit according to claim 4, further comprising a voltage stabilizing module and a pull-down module, wherein the voltage stabilizing module is connected to the first node and the first output module and/or the second output module, and is configured to maintain voltage stability when the first output module and/or the second output module outputs the scan signal;
the pull-down module is connected to the first node and the scanning signal output end and is used for pulling down the electric potentials of the first node and the scanning signal output end to a first electric potential.
6. The scan driving circuit according to claim 5, wherein the pull-up module comprises a first switching tube, the first output module comprises a second switching tube and a third switching tube, a gate and a source of the first switching tube are connected to a start signal terminal, a drain of the first switching tube is connected to the first node, and the first switching tube is used for receiving a start signal according to the start signal terminal and pulling up a potential of the first node to the preset potential;
the grid electrode of the second switching tube is connected with the first node, the source electrode of the second switching tube is connected with the clock signal end, the drain electrode of the second switching tube is connected with the source electrode of the third switching tube, and the second switching tube is used for being conducted when the first node is located at the preset potential so as to receive the clock signal from the clock signal end;
the grid electrode of the third switching tube is connected to the first control end, the drain electrode of the third switching tube is connected to the scanning signal output end and is used for being conducted when the first control signal is received, and the received clock signal is output through the scanning signal output end.
7. The scan driving circuit according to claim 6, wherein,
the second output module comprises a fourth switching tube and a fifth switching tube, wherein the grid electrode of the fourth switching tube is connected with the first node, the source electrode of the fourth switching tube is connected with the clock signal end, the drain electrode of the fourth switching tube is connected with the source electrode of the fifth switching tube and is used for being conducted when the first node is located at the preset potential so as to receive the clock signal from the clock signal end;
the grid electrode of the fifth switching tube is connected to the second control end, the drain electrode of the fifth switching tube is connected to the scanning signal output end and is used for being conducted when the second control signal is received, and the received clock signal is output through the scanning signal output end.
8. The scan driving circuit according to claim 7, wherein the second switching transistor and the fourth switching transistor are transistors, the second switching transistor and the fourth switching transistor are manufactured by the same process, a channel width of the second switching transistor is a first width, a channel width of the fourth switching transistor is a second width, and the second width is 1.5 times the first width.
9. The scan driving circuit according to claim 8, wherein the pull-down module comprises a sixth switching tube and a seventh switching tube, a gate of the sixth switching tube is connected to a reset terminal, a source of the sixth switching tube is connected to the first node, and a drain of the sixth switching tube is connected to a low voltage terminal, and is configured to be turned on when a reset signal is received from the reset terminal, so as to pull down a potential of the first node to the first potential;
the grid electrode of the seventh switching tube is connected to the reset end, the source electrode of the seventh switching tube is connected to the scanning signal output end, the drain electrode of the seventh switching tube is connected to the low-voltage end, and the drain electrode of the seventh switching tube is used for being conducted when the reset signal is received from the reset end so as to control the scanning signal output end to stop outputting the scanning signal.
10. A display panel, comprising a plurality of pixel units arranged in a matrix in a display area, a data driving circuit arranged in a non-display area, a time sequence control circuit and a scanning driving circuit as claimed in any one of claims 1 to 9, wherein the scanning driving circuit is used for driving the pixel units together according to a grid output control signal output by the time sequence control circuit and a source output control signal output by the time sequence control circuit by matching with the data driving circuit.
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| CN202310801840.7A CN116798375A (en) | 2023-06-30 | 2023-06-30 | Scan driving circuit and display panel |
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| CN202310801840.7A CN116798375A (en) | 2023-06-30 | 2023-06-30 | Scan driving circuit and display panel |
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