CN116794962A - Large dynamic measurement range high-resolution multipurpose time-to-digital converter circuit - Google Patents

Large dynamic measurement range high-resolution multipurpose time-to-digital converter circuit Download PDF

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CN116794962A
CN116794962A CN202210920968.0A CN202210920968A CN116794962A CN 116794962 A CN116794962 A CN 116794962A CN 202210920968 A CN202210920968 A CN 202210920968A CN 116794962 A CN116794962 A CN 116794962A
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output
module
digital converter
input end
interpolator
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刘晨
刘明明
赵宏宇
王化方
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Xi'an Zhongling Xingxun Electronic Technology Co ltd
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Xi'an Zhongling Xingxun Electronic Technology Co ltd
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/005—Time-to-digital converters [TDC]

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Abstract

The invention discloses a high-resolution multipurpose time-to-digital converter circuit with a large dynamic measurement range, which comprises a control signal generation module, a first frequency synthesizer FS1, a fine time-to-digital converter module, a coarse time-to-digital converter module, a reference clock counter module and a data processing and calibrating module. The high Duan Chazhi device in the reference clock counter module is used for expanding the maximum measurement dynamic range, and the quantization unit of the high Duan Chazhi device is one reference clock period; the middle-section interpolator in the coarse time digital converter module coarsely quantizes the time which is less than one reference clock period and is longer than the basic time delay unit in the middle-section interpolator; the low-stage interpolator in the fine time digital converter module refines the time of the basic delay unit duration in less than one middle-stage interpolator so as to realize high measurement resolution.

Description

Large dynamic measurement range high-resolution multipurpose time-to-digital converter circuit
Technical Field
The invention relates to the field of digital-analog hybrid integrated circuits, in particular to a high-resolution multipurpose time-to-digital converter circuit with a large dynamic measurement range.
Background
Optical signals play an important role where distance measurement by physical contact and conventional methods is not possible. Time-of-flight based time measurement techniques are very important in the fields of high-energy physics, medical imaging, radio frequency signal phase difference detection, flow monitoring, etc., where time-to-digital converters (TDCs) are required. The high-precision time-to-digital converter is a high-precision time measuring instrument with resolution up to picosecond, has the advantages of high resolution, low power consumption, low delay and the like, and can be widely applied to the scenes.
Analog methods are mostly adopted in the traditional TDC, analog-to-digital conversion is needed, and an analog circuit often has larger power consumption and is sensitive to leakage current, the performance of the analog circuit is reduced along with the reduction of a power supply voltage, and the influence on the digital circuit is far smaller than that of the analog circuit. In the laser ranging application scene, the measurement accuracy is reduced due to the reflectivity of the object surface and the direction of the object, and the dynamic measurement range is also insufficient.
The structure of the existing three-section high-precision time-to-digital converter is shown in fig. 1, a Start signal Start is input to an initial phase adjusting circuit, and synchronization between the Start signal and the rising edge of an external input clock CLK can be realized; the linear feedback shift register can carry out counting type high-level quantification on the time to be measured through an external input clock according to the Stop signal Stop and the synchronous Start signal Start; the dual-loop delay phase-locked loop respectively provides delay unit time for middle-stage quantization by adopting a tap delay line method and differential delay unit time for low-stage quantization by adopting a differential delay method; the edge detection circuit can detect the Stop signal and input the Stop signal as the starting time of low-stage bit quantization to the annular vernier type time digital conversion unit, and the module performs low-stage quantization on the middle-stage quantization residual. And sending the three-section quantized data into a decoding unit for decoding, and then sequentially splicing the three-section quantized values in series through a data reading unit to output a time-digital conversion result. The architecture TDC generally requires a high frequency reference clock, and it is difficult to achieve a large measurement range.
Another existing three-segment high-precision time-to-digital converter structure is shown in fig. 2, and compared with the structure, the structure has the same high-segment quantization method, except that ring oscillation type TDC is adopted for the middle-segment quantization and the low-segment quantization, a two-bit binary synchronous counter inputs the middle-segment quantization value into a direct decoding latch circuit, and a serial data output circuit serially outputs the three-segment quantization values in sequence. The ring oscillation type TDC is adopted in the low-stage quantization of the structure, so that higher measurement resolution is difficult to realize.
Disclosure of Invention
Aiming at the defects of the prior art, the invention discloses a high-resolution multipurpose time-to-digital converter circuit with a large dynamic measurement range so as to solve the problems in the prior art.
To achieve the above object, the present invention includes: a control signal generating module 1, a first frequency synthesizer FS12, a fine time digital converter module 3, a coarse time digital converter module 4, a reference clock counter module 5 and a data processing and calibrating module 6;
the control signal generation module 1 is used for generating a control signal required by normal operation of a circuit, and is provided with two input ends and an output end, wherein the first input end is connected with a Start signal Start, and the second input end is connected with a Stop signal Stop; the output end outputs an enable signal en1 and is connected to the fine time digital converter module 3 and the coarse time digital converter module 4 at the same time;
the first frequency synthesizer FS12 has an input end connected to the external input reference clock Ref_clk and an output end for outputting the second control signal V ctr2 And is connected to the fine time digitizer module 3;
the fine time digital converter module 3 mainly performs low-level quantization of time digital conversion, and has four input terminals and one output terminal, wherein the first input terminal is connected with the enable signal en1 output by the control signal generating module 1, and the second input terminal is connected with the second control signal V output by the first frequency synthesizer FS12 ctr2 The third input end is connected with the first control signal V output by the coarse time digital converter module 4 ctr1 The fourth input end is connected with an enable signal en2 output by the coarse time digital converter module 4; the output end outputs a low-level quantization result D1 and is connected to the data processing calibration module 6;
the coarse time digitizer module 4 is mainly completedThe middle bit quantization of the inter-digital conversion is provided with three input ends and three output ends, wherein the first input end is connected with an enable signal en1 output by the control signal generation module 1, the second input end is connected with an external input reference clock Ref_clk, and the third input end is connected with a disable signal disten 2 output by the reference clock counter module 5; the first output end outputs a first control signal V ctr1 The second output end outputs an enable signal en2 and is connected to the fine time digital converter module 3 and the reference clock counter module 5, and the third output end outputs a middle segment bit quantization result D2 and is connected to the data processing calibration module 6;
the reference clock counter module 5 has two input ends and two output ends, the first input end is connected with the enable signal en2 output by the coarse time digital converter module 4, and the second input end is connected with the external input reference clock Ref_clk; the first output end outputs a disable signal distn 2 and is connected to the coarse time digital converter module 4, and the second output end outputs a high-level bit quantization result D3 and is connected to the data processing calibration module 6;
the data processing and calibrating module 6 is mainly used for completing calibration and combination of final measurement results and outputting the final measurement results in the form of binary codes, and is provided with three input ends and an output end, wherein the first input end is connected with a low-stage bit quantization result D1 output by the fine time digital converter module 3, the second input end is connected with a middle-stage bit quantization result D2 output by the coarse time digital converter module 4, and the third input end is connected with a high-stage bit quantization result D3 of the reference clock counter module 5; the output end is used for outputting the binary code of the measurement result.
The fine time digitizer module 3 includes a low-level interpolator and a low-level data processor, wherein: the low-stage interpolator is provided with four input ends and an output end, and the first input end is connected with an enable signal en1 output by the control signal generating module 1; a second input terminal connected to the second control signal V output by the first frequency synthesizer FS12 ctr2 The method comprises the steps of carrying out a first treatment on the surface of the The third input end is connected with the first control signal V output by the coarse time digital converter module 4 ctr1 The method comprises the steps of carrying out a first treatment on the surface of the The fourth input end is connected with an enable signal en2 output by the coarse time digital converter module 4; output end outputOutputting the binary character string DM of M bits to a low-stage data processor; the low-stage data processor is mainly used for preprocessing an M-bit binary string DM output by the low-stage interpolator so as to realize conversion of the quantization time of the low-stage interpolator, and the low-stage data processor is provided with an input end and an output end, wherein the input end is connected with the M-bit binary string DM output by the low-stage interpolator, and the output end outputs a low-stage bit quantization result D1 and is connected to the data processing calibration module 6.
The low-stage interpolator is a two-dimensional vernier delay chain type TDC, which comprises a first delay chain, a second delay chain and a sampling D trigger array with M-dimension and M-dimension>1, a step of; the first delay chain consists of M voltage-controlled delay units 1, and the delay time length of each single delay unit is tau 1 ，τ 1 > 0, the delay time τ 1 And a first control signal V ctr1 The enable signal en1 is used to enable the first delay chain in direct proportion to the voltage value of (a); the second delay chain consists of M voltage-controlled delay units 2, and the delay time length of each single delay unit is tau 2 ，τ 2 > 0, the delay time τ 2 And a second control signal V ctr2 The enable signal en2 is used to enable the second delay chain in direct proportion to the voltage value of (a); due to the delay tau of the delay cells in the first delay chain 1 A delay tau greater than the delay elements in the second delay chain 2 Thus, the first delay chain is also called slow delay chain and the second delay chain is also called fast delay chain; the D trigger array of M is used for sampling the relative positions of signal transmission in the two delay chains, and the output of the D trigger array is a binary string with M2 bits and is transmitted to the low-stage data processor.
The aforementioned coarse time digitizer module 4 includes a middle stage interpolator, a first phase detector PD1 and a middle stage data processor, wherein: the middle-section interpolator is a ring oscillation type TDC based on a frequency synthesizer, and is provided with two input ends and three output ends, wherein the first input end is connected with an external input reference clock Ref_clk, and the second input end is connected with an enable signal en1 of the output device of the control signal generation module 1; the first output end outputs an output oscillation period pulse signal Clk representing the ring oscillator in the middle-section interpolator and is connected to the middle-section data processor,the second output end outputs N-bit binary character strings representing the output phase states of each delay unit on the annular oscillator in the middle-stage interpolator and is connected to the interrupt data processor and the first phase detector PD1, and the third output end outputs a first control signal V ctr1 And is connected to the fine time digitizer module 3; the first phase detector PD1 is provided with an input end and an output end, the input end of the first phase detector PD1 is connected with an N-bit binary string DN which is output by the middle-stage interpolator and represents phase transmission information on the ring oscillator in the middle-stage interpolator, and the N-bit binary string DN is used for detecting output level jumps of taps of the ring oscillator in the middle-stage interpolator; the output end of the digital clock counter module outputs an enable signal en2 and is connected to the fine time digital converter module 3, the reference clock counter module 5 and the middle section data processor; the middle section data processor is mainly used for correspondingly processing the quantized result of the middle section interpolator-the ring oscillator so as to realize conversion of the quantized time of the middle section interpolator, and is provided with four input ends and an output end, wherein the first input end is connected with a periodic signal Clk representing an integer part of the output oscillation period of the ring oscillator of the middle section interpolator, the second input end is connected with a signal DN representing phase transmission information on the ring oscillator of the middle section interpolator, namely, a period fraction part less than one oscillation period, the third input end is connected with an enable signal en2, and the fourth input end is connected with a disable signal distn 2 output by the reference clock counter module 5; the output end outputs the middle segment bit quantization result D2 and is connected to the data processing calibration module 6.
The middle-section interpolator adopts a voltage-controlled ring oscillator structure based on a frequency synthesizer, and the output of the middle-section interpolator comprises two parts, wherein one part is a periodic signal representing that an integer number of oscillation periods are completed, and the other part is a fractional part of less than one oscillation period; the fractional part represents output phase information of each delay unit tap in the ring oscillator; the middle-section interpolator comprises a frequency controller, N voltage-controlled delay units and N D triggers; the N voltage-controlled delay units are connected end to form a ring oscillator, the Nth delay unit in the ring oscillator is used as the output end of the ring oscillator to output a periodic signal Clk representing the integer part of the oscillation period of the middle-section interpolator, and the frequency controller is combined with an external inputObtaining a frequency control signal V by inputting a reference clock Ref_clk and a ring oscillator output signal Clk ctrl To control the output of the ring oscillator to be in an integer multiple relationship with the reference clock ref_clk; the N D flip-flops latch the outputs of the N voltage-controlled delay units respectively, and the enable signal en1 is used for controlling the working time of the N D flip-flops.
The middle section data processor specifically comprises a middle section counter, a state decoder and a combined decoder functional module; when the enable signal en2 output by the first phase detector PD1 is at a high level, the counter starts to count the signal Clk representing the integer part of the oscillation period of the ring oscillator in the middle interpolator, and the state decoder decodes the tap phase states on the delay chain of the ring oscillator according to the input signal DN representing the phase transmission state information on the ring oscillator in the middle interpolator, so as to obtain a period fraction part of less than one oscillation period; the combined decoder performs the combined decoding again on the integer part remembered by the middle-stage counter and the fraction part decoded by the decoder to obtain a middle-stage quantization result D2.
The reference clock counter module 5 includes a high Duan Chazhi unit, an alternative control selector, and a second phase detector PD2, wherein: the high Duan Chazhi device consists of a reference clock counter with an enabling control end, and is provided with two input ends and an output end, wherein a first input end of the high Duan Chazhi device receives an external input reference clock Ref_clk as a clock control end of the counter; the second input end is connected with a control signal ctrl output by the alternative control selector, and the control signal can enable the reference clock counter to start counting and can lock the reference clock to stop counting; the output end outputs the high-level quantized result D3 and is connected and output to the data processing and calibrating module 6; the two-out-of-one control selector is provided with three input ends and one output end, wherein the first input end is connected with a high level, the second input end is connected with a low level, and the third input end is connected with a control signal Sel output by the second phase detector PD 2; the output end of the high-stage interpolator outputs a control signal ctrl to the high-stage interpolator, and the control signal ctrl is used for controlling the start or stop of a reference clock counter in the high-stage interpolator; the second phase detector PD2 is provided with two input ends and two output ends, the first input end is connected with the enable signal en2 output by the coarse time digital converter module 4, and the second input end is connected with an external input reference clock ref_clk, and is used for detecting the phase of ref_clk; the first output end outputs a control signal Sel and is connected to the alternative control selector, and the second output end outputs a disable signal disten 2 and is connected to the coarse time digital converter module 4 for ending the middle section quantization process.
Compared with the prior art, the invention has the following advantages:
1. different from the traditional three-section TDC, the frequency requirement on the external reference clock is not very high, and the required internal high-frequency clock can be flexibly realized through the internal frequency multiplier and used as the reference clock of the delay phase-locked loop. On the one hand, the cost is reduced, and on the other hand, the lower external reference clock can more easily expand the maximum measurement range.
2. Unlike traditional delay chain type TDC and clock counting type TDC, the TDC circuit in the invention comprises a low-stage interpolator unit, namely a two-dimensional delay chain type time-to-digital converter, which can break through the limitation of the minimum gate delay determined by the process on the TDC measurement resolution, thereby greatly improving the measurement resolution.
3. Unlike conventional successive approximation type TDCs and vernier delay chain type TDCs, the TDC circuit of the present invention includes a high Duan Chazhi device, so that the measurement time range, i.e., the dynamic measurement range, can be greatly expanded and high linearity is maintained.
4. The three-section type TDC has the function of continuously receiving and processing a plurality of stop signals, so that the working range and the application scene of the TDC are expanded.
5. According to the invention, a high Duan Chazhi device, a middle-section interpolator and a low-section interpolator can be simultaneously used according to the measurement requirement; according to the requirement, only the high Duan Chazhi device and the middle-section interpolator are selected to sacrifice the measurement resolution to obtain a larger measurement dynamic range, and meanwhile, the measurement dynamic power consumption is reduced; and the middle-stage interpolator and the low-stage interpolator can be selected according to the measurement requirement, so that the measurement dynamic range is sacrificed to obtain high measurement resolution, and the measurement conversion rate of the system is improved, thereby having high use flexibility.
Drawings
FIG. 1 is a block diagram of a conventional three-stage TDC circuit
FIG. 2 is a block diagram of another prior art three-stage TDC circuit
FIG. 3 is a functional block diagram of a TDC system according to the present invention
FIG. 4 is a block diagram of a TDC system according to the present invention
FIG. 5 is a timing diagram of the measurement principle of the TDC system of the present invention
FIG. 6 shows a middle stage interpolator based on ring oscillation type TDC in a TDC system according to the present invention
FIG. 7 shows a low-stage interpolator based on two-dimensional vernier delay chain type TDC in a TDC system according to the present invention
Detailed Description
The following describes the invention in more detail with reference to the drawings.
Referring to fig. 3, the present invention includes: a control signal generating module 1, a first frequency synthesizer FS12, a fine time digital converter module 3, a coarse time digital converter module 4, a reference clock counter module 5 and a data processing and calibrating module 6; wherein: the control signal generation module 1 is used for generating a control signal required by normal operation of a circuit, and is provided with two input ends and an output end, wherein the first input end is connected with a Start signal Start, and the second input end is connected with a Stop signal Stop; the output end outputs an enable signal en1 and is connected to the fine time digital converter module 3 and the coarse time digital converter module 4 at the same time; the first frequency synthesizer FS12 has an input end connected to the external input reference clock Ref_clk and an output end for outputting the second control signal V ctr2 And is connected to the fine time digitizer module 3; the fine time digital converter module 3 mainly performs low-level quantization of time digital conversion, and has four input terminals and one output terminal, the first input terminal is connected with the enable signal en1 output by the control signal generating module 1, and the second input terminal is connected with the second control signal V output by the first frequency synthesizer FS1 ctr2 The third input end is connected with the coarse time digital converter module 4Output first control signal V ctr1 The fourth input end is connected with an enable signal en2 output by the coarse time digital converter module 4; the output end outputs a low-level quantization result D1 and is connected to the data processing calibration module 6; the coarse time digital converter module 4 mainly completes middle bit quantization of time digital conversion, and has three input ends and three output ends, wherein the first input end is connected with an enable signal en1 output by the control signal generating module 1, the second input end is connected with an external input reference clock Ref_clk, and the third input end is connected with a disable signal distn 2 output by the reference clock counter module 5; the first output end outputs a first control signal V ctr1 The second output end outputs an enable signal en2 and is connected to the fine time digital converter module 3 and the reference clock counter module 5, and the third output end outputs a middle segment bit quantization result D2 and is connected to the data processing calibration module 6; the reference clock counter module 5 has two input ends and two output ends, the first input end is connected with the enable signal en2 output by the coarse time digital converter module 4, and the second input end is connected with the external input reference clock Ref_clk; the first output end outputs a disable signal distn 2 and is connected to the coarse time digital converter module 4, and the second output end outputs a high-level bit quantization result D3 and is connected to the data processing calibration module 6; the data processing and calibrating module 6 is mainly used for completing calibration and combination of final measurement results and outputting the final measurement results in the form of binary codes, and is provided with three input ends and an output end, wherein the first input end is connected with a low-stage bit quantization result D1 output by the fine time digital converter module 3, the second input end is connected with a middle-stage bit quantization result D2 output by the coarse time digital converter module 4, and the third input end is connected with a high-stage bit quantization result D3 of the reference clock counter module 5; the output end is used for outputting the binary code of the measurement result.
Referring to fig. 4, the fine time digitizer module 3 includes a low-stage interpolator and a low-stage data processor, wherein: the low-stage interpolator is provided with four input ends and an output end, and the first input end is connected with an enable signal en1 output by the control signal generating module 1; a second input terminal connected to the second control signal V output by the first frequency synthesizer FS12 ctr2 The method comprises the steps of carrying out a first treatment on the surface of the The third input end is connected with the first control signal V output by the coarse time digital converter module 4 ctr1 The method comprises the steps of carrying out a first treatment on the surface of the The fourth input end is connected with an enable signal en2 output by the coarse time digital converter module 4; the output end outputs a binary character string DM of M2 bits to the low-stage data processor; the low-stage data processor is mainly used for preprocessing the M2-bit binary string DM output by the low-stage interpolator so as to realize conversion of the quantization time of the low-stage interpolator, and the low-stage data processor is provided with an input end and an output end, wherein the input end is connected with the M2-bit binary string DM output by the low-stage interpolator, and the output end outputs a low-stage quantization result D1 and is connected to the data processing calibration module 6.
The coarse time digitizer module 4 comprises a mid-section interpolator, a first phase detector PD1 and a mid-section data processor, wherein: the middle-section interpolator is a voltage-controlled ring oscillation type TDC based on a frequency synthesizer, and is provided with two input ends and three output ends, wherein the first input end is connected with an external input reference clock Ref_clk, and the second input end is connected with an enable signal en1 output by the control signal generation module 1; the first output end outputs an oscillation period signal Clk representing the output of the ring oscillator in the middle-stage interpolator and is connected to the middle-stage data processor, the second output end outputs a signal DN representing a phase transmission state signal of less than one oscillation period on the ring oscillator in the middle-stage interpolator and is connected to the middle-stage data processor and the first phase detector PD1, and the third output end outputs a first control signal V ctr1 And is connected to the fine time digitizer module 3; the first phase detector PD1 is provided with an input end and an output end, and the input end is connected with the signal DN representing the phase transmission state on the ring oscillator output by the middle-stage interpolator, and is used for detecting the tap output level jump of the ring oscillator in the middle-stage interpolator; the output end of the digital clock counter module outputs an enable signal en2 and is connected to the fine time digital converter module 3, the reference clock counter module 5 and the middle section data processor; the middle section data processor is mainly used for correspondingly processing the quantized result of the middle section interpolator-ring oscillator to realize the conversion of the quantized time of the middle section interpolator, and is provided with four input ends and an output end, wherein the first input end is connected withThe second input end of the oscillation signal Clk representing the output of the middle-section interpolator is connected with a fractional part output signal DN representing less than one oscillation period of the ring oscillator in the middle-section interpolator, the third input end of the oscillation signal Clk is connected with an enable signal en2, and the fourth input end of the oscillation signal Clk is connected with a disable signal distn 2 output by the reference clock counter module 5; the output end outputs the middle segment bit quantization result D2 and is connected to the data processing calibration module 6.
The reference clock counter module 5 comprises a high Duan Chazhi selector, an alternative control selector and a second phase detector PD2, wherein: the high Duan Chazhi device consists of a reference clock counter with an enabling control end, and is provided with two input ends and an output end, wherein a first input end of the high Duan Chazhi device receives an external input reference clock Ref_clk as a clock control end of the counter; the second input end is connected with a control signal ctrl output by the alternative control selector, and the control signal can enable the reference clock counter to start counting and can lock the reference clock to stop counting; the output end outputs the high-level quantized result D3 and is connected and output to the data processing and calibrating module 6; the two-out-of-one control selector is provided with three input ends and one output end, wherein the first input end is connected with a high level, the second input end is connected with a low level, and the third input end is connected with a control signal Sel output by the second phase detector PD 2; the output end of the high-stage interpolator outputs a control signal ctrl to the high-stage interpolator, and the control signal ctrl is used for controlling the start or stop of a reference clock counter in the high-stage interpolator; the second phase detector PD2 is provided with two input ends and two output ends, the first input end is connected with the enable signal en2 output by the coarse time digital converter module 4, and the second input end is connected with an external input reference clock ref_clk, and is used for detecting the phase of ref_clk; the first output end outputs a control signal Sel and is connected to the alternative control selector, and the second output end outputs a disable signal disten 2 and is connected to the coarse time digital converter module 4 for ending the middle section quantization process.
Referring to fig. 6, the middle interpolator adopts a voltage-controlled ring oscillator structure based on a frequency synthesizer, and the output of the middle interpolator comprises two parts, wherein one part is a periodic signal representing an integer oscillation period, and the other part is a fractional part of less than one oscillation period; score ofPart of the current output phase information is represented by each delay cell tap in the ring oscillator; the middle-section interpolator comprises a frequency controller, N voltage-controlled delay units, N D triggers and N>1, a step of; the N voltage-controlled delay units are connected end to form a ring oscillator, the Nth delay unit in the ring oscillator is used as the output end of the ring oscillator to output a periodic signal Clk representing the integer part of the oscillation period of the ring oscillator in the middle-section interpolator, and the frequency controller combines an external input reference clock Ref_clk and the ring oscillator output signal Clk to obtain a frequency control signal V ctrl To control the output of the ring oscillator to be in an integer multiple relationship with the reference clock ref_clk; the N D triggers respectively latch the outputs of the N voltage-controlled delay units and obtain a signal DN representing the fractional part of the middle-section differential device; the enable signal en1 is used to control the operation timings of the N D flip-flops. The middle section data processor specifically comprises a middle section counter, a state decoder and a combined decoder functional module; when the first phase detector PD1 detects that the first 1 appears in the signal DN representing the state information of the output level of each tap of the ring oscillator in the middle interpolator, the output enable signal en2 is at high level, and the counter starts counting the periodic square wave signal Clk representing the output of the middle interpolator. The state decoder decodes the phase state of each tap on the delay chain of the ring oscillator according to fractional part signals DN representing less than one oscillation period of the ring oscillator in the middle-stage interpolator to obtain fractional parts less than one oscillation period; the combined decoder performs the combined decoding again on the integer part remembered by the counter and the fractional part decoded by the decoder to obtain a middle bit quantization result D2.
Referring to fig. 7, the low-stage interpolator is a two-dimensional vernier delay chain type TDC which comprises a sampling D flip-flop array including a first delay chain, a second delay chain, and m×m dimensions, M>1, a step of; the first delay chain consists of M voltage-controlled delay units 1, and the delay time length of each single delay unit is tau 1 ，τ 1 > 0, the delay time τ 1 And a first control signal V ctr1 The enable signal en1 is used to enable the first delay chain in direct proportion to the voltage value of (a); the second extensionThe time chain consists of M voltage-controlled delay units 2, and the delay time of a single delay unit is tau 2 ，τ 2 > 0, the delay time τ 2 And a second control signal V ctr2 The enable signal en2 is used to enable the second delay chain in direct proportion to the voltage value of (a); due to the delay tau of the delay cells in the first delay chain 1 A delay tau greater than the delay elements in the second delay chain 2 Thus, the first delay chain is also called slow delay chain and the second delay chain is also called fast delay chain; the M x M dimension sampling D trigger array is used for sampling the relative positions of signal transmission in the two delay chains, and outputs a binary character string with M2 bits, and the binary character string is transmitted to the low-stage data processor.
The working principle of the invention with reference to fig. 4 to 7 is: the external input reference clock Ref_clk passes through a frequency controller in the middle-stage differential device to obtain a first control signal V ctrl1 Obtaining a second control signal V through a first frequency synthesizer FS12 ctrl2 The method comprises the steps of carrying out a first treatment on the surface of the Wherein the first control signal V ctrl1 Controlling the oscillation frequency of the first delay chain in the low-stage interpolator, and the second control signal V ctrl2 The frequency of the second delay chain in the low-stage interpolator is controlled. When the Start signal arrives, en1 output by the control signal generating module 1 becomes high level, a first delay chain (slow chain) in the low-stage interpolator starts to work, N D triggers in the median interpolator are enabled, when the first phase detector PD1 detects that the first 1 appears in a signal DN representing phase transmission state information on the ring oscillator in the middle-stage interpolator, the output enabling signal en2 is high level, a second delay chain (fast chain) in the low-stage difference device starts to work, when the fast chain catches up with the slow chain, the low-stage bit quantization is ended, a quantized result is recorded by the low-stage data processor and is sent to the data processing calibration unit 6, and the measurement result of the low-stage interpolator is t1; meanwhile, when the enable signal en2 is at high level, the counter in the middle stage data processor starts counting the periodic signal Clk representing the integer part of the oscillation period of the ring oscillator in the middle stage interpolator, and the state decoder counts the tap phases of the delay chain of the ring oscillator according to the fractional periodic signal DN representing the initial phase state of the ring oscillator in the middle stage interpolatorDecoding the state to obtain fractional parts of less than one oscillation period; the combined decoder completes the re-combined decoding of the integer part remembered by the counter and the fraction part translated by the decoder so as to obtain a middle bit quantization result D2; meanwhile, when the enable signal en2 is at a high level, the second phase detector PD2 starts to operate, and when the first rising edge of the external reference clock ref_clk is detected, the control signal Sel is at a high level, the alternative control selector outputs a high level to the high Duan Chazhi device, the high Duan Chazhi device starts to count ref_clk, and the disable signal dis 2 output by the second phase detector PD2 is valid, so that the middle data processor stops receiving the output of the middle interpolator, which means that the middle interpolator is quantized to be finished, and the amount is t2.
When the Stop signal arrives, the control signal generating module 1 also generates an enable signal en1, a first delay chain (slow chain) in the low-stage interpolator starts to work, N D triggers in the middle-stage interpolator are enabled, when the first phase detector PD1 detects that the first 1 appears in a signal DN representing phase transmission state information on the ring oscillator in the middle-stage interpolator, the output enable signal en2 is high level, a second delay chain (fast chain) in the low-stage differentiator starts to work, when the fast chain catches up with the slow chain, the low-stage bit quantization is ended, a quantized result is recorded by the low-stage data processor and is sent to the data processing calibration unit 6, and the measurement result of the low-stage differentiator is t4; meanwhile, when the enable signal en2 is at a high level, a counter in the middle section data processor starts to count a periodic signal Clk representing an integer part of the output oscillation period of the ring oscillator in the middle section interpolator, and a state decoder decodes the phase states of a plurality of taps on the delay chain of the ring oscillator according to a fractional periodic signal DN representing the initial phase state of the ring oscillator in the middle section interpolator to obtain fractional parts of less than one oscillation period; the combined decoder completes the re-combined decoding of the integer part calculated by the counter and the fraction part translated by the decoder to obtain a middle bit quantization result D2; meanwhile, when the enable signal en2 is at a high level, the second phase detector PD2 starts to operate, and when the first rising edge of the external reference clock ref_clk is detected, the control signal Sel is at a low level, the alternative control selector outputs a low level to the up Duan Chazhi device, so that the up Duan Chazhi device stops operating, the high-level quantization is ended, and the high-level quantization result is t3; meanwhile, the disable signal dis 2 output by the second phase detector PD2 is valid, so that the middle stage data processor stops receiving the output of the middle stage interpolator, which means that the quantization of the middle stage interpolator is finished, and the result is t5. Each segment of quantized results is input to a data processing calibration module 6, which is used to complete the calibration and combination of the final measurement results, and output in the form of binary codes. Fig. 5 shows the time quantization relationship among the low-stage interpolator, the middle-stage interpolator, and the high Duan Chazhi interpolator, and the time relationship between the corresponding measurement time and the measurement of each stage of interpolator can be expressed as t=t1+t2+t3-T4-T5.
The above description is only one specific example of the invention and does not constitute any limitation of the invention, and it will be apparent to those skilled in the art that various modifications and changes in form and details may be made without departing from the principles, construction of the invention, but these modifications and changes based on the idea of the invention are still within the scope of the claims of the invention.

Claims (7)

1. A high-resolution multipurpose time-to-digital converter circuit with large dynamic measurement range mainly comprises: the device comprises a control signal generation module (1), a first frequency synthesizer FS1 (2), a fine time digital converter module (3), a coarse time digital converter module (4), a reference clock counter module (5) and a data processing calibration module (6); the method is characterized in that:
the control signal generation module (1) is used for generating a control signal required by normal operation of the circuit, and is provided with two input ends and an output end, wherein the first input end is connected with a Start signal Start, and the second input end is connected with a Stop signal Stop; the output end outputs an enable signal en1 and is simultaneously connected to the fine time digital converter module (3) and the coarse time digital converter module (4);
the first frequency synthesizer FS1 (2) has an input and an outputAn output end, the input end is connected with an external input reference clock Ref_clk, and the output end outputs a second control signal V ctr2 And is connected to a fine time digitizer module (3);
the fine time digital converter module (3) mainly completes low-level bit quantization of time digital conversion and has four input ends and one output end, wherein the first input end is connected with an enable signal en1 output by the control signal generating module (1), and the second input end is connected with a second control signal V output by the first frequency synthesizer FS1 (2) ctr2 The third input end is connected with a first control signal V output by the coarse time digital converter module (4) ctr1 The fourth input end is connected with an enable signal en2 output by the coarse time digital converter module (4); the output end outputs a low-level quantization result D1 and is connected to the data processing calibration module (6);
the coarse time digital converter module (4) mainly completes middle-bit quantization of time digital conversion, and is provided with three input ends and three output ends, wherein the first input end is connected with an enable signal en1 output by the control signal generation module (1), the second input end is connected with an external input reference clock Ref_clk, and the third input end is connected with a disable signal unen 2 output by the reference clock counter module (5); the first output end outputs a first control signal V ctr1 The second output end outputs an enable signal en2 and is connected to the fine time digital converter module (3) and the reference clock counter module (5), and the third output end outputs a middle segment bit quantization result D2 and is connected to the data processing calibration module (6);
the reference clock counter module (5) is provided with two input ends and two output ends, the first input end is connected with an enable signal en2 output by the coarse time digital converter module (4), and the second input end is connected with an external input reference clock Ref_clk; the first output end outputs a disable signal distn 2 and is connected to the coarse time digital converter module (4), and the second output end outputs a high-level bit quantization result D3 and is connected to the data processing calibration module (6);
the data processing and calibrating module (6) is mainly used for completing calibration and combination of final measurement results and outputting the final measurement results in a binary code form, and is provided with three input ends and an output end, wherein the first input end is connected with a low-level bit quantization result D1 output by the fine time digital converter module (3), the second input end is connected with a middle-level bit quantization result D2 output by the coarse time digital converter module (4), and the third input end is connected with a high-level bit quantization result D3 of the reference clock counter module (5); the output end is used for outputting the binary code of the measurement result.
2. The large dynamic measurement range high resolution multi-purpose TDC circuit according to claim 1, characterized in that the fine time digitizer module (3) comprises a low-stage interpolator and a low-stage data processor, wherein:
the low-stage interpolator is provided with four input ends and an output end, and the first input end is connected with an enable signal en1 output by the control signal generating module (1); a second input end connected with the second control signal V output by the first frequency synthesizer FS1 (2) ctr2 The method comprises the steps of carrying out a first treatment on the surface of the The third input end is connected with a first control signal V output by the coarse time digital converter module (4) ctr1 The method comprises the steps of carrying out a first treatment on the surface of the The fourth input end is connected with an enable signal en2 output by the coarse time digital converter module (4); the output end outputs the binary character string DM of M bits to the low-stage data processor;
the low-stage data processor is mainly used for preprocessing an M-bit binary string DM output by the low-stage interpolator so as to realize conversion of the quantization time of the low-stage interpolator, and the low-stage data processor is provided with an input end and an output end, wherein the input end is connected with the M-bit binary string DM output by the low-stage interpolator, and the output end outputs a low-stage bit quantization result D1 and is connected to the data processing calibration module (6).
3. The large dynamic measurement range high resolution multipurpose time to digital converter circuit of claim 1, wherein the coarse time to digital converter module (4) includes a mid-section interpolator, a first phase detector PD1, and a mid-section data processor, wherein:
the middle-stage interpolator is a ring oscillation type time-digital converter based on a frequency synthesizer, and has two input ends and three output ends, wherein the first input end is connected with an external input reference clock Ref_clk, the second input end is connected with an enable signal en1 output by the control signal generating module (1); the first output end outputs a periodic oscillation signal Clk representing the cyclic oscillator in the middle-stage difference device and is connected to the middle-stage data processor, the second output end outputs an N-bit binary character string DN representing the output phase state of each delay unit on the cyclic oscillator in the middle-stage difference device, and the N-bit binary character string also represents the fractional part of less than one oscillation period and is connected to the interrupt data processor and the first phase detector PD1, and the third output end outputs a first control signal V ctr1 And is connected to a fine time digitizer module (3);
the first phase detector PD1 is provided with an input end and an output end, the input end of the first phase detector is connected with an N-bit binary string DN which is output by the middle-stage interpolator and represents a fractional part of the output oscillation period of the ring oscillator in the middle-stage interpolator, and the N-bit binary string DN is used for detecting the jump of the tap output level of the ring oscillator in the middle-stage interpolator; the output end of the digital clock counter module outputs an enable signal en2 and is connected to the fine time digital converter module (3), the reference clock counter module (5) and the middle section data processor;
the middle section data processor is mainly used for correspondingly processing the quantized result of the middle section interpolator-the ring oscillator so as to realize conversion of the quantized time of the middle section interpolator, and is provided with four input ends and an output end, wherein the first input end is connected with an output periodic oscillating signal Clk representing the ring oscillator of the middle section interpolator, the second input end is connected with an N-bit binary character string DN representing the output phase state of each delay unit on the ring oscillator of the middle section interpolator, the third input end is connected with an enable signal en2, and the fourth input end is connected with a disable signal distn 2 output by the reference clock counter module (5); the output end outputs the middle segment bit quantization result D2 and is connected to the data processing calibration module (6).
4. The large dynamic measurement range high resolution multipurpose time to digital converter circuit of claim 1, wherein the reference clock counter module (5) includes a high Duan Chazhi selector, an alternative control selector, and a second phase detector PD2, wherein:
the high Duan Chazhi device consists of a reference clock counter with an enabling control end, and is provided with two input ends and an output end, wherein a first input end of the high Duan Chazhi device receives an external input reference clock Ref_clk as a clock control end of the counter; the second input end is connected with a control signal ctrl output by the alternative control selector, and the control signal can enable the reference clock counter to start counting and can lock the reference clock to stop counting; the output end outputs a high-level quantization result D3 and is connected and output to a data processing and calibrating module (6);
the two-out-of-one control selector is provided with three input ends and one output end, wherein the first input end is connected with a high level, the second input end is connected with a low level, and the third input end is connected with a control signal Sel output by the second phase detector PD 2; the output end of the high-stage interpolator outputs a control signal ctrl to the high-stage interpolator, and the control signal ctrl is used for controlling the start or stop of a reference clock counter in the high-stage interpolator;
the second phase detector PD2 is provided with two input ends and two output ends, the first input end is connected with an enable signal en2 output by the coarse time digital converter module (4), and the second input end is connected with an external input reference clock Ref_clk and used for detecting the phase of the Ref_clk; the first output end outputs a control signal Sel and is connected to the alternative control selector, and the second output end outputs a disable signal disten 2 and is connected to the coarse time digital converter module (4) for ending the middle section quantization process.
5. The large dynamic measurement range high resolution multipurpose time to digital converter circuit of claim 2, wherein: the low-stage interpolator is a two-dimensional vernier delay chain type time-to-digital converter, which comprises a first delay chain, a second delay chain and a sampling D trigger array with M-dimension and M-dimension>1, a step of; the first delay chain consists of M voltage-controlled delay units 1, and the delay time length of each single delay unit is tau 1 ，τ 1 > 0, the delay time τ 1 In proportion to the voltage value of the first control signal Vctr1, the enable signal en1 is used to enable the first delay chain; the second delay chain consists of M voltage-controlled delay units 2, and the delay time length of a single delay unitIs tau 2 ，τ 2 > 0, the delay time τ 2 In proportion to the voltage value of the second control signal Vctr2, the enable signal en2 is used to enable the second delay chain; due to the delay tau of the delay cells in the first delay chain 1 A delay tau greater than the delay elements in the second delay chain 2 Thus, the first delay chain is also called slow delay chain and the second delay chain is also called fast delay chain; the M x M dimension sampling D trigger array is used for sampling the relative positions of signal transmission in the two delay chains, outputting a binary character string with M2 bits, and transmitting the binary character string to the low-stage data processor for preprocessing.
6. A large dynamic measurement range high resolution multipurpose time to digital converter circuit according to claim 3, characterized in that: the middle-section interpolator adopts a frequency synthesizer based on a ring oscillator structure to realize a coarse quantization time-to-digital converter, and the output of the middle-section interpolator comprises two parts, wherein one part is the output oscillation period of the ring oscillator, and the other part is a fraction part of less than one oscillation period; the fraction part represents the current output phase information of each delay unit tap of the ring oscillator; the middle-section interpolator comprises a frequency controller, N voltage-controlled delay units, N D triggers and N>1, a step of; the N voltage-controlled delay units are connected end to form a ring oscillator, the Nth delay unit in the ring oscillator is used as the output end of the ring oscillator to output a signal Clk representing the integer part of the oscillation period of the middle-section interpolator, and the frequency controller is combined with an external input reference clock Ref_clk and the output signal Clk of the ring oscillator to obtain a first control signal V ctrl1 The output of the ring oscillator is controlled to be in integral multiple relation with the reference clock Ref_clk, and the delay time of each delay unit in the first delay chain in the low-stage interpolator is also controlled; the N D flip-flops latch the outputs of the N voltage-controlled delay units respectively, and the enable signal en1 is used for controlling the working time of the N D flip-flops.
7. A large dynamic measurement range high resolution multipurpose time to digital converter circuit according to claim 3, characterized in that: the middle section data processor specifically comprises a middle section counter, a state decoder and a combined decoder functional module; when the first phase detector PD1 detects that the first 1 appears in the signal DN representing the fractional part of the middle-stage interpolator, the output enable signal en2 is at a high level, and at this time, the middle-stage counter starts counting the signal Clk representing the integer part of the middle-stage interpolator, and the state decoder performs sampling decoding on the phase states of the taps on the delay chain of the ring oscillator according to the signal DN representing the fractional part of the output oscillation period of the middle-stage interpolator, so as to obtain fractional parts of less than one oscillation period; the combined decoder performs the combined decoding again on the integer part remembered by the counter and the fractional part decoded by the decoder to obtain a middle bit quantization result D2.
CN202210920968.0A 2022-08-08 2022-08-08 Large dynamic measurement range high-resolution multipurpose time-to-digital converter circuit Pending CN116794962A (en)

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