CN116784010A - 具有金属合金接合垫的接合半导体裸片组件和其形成方法 - Google Patents
具有金属合金接合垫的接合半导体裸片组件和其形成方法 Download PDFInfo
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- CN116784010A CN116784010A CN202180089386.6A CN202180089386A CN116784010A CN 116784010 A CN116784010 A CN 116784010A CN 202180089386 A CN202180089386 A CN 202180089386A CN 116784010 A CN116784010 A CN 116784010A
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- 238000000034 method Methods 0.000 title claims description 60
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
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- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
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- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 1
- 229910000570 Cupronickel Inorganic materials 0.000 description 1
- 229910002482 Cu–Ni Inorganic materials 0.000 description 1
- 241001424392 Lucia limbaria Species 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910018104 Ni-P Inorganic materials 0.000 description 1
- 229910018536 Ni—P Inorganic materials 0.000 description 1
- 229910001096 P alloy Inorganic materials 0.000 description 1
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- DZPJVKXUWVWEAD-UHFFFAOYSA-N [C].[N].[Si] Chemical compound [C].[N].[Si] DZPJVKXUWVWEAD-UHFFFAOYSA-N 0.000 description 1
- RIRXDDRGHVUXNJ-UHFFFAOYSA-N [Cu].[P] Chemical compound [Cu].[P] RIRXDDRGHVUXNJ-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
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- FZQBLSFKFKIKJI-UHFFFAOYSA-N boron copper Chemical compound [B].[Cu] FZQBLSFKFKIKJI-UHFFFAOYSA-N 0.000 description 1
- 239000000872 buffer Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000000109 continuous material Substances 0.000 description 1
- 229910001431 copper ion Inorganic materials 0.000 description 1
- YOCUPQPZWBBYIX-UHFFFAOYSA-N copper nickel Chemical compound [Ni].[Cu] YOCUPQPZWBBYIX-UHFFFAOYSA-N 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
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- 239000011574 phosphorus Substances 0.000 description 1
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- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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Classifications
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Abstract
一种接合组件包含第一半导体裸片和第二半导体裸片。所述第一半导体裸片包含嵌入于第一电介质材料层中的第一金属接合垫,所述第二半导体裸片包含嵌入于第二电介质材料层中的第二金属接合垫,所述第一金属接合垫接合到所述第二金属接合垫中的相应一者;且所述第一金属接合垫中的每一者包含腐蚀屏障层,所述腐蚀屏障层含有主接合金属与不同于所述主接合金属的至少一种腐蚀抑制元素的合金。
Description
相关申请
本申请要求2021年2月4日提交的第17/167,161号美国非临时申请的优先权益,所述申请的全部内容以引用的方式并入本文中。
技术领域
本公开大体上涉及半导体装置的领域,且具体来说,涉及具有防腐蚀金属合金接合垫的半导体裸片以及其形成方法。
背景技术
半导体存储器装置可包含位于同一衬底上的存储器阵列和驱动器电路。然而,驱动器电路占据衬底上的宝贵空间,因此减少了可用于存储器阵列的空间。
发明内容
根据本公开的一方面,一种形成半导体结构的方法包含:提供第一半导体裸片,所述第一半导体裸片包含位于第一衬底上方的第一半导体装置且包含嵌入于第一电介质材料层中的第一金属互连结构;在所述第一半导体裸片的前侧上形成垫腔,其中所述第一金属互连结构的子集的表面物理上暴露于所述垫腔的底部表面处;以及在所述垫腔中形成第一金属接合垫。所述第一金属接合垫中的每一者包括腐蚀屏障层,所述腐蚀屏障层包括主接合金属与不同于所述主接合金属的至少一种腐蚀抑制元素的合金。
根据本公开的另一方面,一种接合组件包含第一半导体裸片和第二半导体裸片。所述第一半导体裸片包含嵌入于第一电介质材料层中的第一金属接合垫,所述第二半导体裸片包含嵌入于第二电介质材料层中的第二金属接合垫,所述第一金属接合垫接合到所述第二金属接合垫中的相应一者;且所述第一金属接合垫中的每一者包含腐蚀屏障层,所述腐蚀屏障层含有主接合金属与不同于所述主接合金属的至少一种腐蚀抑制元素的合金。
附图说明
图1是根据本公开的实施例的在形成第一垫层级电介质层和第一金属接合垫之后的第一半导体裸片的示意竖直横截面图。
图2A-2E是根据本公开的第一实施例的在形成第一金属接合垫期间第一半导体裸片的第一配置的区域的顺序竖直横截面图。
图3A和3B是根据本公开的第二实施例的在形成第一金属接合垫期间第一半导体裸片的第二配置的区域的顺序竖直横截面图。
图4A和4B是根据本公开的第三实施例的在形成第一金属接合垫期间第一半导体裸片的第三配置的区域的顺序竖直横截面图。
图5是根据本公开的实施例的在形成第二垫层级电介质层和第二金属接合垫之后的第二半导体裸片的示意竖直横截面图。
图6是根据本公开的实施例的在形成第二金属接合垫之后第二半导体裸片的第一配置的区域的竖直横截面图。
图7为根据本公开的实施例的在形成第二金属接合垫之后第二半导体裸片的第二配置的区域的竖直横截面图。
图8是根据本公开的实施例的在形成第二金属接合垫之后第二半导体裸片的第三配置的区域的竖直横截面图。
图9是根据本公开的实施例的第一半导体裸片和第二半导体裸片的示例性接合组件的竖直横截面图。
图10A和10B是根据本公开的第一实施例的示例性接合组件的第一配置的区域的顺序竖直横截面图。
图11A和11B是根据本公开的第二实施例的示例性接合组件的第二配置的区域的顺序竖直横截面图。
图12是根据本公开的第三实施例的示例性接合组件的第三配置的区域的竖直横截面图。
图13是根据本公开的实施例的在形成背侧接合垫之后的示例性接合组件的竖直横截面图。
具体实施方式
晶片到晶片接合或裸片到裸片接合可用于竖直堆叠半导体裸片,由此实现堆叠式接合半导体裸片的制造。对金属接合垫中的金属的腐蚀在金属到金属接合中具有有害影响。腐蚀的金属接合垫表面使接合强度减小、呈现空隙且降低对电迁移的抗性。本公开的实施例涉及用于半导体裸片接合的防腐蚀金属合金(例如,铜或铝合金)接合垫和其形成方法,现在详细描述所述防腐蚀金属合金接合垫的各个方面。
各图未按比例绘制。除非明确地描述或以其它方式清楚地指示不存在元件的重复,否则在示出元件的单个实例的情况下,可重复元件的多个实例。例如“第一”、“第二”以及“第三”等序数仅用以标识类似元件,且可跨本公开的说明书和权利要求书采用不同序数。术语“至少一个”元件是指包含单个元件的可能性和多个元件的可能性的所有可能性。
相同附图标号是指相同元件或类似元件。除非另外指示,否则假定具有相同附图标号的元件具有相同组成和相同功能。除非另有指示,否则元件之间的“接触”是指元件之间提供由所述元件共享的边缘或表面的直接接触。如果两个或更多个元件彼此不直接接触或彼此间不直接接触,则所述两个元件“彼此分离”或“彼此间分离”。如本文中所使用,位于第二元件“上”的第一元件可位于第二元件的表面的外侧上或第二元件的内侧上。如本文中所使用,如果第一元件的表面与第二元件的表面之间存在物理接触,则第一元件“直接”定位于第二元件“上”。如本文中所使用,如果第一元件与第二元件之间存在由至少一种导电材料组成的导电路径,则第一元件“电连接到”第二元件。如本文中所使用,“原型(prototype)”结构或“处理中”结构是指其中至少一个组件的形状或组成随后被修改的暂时结构。
如本文中所使用,“层”是指包含具有厚度的区域的材料部分。层可在整个下伏或上覆结构上方延伸,或可具有比下伏或上覆结构的范围小的范围。另外,层可以是厚度小于连续结构的厚度的均质或非均质连续结构的区域。例如,层可位于在连续结构的顶部表面与底部表面之间或在连续结构的顶部表面和底部表面处的任何一对水平平面之间。层可水平地、竖直地和/或沿着锥形表面延伸。衬底可以是层,可在其中包含一个或多个层,或可在其上、其上方和/或其下具有一个或多个层。
如本文中所使用,如果第二表面上覆于或下伏于第一表面且存在包含第一表面和第二表面的竖直平面或基本竖直平面,则第一表面和第二表面彼此“竖直重合”。基本竖直平面是沿着偏离竖直方向小于5度的角度的方向笔直延伸的平面。竖直平面或基本竖直平面沿着竖直方向或基本竖直方向是笔直的,且沿着垂直于竖直方向或基本竖直方向的方向可包含或可不包含曲率。
如本文中所使用,“存储器层级”或“存储器阵列层级”是指对应于包含存储器元件阵列的最顶部表面的第一水平平面(即,平行于衬底的顶部表面的平面)与包含存储器元件阵列的最底部表面的第二水平平面之间的一般区域的层级。如本文中所使用,“贯穿堆叠”元件是指竖直延伸穿过存储器层级的元件。
如本文中所使用,“半导电材料”是指具有1.0×10-5S/m到1.0×105S/m范围内的电导率的材料。如本文中所使用,“半导体材料”是指在其中不存在电掺杂剂的情况下具有1.0x 10-5S/m到1.0S/m范围内的电导率的材料,且其能够在利用电掺杂剂合适掺杂时产生具有1.0S/m到1.0x 105S/m范围内的电导率的掺杂材料。如本文中所使用,“电掺杂剂”是指将空穴添加到能带结构内的价带的p型掺杂剂,或将电子添加到能带结构内的导带的n型掺杂剂。如本文中所使用,“导电材料”是指具有大于1.0×105S/m的电导率的材料。如本文中所使用,“绝缘体材料”或“电介质材料”是指具有小于1.0×10-5S/m的电导率的材料。如本文所使用,“重掺杂半导体材料”是指以足够高的原子浓度掺杂有电掺杂剂以变为导电材料的半导体材料,所述导电材料要么形成为结晶材料,要么通过退火过程转换为结晶材料(例如,从初始非晶态),即,具有大于1.0x 105S/m的电导率。“掺杂半导体材料”可以是重掺杂半导体材料,或可以是包含提供1.0x 10-5S/m到1.0x 105S/m范围内的电导率的浓度下的电掺杂剂(即,p型掺杂剂和/或n型掺杂剂)的半导体材料。“本征半导体材料”是指未掺杂有电掺杂剂的半导体材料。因此,半导体材料可以是半导电或导电的,并且可以是本征半导体材料或掺杂半导体材料。掺杂半导体材料可取决于其中的电掺杂剂的原子浓度而为半导电或导电的。如本文中所使用,“金属材料”是指其中包含至少一种金属元素的导电材料。针对电导率的所有测量均在标准条件下进行。
本公开的各种三维存储器装置包含单片三维NAND串存储器装置,且可使用本文中所描述的各种实施例来制造。单片三维NAND串位于定位在衬底上方的单片三维NAND串阵列中。三维NAND串阵列的第一装置层级中的至少一个存储器单元位于三维NAND串阵列的第二装置层级中的另一存储器单元上方。
通常,半导体封装(或“封装”)是指可通过一组引脚或焊球附接到电路板的单元半导体装置。半导体封装可包含半导体芯片(或“芯片”)或例如通过倒装芯片接合或另一种芯片到芯片接合而接合在一起的多个半导体芯片。封装或芯片可包含单个半导体裸片(或“裸片”)或多个半导体裸片。裸片是可独立地执行外部命令或报告状态的最小单元。通常,具有多个裸片的封装或芯片能够同时执行与其中的平面总数目一样多的外部命令。每个裸片包含一个或多个平面。相同的并行操作可在同一裸片内的每个平面中执行,但可能存在一些限制。在裸片是存储器裸片,即,包含存储器元件的裸片的情况下,并行读取操作、并行写入操作或并行擦除操作可在同一存储器裸片内的每个平面中执行。在存储器裸片中,每个平面含有若干存储器块(或“块”),所述存储器块是可在单个擦除操作中擦除的最小单元。每个存储器块含有数个页,页是可被选择用于编程的最小单元。页也是可被选择以进行读取操作的最小单位。
参考图1,示出第一半导体裸片900。第一半导体裸片900包含第一衬底908、上覆于第一衬底908的第一半导体装置920、位于第一半导体装置上的第一互连层级电介质材料层(290、960),以及嵌入于第一互连层级电介质材料层(290、960)中的第一金属互连结构980。在一个实施例中,第一衬底908可以是第一衬底,例如具有范围从500微米到1mm的厚度的市售硅晶片。
通过在第一衬底908的顶部表面上方施加光致抗蚀剂层、光刻图案化光致抗蚀剂层以形成离散开口阵列以及通过执行各向异性蚀刻过程将离散开口阵列的图案转移到第一衬底的上部部分中,可在第一衬底908的上部部分中形成离散衬底凹部腔。随后可例如通过灰化移除光致抗蚀剂层。每个离散衬底凹部腔的深度可在从500nm到10,000的范围内,但也可采用更小和更大的深度。贯穿衬底衬里386和贯穿衬底通孔结构388可形成于每个离散衬底凹部腔内。
一般来说,第一半导体装置920可包括所属领域中已知的任何半导体装置。在一个实施例中,第一半导体裸片900包括存储器裸片,且可包含存储器装置,例如三维NAND存储器装置。在说明性实例中,第一半导体装置920可包含绝缘层32和导电层46的竖直交替堆叠,以及竖直延伸穿过所述竖直交替堆叠(32、46)的存储器开口的二维阵列。导电层46可包括三维NAND存储器装置的字线。
存储器开口填充结构58可形成于每个存储器开口内。存储器开口填充结构58可包含存储器膜和接触存储器膜的竖直半导体通道。存储器膜可包含阻挡电介质、隧穿电介质和位于阻挡电介质与隧穿电介质之间的电荷存储材料。电荷存储材料可包括电荷捕获层,例如氮化硅层,或多个离散电荷捕获区,例如电荷捕获层的浮动栅极或离散部分。在此情况下,每个存储器开口填充结构58和导电层46的邻近部分构成竖直NAND串。替代地,存储器开口填充结构58可包含任何类型的非易失性存储器元件,例如电阻式存储器元件、铁电存储器元件、相变存储器元件等。存储器装置可包含连接到每个竖直半导体通道的底端的任选水平半导体通道层10,以及提供第一衬底908与水平半导体通道层10之间的电隔离的任选电介质间隔物层910。
导电层46可被图案化以提供阶台区,其中每个上覆导电层46具有比任何下伏导电层46更小的侧向范围。触点通孔结构(未示出)可在阶台区中形成于导电层46上以提供到导电层46的电连接。电介质材料部分65可形成于每个竖直交替堆叠(32、46)周围以提供相邻竖直交替堆叠(32、46)之间的电隔离。
贯穿存储器层级通孔腔可穿过电介质材料部分65、任选的电介质间隔物层910和水平半导体通道层10形成。任选的贯穿存储器层级电介质衬里486和贯穿存储器层级通孔结构488可形成于每个贯穿存储器层级通孔腔内。每个贯穿存储器层级电介质衬里486包含例如氧化硅的电介质材料。每个贯穿存储器层级通孔结构488可直接形成于贯穿衬底通孔结构388中的相应一者上。
第一互连层级电介质材料层(290、960)可包含嵌入触点通孔结构和位线982的第一近侧互连层级电介质材料层290,以及嵌入位于第一近侧互连层级电介质材料层290上方的第一金属互连结构980的子集的第一远侧互连层级电介质材料层960。如本文所使用,“近侧”表面是指接近于衬底的表面,且“远侧”表面是指远离衬底的表面。在第一半导体裸片900中,近侧表面是指接近于第一衬底908的表面,且远侧表面是指远离第一衬底908的表面。
位线982是第一金属互连结构980的子集且可电接触位于存储器开口填充结构58的顶部处的半导体通道上方的漏极区。触点通孔结构接触第一半导体装置的各种节点。一般来说,第一金属互连结构980可电连接到第一半导体装置920。第一金属互连结构980的近侧子集可位于第一远侧互连层级电介质材料层960内。作为第一金属互连结构980的子集的互连金属线和互连金属通孔结构可嵌入于第一远侧互连层级电介质材料层960中。在说明性实例中,第一金属互连结构980可包含多个存储器侧金属线层级和多个存储器侧金属通孔层级。
第一近侧互连层级电介质材料层290和第一远侧互连层级电介质材料层960中的每一者可包含电介质材料,例如未掺杂硅酸盐玻璃、掺杂硅酸盐玻璃、有机硅酸盐玻璃、氮化硅、电介质金属氧化物或其组合。第一远侧互连层级电介质材料层960可包含一个或多个电介质扩散屏障衬里(未明确示出)。在此情况下,嵌入于第一远侧互连层级电介质材料层960中的每个电介质扩散屏障衬里可包含氮化硅碳(即,硅碳氮“SiCN”,其也被称作氮化碳化硅(silicon carbide nitride))、氮化硅(Si3N4)、氮氧化硅或有效阻挡铜扩散的任何其它电介质材料。在一个实施例中,嵌入于第一远侧互连层级电介质材料层960中的每个电介质扩散屏障衬里可包含介电常数小于5的电介质材料,例如介电常数约为3.8的SiCN,以减小第一金属互连结构980的RC延迟。每个电介质扩散屏障衬里可具有10nm到30nm范围内的厚度。
可形成包含任选的第一互连封盖电介质扩散屏障衬里962和第一垫层级电介质层990的层堆叠。第一互连封盖电介质扩散屏障衬里962可包含阻挡铜扩散的电介质材料。在一个实施例中,第一互连封盖电介质扩散屏障衬里962可包含氮化硅、碳氮化硅、氮氧化硅或其堆叠。第一互连封盖电介质扩散屏障衬里962的厚度可在5nm到50nm的范围内,但也可采用更小和更大的厚度。
第一垫层级电介质层990可包含未掺杂硅酸盐玻璃(例如,氧化硅)、掺杂硅酸盐玻璃、有机硅酸盐玻璃、氮化硅、碳氮化硅或电介质金属氧化物,和/或主要由前述成分组成。第一垫层级电介质层990的厚度可在100nm到300nm的范围内,但也可采用更小和更大厚度。第一垫层级电介质层990可具有平坦顶部表面。
图2A-2E是根据本公开的第一实施例的在形成第一金属接合垫998期间第一半导体裸片900的第一配置的区域的顺序竖直横截面图。
参考图2A,光致抗蚀剂层可施加于第一垫层级电介质层990上方,且可被光刻图案化以在上覆于第一金属互连结构980的最顶部金属互连结构的区域中形成离散开口。可执行各向异性蚀刻过程以通过第一垫层级电介质层990和第一互连封盖电介质扩散屏障衬里962来转移光致抗蚀剂层中的开口的图案。在上覆于金属互连结构980的区域中,形成穿过第一垫层级电介质层990和第一互连封盖电介质扩散屏障衬里962的第一垫通孔腔91。最顶部金属互连结构980的顶部表面可物理上暴露于每个第一垫通孔腔91的底部。在一个实施例中,可在最顶部金属互连结构中的相应一者的区域内形成每个第一垫通孔腔91。
在图2A中示出在形成第一垫腔91之后的第一半导体裸片900的第一配置的区域。第一垫腔91可具有矩形或圆角矩形的水平横截面形状。第一垫腔91中的每一者可具有限定第一垫腔91的四个侧壁的两对平行侧壁。在相应的一对平行侧壁之间测量的第一垫腔91的侧向距离(即,长度和宽度)可以是200nm或更小,例如在从50nm到200nm的范围内,例如从100nm到150nm,但也可采用更小和更大的侧向距离。第一垫腔91的间距可以是1微米或更小,例如在从200nm到1微米的范围内。
通常,可提供第一半导体裸片900,其包含位于第一衬底908上的第一半导体装置920并且包含嵌入于第一电介质材料层(960、962、990)中的第一金属互连结构980。第一垫腔91可形成于第一半导体裸片900的前侧上,使得第一金属互连结构980的子集的表面物理上暴露于第一垫腔91的底部表面处。
参考后续图,可在第一垫通孔腔中依序沉积任选的垫层级金属屏障衬里和至少一种垫层级金属填充材料。可从包含第一垫层级电介质层990的顶部表面的水平平面上方移除垫层级金属屏障衬里和至少一种垫层级金属填充材料的多余部分。垫层级金属屏障衬里和至少一种垫层级金属填充材料的剩余部分包括第一金属接合垫998。本公开的各种实施例提供用于将第一金属接合垫998形成为防腐蚀结构的方法和结构。本公开的额外实施例提供用于形成含有第二金属接合垫作为防腐蚀结构的第二半导体裸片的方法和结构。本公开的其它实施例提供用于形成含有防腐蚀金属接合垫的半导体裸片接合组件的方法和结构。
本公开的附加实施例提供了用于形成包含作为耐腐蚀结构的第二金属焊盘的第二半导体管芯的方法和结构。本公开的进一步的实施例提供了方法和结构
具体地,参考图2B,包含导电金属氮化物材料的任选连续金属屏障衬里92L可直接沉积在垫腔91的物理上暴露的表面上。连续金属屏障衬里92L包含例如TiN、TaN和/或WN等导电金属屏障材料。导电金属屏障材料可阻挡铜或铝的扩散。连续金属屏障衬里92L的厚度可在2nm到10nm的范围内,例如从4nm到8nm,但也可采用更小和更大厚度。连续金属屏障衬里92L可通过物理气相沉积或化学气相沉积沉积。替代地,可省略连续金属屏障衬里92L。
包含第一原子百分比(即,浓度)的主接合金属的第一主接合金属层94L可作为连续材料层直接沉积在垫腔91内,在连续金属屏障衬里92L的物理上暴露的表面上(如果存在)或在第一金属互连结构980的物理上暴露的表面上(如果省略了衬里92L)。在一个实施例中,主接合金属可以是选自Cu和Al的金属元素。第一主接合金属层94L可通过电镀和/或物理气相沉积形成。
在一个实施例中,主接合金属是Cu,且第一原子百分比可在90%到100%的范围内,例如95%到99.9999%和/或99%到99.999%和/或99.9%到99.99%。在第一原子百分比不是100%的情况下,除了铜之外的至少一种添加剂元素可存在于第一主接合金属层94L内。至少一种添加剂元素可包含例如铅、锌、镍、铁、硫、锑、砷、银、锡、钙、锡等。在一个实施例中,至少一种添加剂元素的总原子百分比可小于1%,例如小于0.1%和/或小于0.01%和/或小于0.001%。在一个实施例中,第一主接合金属层94L可不含镍、硼或磷,或可包含镍、硼和/或磷,其原子百分比小于0.1%和/或小于0.01%和/或少于0.001%和/或小于0.0001%。
在另一实施例中,主接合金属是Al,且第一原子百分比可在从98%到100%的范围内,例如从99%到99.9999%和/或从99.8%到99.999%和/或99.98%到99.99%。在第一原子百分比不是100%的情况下,除了铜之外的至少一种添加剂元素可存在于第一主接合金属层94L内。至少一种添加剂元素可包含例如铅、锌、镍、铁、硫、锑、砷、银、锡、钙、锡等。在一个实施例中,至少一种添加剂元素的总原子百分比可小于1%,例如小于0.1%和/或小于0.01%和/或小于0.001%。在一个实施例中,第一主接合金属层94L可不含铜,或可包含原子百分比小于0.1%和/或小于0.01%和/或小于0.001%和/或小于0.0001%的铜。
参考图2C,通过执行平坦化过程,可从包含第一电介质材料层(960、962、990)的最顶部表面(例如第一垫层级电介质层990的最顶部表面)的水平平面上方移除第一主接合金属层94L和连续金属屏障衬里92L的部分。平坦化过程可采用化学机械抛光(CMP)过程或凹部蚀刻过程(其可包括各向同性蚀刻过程或各向异性蚀刻过程)。
在移除上覆于包含第一电介质材料层(960、962、990)的顶部表面的水平平面的第一主接合金属层94L和连续金属屏障衬里92L的部分之后,位于垫腔91内的第一主接合金属层94L和连续金属屏障衬里92L的剩余部分可通过执行凹部蚀刻过程在包含第一电介质材料层(960、962、990)的顶部表面的水平平面下方竖直凹入某一竖直凹入距离。凹部蚀刻过程可包含各向同性蚀刻过程(例如湿式蚀刻过程或化学干式蚀刻过程)和/或各向异性蚀刻过程(例如反应性离子蚀刻过程)。竖直凹入距离可在从10nm到100nm的范围内,例如从30nm到50nm,但也可采用更小和更大的竖直凹入距离。保持在垫腔91中的任选的连续金属屏障衬里92L的竖直凹入的剩余部分包括任选的第一金属屏障衬里92。保持在垫腔91中的主接合材料层94L的竖直凹入的剩余部分包括第一垫基底部分94,所述第一垫基底部分是第一金属接合垫的近侧区域(待随后完成),其相对于待随后形成的第一金属接合垫的额外区域处于第一垫腔91的底部表面的近侧。
参考图2D,包含处于第二原子百分比的主接合金属且包含至少一种腐蚀抑制元素的腐蚀屏障层96L可沉积在第一垫基底部分94上。根据本公开的方面,第二原子百分比可小于第一原子百分比。
在一个实施例中,主接合金属是Cu,且第二原子百分比可在50%到95%的范围内,例如55%到90%和/或60%到85%和/或65%到80%。在一个实施例中,所述至少一种腐蚀抑制元素中的每一者包括Ni、B或P。在一个实施例中,腐蚀屏障层96L可主要由Cu和选自Ni、B或P的单种腐蚀抑制元素组成。至少一种腐蚀抑制元素的总原子百分比可在10%到50%的范围内,例如12.5%到45%,和/或15%到40%,和/或20%到35%。例如,腐蚀屏障层96L可包括铜镍合金,其含有5到45原子百分比的镍和余量铜,例如5到15原子百分比的镍,或10原子百分比的镍,或30原子百分比的镍或44原子百分比的镍,和余量铜。替代地,腐蚀屏障层96L可包括铜磷合金或铜硼合金,其含有5到20原子百分比的硼或磷以及余量铜。
在另一实施例中,主接合金属为Al,且第二原子百分比可在90%到99.5%的范围内,例如91%到99.2%和/或95%到99%和/或98%到99%。所述至少一种腐蚀抑制元素可包含例如Cu。在一个实施例中,腐蚀屏障层96L可包括铝铜合金,且在一个实施例中可主要由Al和Cu组成。Cu的总原子百分比可在0.5%到10%的范围内,例如0.8%到9%,和/或1%到5%,和/或1%到2%。
通常,主接合金属可选自Cu和Al,且腐蚀屏障层96L可包括不同于主接合金属且选自Ni、B、P和Cu的至少一种腐蚀抑制元素。如果主接合金属是Cu,则至少一种腐蚀抑制元素可包括Ni。在一个实施例中,所述至少一种腐蚀抑制元素可包括Ni、Ni和B或Ni和P。在一个实施例中,第二原子百分比小于第一原子百分比,且第一垫基底部分94不含所述至少一种腐蚀抑制元素。
参考图2E,可执行化学机械抛光过程以移除腐蚀屏障层96L的上覆于包含第一电介质材料层(960、962、990)的最顶部表面(例如第一垫层级电介质层990的顶部表面)的水平平面的部分。腐蚀屏障层96L的剩余部分包括第一腐蚀屏障层96。任选的第一金属屏障衬里92、第一垫基底部分94和第一腐蚀屏障层96的每个连续组合构成第一金属接合垫998。第一腐蚀屏障层96的厚度可为100nm或更小,例如30nm到50nm。每个第一金属接合垫998包含直接形成于第一金属屏障衬里92(若存在,其为连续金属屏障衬里92L的剩余部分)上且在相应垫腔91的底部表面近侧的作为第一金属接合垫998的近侧区的第一垫基底部分94,以及远离垫腔91的底部表面的作为远侧区的腐蚀屏障层96。每个第一金属接合垫998包括相应的平坦顶部表面,所述平坦顶部表面由第一腐蚀屏障层96的顶部表面组成。每个第一金属接合垫998的顶部表面的周边可接触第一电介质材料层(960、962、990)当中的最顶部层的周边的周边。
图3A和3B是根据本公开的第二实施例的在形成第一金属接合垫期间第一半导体裸片900的第二配置的区域的顺序竖直横截面图。
参考图3A,可通过执行图2B的处理步骤且将第一主接合金属层94L的厚度减小而从图2A中所示的第一半导体裸片900的第一配置导出第一半导体裸片900的第二配置。具体地,第一主接合金属层94L的厚度可减小,使得第一垫腔91的区域的中心部分内的第一主接合金属层94L的水平顶部表面形成于某一高度处,所述高度比包含第一电介质材料层(960、962、990)的最顶部表面(例如第一垫层级电介质层990的顶部表面)的水平平面低某一竖直偏移距离。所述竖直偏移距离可在10nm到100nm的范围内,例如30nm到50nm,但也可采用更小和更大的竖直偏移距离。通常,上覆于每个垫腔91的中心部分的第一主接合金属层94L的每个凹入的顶部表面可相对于包含第一电介质材料层(960、962、990)的最顶部表面的水平平面竖直凹入范围在10nm到100nm内的竖直距离。
随后,可执行图2D的处理步骤以将腐蚀屏障层96L直接沉积在主接合金属层94L的顶部表面上。可选择腐蚀屏障层96L的厚度,使得腐蚀屏障层96L的整个顶部表面位于包含第一电介质材料层(960、962、990)的最顶部表面的水平平面上方。
参考图3B,可执行图2E的处理步骤以移除腐蚀屏障层96L、第一主接合金属层94L和任选的连续金属屏障衬里92L的部分,所述部分上覆于包含第一电介质材料层(960、962、990)的最顶部表面(例如第一垫层级电介质层990的顶部表面)的水平平面。腐蚀屏障层96L的剩余部分包括第一腐蚀屏障层96。第一金属屏障衬里92、第一垫基底部分94和任选的第一腐蚀屏障层92的每个连续组合构成第一金属接合垫998。因此,在此实施例中,第一金属接合垫998可在单个平坦化步骤(例如单个CMP步骤)期间形成。每个第一金属接合垫998包含直接形成于任选的第一金属屏障衬里92(其为连续金属屏障衬里92L的剩余部分)上且在相应垫腔91的底部表面近侧的作为第一金属接合垫998的近侧区的第一垫基底部分94,以及远离垫腔91的底部表面的作为远侧区的腐蚀屏障层96。每个第一金属接合垫998包括相应的平坦顶部表面,所述平坦顶部表面包含第一金属屏障衬里92的顶部表面、第一垫基底部分94的顶部表面和第一腐蚀屏障层96的顶部表面。每个第一金属接合垫998的顶部表面的周边可接触第一电介质材料层(960、962、990)当中的最顶部层的周边的周边。
图4A和4B是根据本公开的第三实施例的在形成第一金属接合垫期间第一半导体裸片900的第三配置的区域的顺序竖直横截面图。在第三实施例中,省略第一垫基底部分94。
参考图4A,通过以与图2B的处理步骤中相同的方式沉积包含导电金属氮化物材料的任选的连续金属屏障衬里92L,可从第一半导体裸片900的第一配置导出第一半导体裸片900的第三配置。替代地,可省略连续金属屏障衬里92L。
随后,可在连续金属屏障衬里92L(若存在)的物理上暴露的表面上或在第一金属互连结构980的物理上暴露的表面上(若省略衬里92L)沉积包含处于第二原子百分比的主接合金属且包含至少一种腐蚀抑制元素的上述腐蚀屏障层96L。
在一个实施例中,至少一种腐蚀抑制元素的百分比(即,浓度)可作为腐蚀屏障层96L的厚度的函数而恒定。在另一实施例中,腐蚀屏障层96L包括经过组成调节的腐蚀屏障层,其中至少一种腐蚀抑制元素的百分比(即,浓度)可随腐蚀屏障层96L的厚度而变化(即,增加和/或减小)。可通过使用镀覆以沉积腐蚀屏障层96L以及通过在沉积过程期间改变镀浴中和/或沉积层中的至少一种腐蚀抑制元素的浓度来实现至少一种腐蚀抑制元素的百分比的变化。沉积层中至少一种腐蚀抑制元素的百分比可通过调整镀浴的pH值、通过调整在电镀过程中施加的电流密度和/或通过调整镀浴中沉积控制速率添加剂(例如,苯并三唑)的浓度来改变,如Karel PS Haesevoets、Aleksandar Radisic和Philippe M.Vereecken.的以全文引用的方式并入本文中的“用于3D堆叠集成电路的微凸块金属化物的利用苯并三唑添加剂从酸性硫酸盐基电解质电沉积的富铜Cu1-xNix合金(0.05<x<0.15)(Copper RichCu1-xNix Alloys(0.05<x<0.15)Electrodeposited from Acid Sulfate-BasedElectrolyte with Benzotriazole Additive for Microbump Metallization for3DStacked Integrate Circuits)”(电化学学会期刊,166(8)(2019)D315)中所描述。
参考图4B,可执行化学机械抛光过程以移除连续金属屏障衬里92L(若存在)和腐蚀屏障层96L的部分,所述部分上覆于包含第一电介质材料层(960、962、990)的最顶部表面(例如第一垫层级电介质层990的顶部表面)的水平平面。连续金属屏障衬里92L的剩余部分包括金属屏障衬里92。腐蚀屏障层96L的剩余部分包括第一腐蚀屏障层96接合金属部分194。第一金属屏障衬里92与第一腐蚀屏障层96的每个连续组合构成第一金属接合垫998。因此,每个第一腐蚀屏障层96可在组成上是均质的或可经过组成调节。
参考图5,示出根据本公开的实施例的第二半导体裸片700。第二半导体裸片700包含第二衬底708、上覆于第二衬底708的第二半导体装置720、上覆于第二半导体装置720的第二互连层级电介质材料层760,以及嵌入于第二互连层级电介质材料层760中的第二金属互连结构780。在一个实施例中,第二半导体装置720可包含用于存储器装置的操作的至少一个互补金属氧化物半导体(CMOS)外围电路系统。在一个实施例中,第二衬底708可以是例如具有在从500微米到1mm的范围内的厚度的市售硅衬底的第二衬底。
通常,第二半导体装置可包括可与第一半导体裸片900中的第一半导体装置结合操作以提供增强的功能的任何半导体装置。在一个实施例中,第一半导体裸片900包括存储器裸片,且第二半导体裸片700包括逻辑裸片,所述逻辑裸片包含用于存储器裸片内的存储器装置(例如三维存储器元件阵列)的操作的支持电路系统(即,外围电路系统)。在一个实施例中,第一半导体裸片900可包含三维存储器装置,所述三维存储器装置包含三维存储器元件阵列、字线(其可包括导电层46的子集)和位线982,且第二半导体裸片700的第二半导体装置720可包含用于三维存储器元件阵列的操作的外围电路系统。所述外围电路系统可包含驱动第一半导体裸片900的三维存储器元件阵列的字线的一个或多个字线驱动器电路、驱动第一半导体裸片900的位线982的一个或多个位线驱动器电路、对字线的地址进行解码的一个或多个字线解码器电路、对位线982的地址进行解码的一个或多个位线解码器电路、感测第一半导体裸片900的存储器开口填充结构58内的存储器元件的状态的一个或多个感测放大器电路、向第一半导体裸片900中的水平半导体通道层10提供电力的源电源电路、数据缓冲器和/或锁存器,和/或可用以操作第一半导体裸片900的三维存储器装置的任何其它半导体电路。
第二互连层级电介质材料层760可包含电介质材料,例如未掺杂硅酸盐玻璃(例如,氧化硅)、掺杂硅酸盐玻璃、有机硅酸盐玻璃、氮化硅、电介质金属氧化物,或其组合。在说明性实例中,第二金属互连结构780可包含多个逻辑侧金属线层级和多个逻辑侧金属线层级。
可形成包含任选的第二互连封盖电介质扩散屏障衬里762和第二垫层级电介质层790的层堆叠。第二互连封盖电介质扩散屏障衬里762可包含阻挡铜扩散的电介质材料。在一个实施例中,第二互连封盖电介质扩散屏障衬里762可包含氮化硅、氮化硅碳、氮氧化硅或其堆叠。第二互连封盖电介质扩散屏障衬里762的厚度可在5nm到50nm的范围内,但也可采用更小和更大的厚度。
第二垫层级电介质层790可包含未掺杂硅酸盐玻璃(例如,氧化硅)、掺杂硅酸盐玻璃、有机硅酸盐玻璃、氮化硅或电介质金属氧化物,和/或主要由前述成分组成。第二垫层级电介质层790的厚度可在300nm到6,000nm的范围内,但也可采用更小和更大厚度。第二垫层级电介质层790可具有平坦顶部表面。
光致抗蚀剂层可施加于第二垫层级电介质层790上方,且可被光刻图案化以在上覆于第二金属互连结构780的最顶部金属互连结构的区域中形成离散开口。可执行各向异性蚀刻过程以通过第二垫层级电介质层790和第二互连封盖电介质扩散屏障衬里762来转移光致抗蚀剂层中的开口的图案。在上覆于金属互连结构780的区域中,形成穿过第二垫层级电介质层790和第二互连封盖电介质扩散屏障衬里762的第二垫通孔腔。最顶部金属互连结构780的顶部表面可物理上暴露于每个第二垫通孔腔的底部。在一个实施例中,可在最顶部金属互连结构中的相应一者的区域内形成每个第二垫通孔腔。
可在第二垫通孔腔中依序沉积垫层级金属屏障衬里和至少一种垫层级金属填充材料。可从包含第二垫层级电介质层790的顶部表面的水平平面上方移除垫层级金属屏障衬里和至少一种垫层级金属填充材料的多余部分。垫层级金属屏障衬里和至少一种垫层级金属填充材料的剩余部分包括第二金属接合垫798。
图2A-4B中示出的各种实施例可在适当修正下采用以在第二半导体裸片700中形成第二金属接合垫798。
参考图6,示出根据本公开的实施例的在形成第二金属接合垫798之后第二半导体裸片700的第一配置的区域。在此情况下,图2A-2E中所示的方法可用于形成第二金属接合垫798。每个第二金属接合垫798可包含第二金属屏障衬里72、第二垫基底部分74和第二腐蚀屏障层76。每个第二金属屏障衬里72可具有与任一第一金属屏障衬里92相同的材料组成且可具有与任一第一金属屏障衬里相同的厚度范围。每个第二垫基底部分74可具有与任一第一垫基底部分94相同的材料组成且可具有与任一第一垫基底部分相同的厚度范围。第二腐蚀屏障层76可具有与任一第一腐蚀屏障层96相同的材料组成且可具有与任一第一腐蚀屏障层相同的厚度范围。
参考图7,示出根据本公开的实施例的在形成第二金属接合垫798之后第二半导体裸片700的第二配置的区域。在此情况下,图3A和3B中所示的方法可用于形成第二金属接合垫798。每个第二金属接合垫798可包含第二金属屏障衬里72、第二垫基底部分74和第二腐蚀屏障层76。每个第二金属屏障衬里72可具有与任一第一金属屏障衬里92相同的材料组成且可具有与任一第一金属屏障衬里相同的厚度范围。每个第二垫基底部分74可具有与任一第一垫基底部分94相同的材料组成且可具有与任一第一垫基底部分相同的厚度范围。第二腐蚀屏障层76可具有与任一第一腐蚀屏障层96相同的材料组成且可具有与任一第一腐蚀屏障层相同的厚度范围。
参考图8,示出根据本公开的实施例的在形成第二金属接合垫798之后第二半导体裸片700的第三配置的区域。在此情况下,图4A和4B中所示的方法可用于形成第二金属接合垫798。每个第二金属接合垫798可包含第二金属屏障衬里72和第二腐蚀屏障层76。每个第二金属屏障衬里72可具有与任一第一金属屏障衬里92相同的材料组成且可具有与任一第一金属屏障衬里相同的厚度范围。每个第二腐蚀屏障层76可具有与任一第一腐蚀屏障层96相同的材料组成且可具有与任一第一腐蚀屏障层相同的厚度范围。
参考图9,第一半导体裸片900和第二半导体裸片700可通过晶片到晶片接合、裸片到晶片接合或裸片到裸片接合而彼此接合。例如,包含多个第一半导体裸片900的第一晶片和包含多个第二半导体裸片700的第二晶片可彼此对准,使得每个第一半导体裸片900的第一金属接合垫998面对对应的第二半导体裸片700的第二金属接合垫798。通常,每个第一半导体裸片900中的第一金属接合垫998的图案可以是第二金属接合垫798的镜像图案。
每对面对的第一金属接合垫998和第二金属接合垫798可对准以使其间的面积重叠达到最大。每对面对的第一半导体裸片900和第二半导体裸片700可彼此接触,使得每个第一金属接合垫998接触第二金属接合垫798中的相应一者且其间具有相应的面积重叠。第一半导体裸片900和第二半导体裸片700的组件在250摄氏度到400摄氏度范围内的高温下退火以引发跨各对面对的相应第一金属接合垫998与相应第二金属接合垫798之间的每个界面的金属扩散。在高温下退火过程的持续时间可在5分钟到2小时的范围内,但也可采用更短或更长的退火持续时间。每对面对的第一金属接合垫998和第二金属接合垫798在高温下的退火过程期间彼此接合。可形成包含第一半导体裸片900和第二半导体裸片700的接合组件。
图10A和10B是根据本公开的实施例的示例性接合组件的第一配置的区域的顺序竖直横截面图。
参考图10A,示出在退火过程之前第一半导体裸片900的第一配置和第二半导体裸片700的第一配置的接合组件。在第一金属接合垫998与第二金属接合垫798之间的每个界面处存在一对第一腐蚀屏障层96和第二腐蚀屏障层76。
参考图10B,示出在退火过程之后第一半导体裸片900的第一配置和第二半导体裸片700的第一配置的接合组件。在第一金属接合垫998与第二金属接合垫798之间的每个界面处的所述一对第一腐蚀屏障层96和第二腐蚀屏障层76的金属材料相互扩散以形成腐蚀屏障层98。每个第一金属接合垫998可包含相应腐蚀屏障层98的第一部分,且每个第二金属接合垫798可包含相应腐蚀屏障层98的第二部分。
图11A和11B是根据本公开的实施例的示例性接合组件的第二配置的区域的顺序竖直横截面图。
参考图11A,示出在退火过程之前第一半导体裸片900的第二配置和第二半导体裸片700的第二配置的接合组件。在第一金属接合垫998与第二金属接合垫798之间的每个界面处存在一对第一腐蚀屏障层96和第二腐蚀屏障层76。
参考图11B,示出在退火过程之后第一半导体裸片900的第二配置和第二半导体裸片700的第二配置的接合组件。在第一金属接合垫998与第二金属接合垫798之间的每个界面处的所述一对第一腐蚀屏障层96和第二腐蚀屏障层76的金属材料相互扩散以形成腐蚀屏障层98。每个第一金属接合垫998可包含相应腐蚀屏障层98的第一部分,且每个第二金属接合垫798可包含相应腐蚀屏障层98的第二部分。
参考图10B和11B,第一垫基底部分94和/或第二垫基底部分74可包含处于第一原子浓度的主接合金属,且腐蚀屏障层98可包含处于小于第一原子百分比的第二原子百分比的主接合金属。第一金属接合垫998中的每一者在热退火过程之后可具有竖直成分梯度,使得:主接合金属的原子百分比在第一金属接合垫998和第二金属接合垫798中的每一者内随着与水平平面的竖直距离增加,所述水平平面包含第一半导体裸片900与第二半导体裸片700之间的接合界面;且所述至少一种腐蚀抑制元素中的每一者的原子百分比在第一金属接合垫998和第二金属接合垫798中的每一者内随着与所述水平平面的竖直距离减小。
参考图12,示出在退火过程之后第一半导体裸片900的第三配置和第二半导体裸片700的第三配置的接合组件。一对第一腐蚀屏障层96和第二腐蚀屏障层76的金属合金材料在第一金属接合垫998与第二金属接合垫798之间相互扩散以提供金属到金属接合。
参考图13,可通过研磨、抛光、各向异性蚀刻或各向同性蚀刻而从背侧薄化第一衬底908。薄化过程可继续,直到移除贯穿衬底衬里386的水平部分被移除且贯穿衬底通孔结构388的水平表面物理上暴露为止。通常,贯穿衬底通孔结构388的端表面可通过薄化第一衬底908的背侧而物理上暴露,所述第一衬底可以是存储器裸片的衬底。薄化之后第一衬底908的厚度可在1微米到30微米的范围内,例如2微米到15微米,但也可采用更小和更大的厚度。
背侧绝缘层930可形成于第一衬底908的背侧。背侧绝缘层930包含例如氧化硅等绝缘材料。背侧绝缘层930的厚度可在从50nm到500nm的范围内,但也可采用较小和较大的厚度。光致抗蚀剂层(未示)可施加在背侧绝缘层930上方,且可经光刻图案化以在贯穿衬底通孔结构388的区域上方形成开口。可执行蚀刻过程以形成穿过光致抗蚀剂层中的每一开口下方的背侧绝缘层930的通孔腔。贯穿衬底通孔结构388的顶部表面可通过背侧绝缘层930物理上暴露于每个通孔腔的底部处。
可将至少一种金属材料沉积到穿过背侧绝缘层930的开口中和背侧绝缘层930的平坦表面上方以形成金属材料层。所述至少一种金属材料可包含铜、铝、钌、钴、钼和/或可通过物理气相沉积、化学气相沉积、电镀、真空蒸发或其它沉积方法沉积的任何其它金属材料。例如,金属氮化物衬里材料(例如,TiN、TaN或WN)可直接沉积在贯穿衬底通孔结构388的物理上暴露的表面上、穿过背侧绝缘层930的开口的侧壁上,以及在背侧绝缘层930的物理上暴露的平坦表面上。金属氮化物衬里材料的厚度可在从10nm到100nm的范围内,但也可采用较小和较大的厚度。至少一种金属填充材料(例如,铜或铝)可沉积在金属氮化物衬里材料上。在一个实施例中,所述至少一种金属填充材料可包含高导电性金属层(例如铜层或铝层)的堆叠和用于将焊球接合在其上的凸块下冶金(UBM)层堆叠。示例性UBM层堆叠包含但不限于Al/Ni/Au堆叠、Al/Ni/Cu堆叠、Cu/Ni/Au堆叠、Cu/Ni/Pd堆叠、Ti/Ni/Au堆叠、Ti/Cu/Ni/Au堆叠、Ti-W/Cu堆叠、Cr/Cu堆叠和Cr/Cu/Ni堆叠。在背侧绝缘层930的平坦水平表面上的金属材料层的厚度可在0.5微米到10微米的范围内,例如1微米到5微米,但也可采用更小和更大的厚度。
至少一种金属填充材料和金属材料层可随后经图案化以形成接触贯穿衬底通孔结构388中的相应一者的离散背侧接合垫936。背侧接合垫936可充当外部接合垫,其可用于将第一半导体裸片900和第二半导体裸片700内的各种节点电连接到外部节点,例如,封装衬底上的接合垫或另一半导体裸片的C4接合垫。例如,焊料材料部分938可形成于背侧接合垫936上,且可执行C4接合过程或线接合过程以将背侧接合垫936电连接到外部电活性节点。
参考所有附图且根据本公开的各种实施例,接合组件包含第一半导体裸片900和第二半导体裸片700。第一半导体裸片900包括嵌入于第一电介质材料层(960、962、990)中的第一金属接合垫998。第二半导体裸片700包括嵌入于第二电介质材料层(760、792、790)中的第二金属接合垫798。第一金属接合垫998在包含第一半导体裸片900与第二半导体裸片700之间的接合界面的水平平面内接合到第二金属接合垫798中的相应一者。第一金属接合垫998中的每一者包含腐蚀屏障层96,所述腐蚀屏障层含有主接合金属和不同于所述主接合金属的至少一种腐蚀抑制元素的合金。
在一个实施例中,所述主接合金属包括Cu,且所述至少一种腐蚀抑制元素包括Ni、B或P。在一个实施例中,合金包括50到95原子百分比的铜和10到50原子百分比的至少一种腐蚀抑制元素。在优选实施例中,所述至少一种腐蚀抑制元素包括Ni。
在一个实施例中,第一金属接合垫998中的每一者另外包括腐蚀屏障层96下方的主接合金属层94。在一个实施例中,主接合金属层包括纯铜或含有小于10原子百分比的至少一种腐蚀抑制元素的铜合金。
在替代实施例中,所述主接合金属包括Al,且所述至少一种腐蚀抑制元素包括Cu。
在一个实施例中,第一半导体裸片900另外包括存储器装置920,且第二半导体裸片700另外包括用于存储器装置920的操作的外围电路系统720。
通过采用Cu-Ni合金、Cu-Ni-P合金或Cu-Ni-B合金代替铜-铜接合中的界面区域处的纯Cu,或通过采用Al-Cu合金代替铝-铝接合中的界面区域处的纯Al,本公开的实施例的结构的各种配置为金属接合垫提供增强的耐腐蚀性。
不希望受特定理论所束缚,相信纯铜腐蚀可由CMP期间的电化学电势引起。由于电负性差异,O或F原子往往会在阴极半反应中从铜上剥离电子,而铜原子往往会在阳极半反应中释放电子并在腐蚀性CMP溶液中形成铜离子。阴极与阳极的面积比非常高。长金属线将充当将电荷集中到小铜岛的天线。相比之下,通过将例如镍的腐蚀抑制合金元素添加到铜接合垫中包含将镍结合到无源铜氧化物(例如,Cu2O)膜中,且以两种方式增加耐腐蚀性。首先,Ni2+离子占据Cu+离子的空位且增加离子阻力,这使得两个Cu+离子消失,且因此增加膜的离子阻力。第二,Ni2+离子直接代替Cu+离子,而离子阻力不改变,且每次取代引起一个Cu+离子的消失且增加电子阻力。
虽然前述内容参考了特定实施例,但应理解,本公开不限于此。本领域的一般技术人员将想到,可对公开的实施例作出各种修改且此类修改旨在处于本公开的范围内。假定并非彼此的替代方案的所有实施例当中存在兼容性。除非另外明确地陈述,否则词语“包括”或“包含”涵盖其中词语“基本上由…组成”或词语“由…组成”代替词语“包括”或“包含”的所有实施例。在本公开中示出使用特定结构和/或配置的实施例的情况下,应理解,可利用在功能上等同的任何其它兼容结构和/或配置实践本公开,前提是此类替代物并未被明确禁用或以其它方式被本领域的一般技术人员认为是不可能的。所有本文中引用的公开、专利申请以及专利以全文引用的方式并入本文中。
Claims (20)
1.一种形成半导体结构的方法,其包括:
提供第一半导体裸片,所述第一半导体裸片包含位于第一衬底上方的第一半导体装置且包含嵌入于第一电介质材料层中的第一金属互连结构;
在所述第一半导体裸片的前侧上形成垫腔,其中所述第一金属互连结构的子集的表面物理上暴露于所述垫腔的底部表面处;以及
在所述垫腔中形成第一金属接合垫,其中所述第一金属接合垫中的每一者包括腐蚀屏障层,所述腐蚀屏障层包括主接合金属与不同于所述主接合金属的至少一种腐蚀抑制元素的合金。
2.根据权利要求1所述的方法,其中:
所述主接合金属包括Cu;且
所述至少一种腐蚀抑制元素包括Ni、B或P。
3.根据权利要求2所述的方法,其中所述合金包括50到95原子百分比的铜和10到50原子百分比的所述至少一种腐蚀抑制元素。
4.根据权利要求3所述的方法,其中所述至少一种腐蚀抑制元素包括Ni。
5.根据权利要求3所述的方法,其另外包括在所述垫腔中沉积主接合金属层,随后在所述主接合金属层上方沉积所述腐蚀屏障层。
6.根据权利要求5所述的方法,其中所述主接合金属层包括纯铜或含有小于10原子百分比的所述至少一种腐蚀抑制元素的铜合金。
7.根据权利要求5所述的方法,其另外包括:
在沉积所述腐蚀屏障层的步骤之前,通过执行第一化学机械抛光(CMP)过程从包含所述第一电介质材料层的最顶部表面的水平平面上方移除所述主接合金属层的部分;
使位于所述垫腔内的所述主接合材料层的部分竖直凹入所述水平平面下方;以及
在沉积所述腐蚀屏障层的步骤之后,通过执行第二化学机械抛光(CMP)过程从包含所述第一电介质材料层的所述最顶部表面的所述水平平面上方移除所述腐蚀屏障层的部分。
8.根据权利要求5所述的方法,其另外包括通过执行化学机械抛光(CMP)过程从包含所述第一电介质材料层的最顶部表面的水平平面上方移除所述腐蚀屏障层和所述主接合金属层的部分,其中填充所述垫腔中的相应一者的剩余材料部分包括所述第一金属接合垫。
9.根据权利要求1所述的方法,其中所述腐蚀屏障层具有浓度随厚度而变化的所述至少一种腐蚀抑制元素。
10.根据权利要求1所述的方法,其中:
所述主接合金属包括Al;且
所述至少一种腐蚀抑制元素包括Cu。
11.根据权利要求1所述的方法,其另外包括:
提供第二半导体裸片,所述第二半导体裸片包含位于第二衬底上的第二半导体装置、嵌入于第二电介质材料层中的第二金属互连结构,以及电连接到所述第二金属互连结构中的相应一者且嵌入于所述第二电介质材料层当中的最顶部层中的第二金属接合垫;以及
通过执行热退火过程将所述第二金属接合垫与所述第一金属接合垫接合。
12.根据权利要求11所述的方法,其中:
所述第一半导体装置包括存储器装置;且
所述第二半导体装置包括用于所述存储器装置的操作的外围电路系统。
13.一种接合组件,其包括第一半导体裸片和第二半导体裸片,其中:
所述第一半导体裸片包括嵌入于第一电介质材料层中的第一金属接合垫;
所述第二半导体裸片包括嵌入于第二电介质材料层中的第二金属接合垫;
所述第一金属接合垫接合到所述第二金属接合垫中的相应一者;且
所述第一金属接合垫中的每一者包括腐蚀屏障层,所述腐蚀屏障层包括主接合金属与不同于所述主接合金属的至少一种腐蚀抑制元素的合金。
14.根据权利要求13所述的接合组件,其中:
所述主接合金属包括Cu;且
所述至少一种腐蚀抑制元素包括Ni、B或P。
15.根据权利要求14所述的接合组件,其中所述合金包括50到95原子百分比的铜和10到50原子百分比的所述至少一种腐蚀抑制元素。
16.根据权利要求15所述的接合组件,其中所述至少一种腐蚀抑制元素包括Ni。
17.根据权利要求15所述的接合组件,其中所述第一金属接合垫中的每一者另外包括所述腐蚀屏障层下方的主接合金属层。
18.根据权利要求17所述的接合组件,其中所述主接合金属层包括纯铜或含有小于10原子百分比的所述至少一种腐蚀抑制元素的铜合金。
19.根据权利要求13所述的接合组件,其中:
所述主接合金属包括Al;且
所述至少一种腐蚀抑制元素包括Cu。
20.根据权利要求13所述的接合组件,其中:
所述第一半导体裸片另外包括存储器装置;且
所述第二半导体裸片另外包括用于所述存储器装置的操作的外围电路系统。
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