CN116781180B

CN116781180B - PCM channel capacity expansion method and capacity expansion system

Info

Publication number: CN116781180B
Application number: CN202310654401.8A
Authority: CN
Inventors: 郑煌盛; 熊国辉; 黄兴浩; 杜强
Original assignee: Guangzhou Gaoke Communications Technology Co ltd
Current assignee: Guangzhou Gaoke Communications Technology Co ltd
Priority date: 2023-06-05
Filing date: 2023-06-05
Publication date: 2023-11-10
Anticipated expiration: 2043-06-05
Also published as: CN116781180A

Abstract

The embodiment of the invention relates to the technical field of communication, and discloses a PCM channel capacity expansion method and a capacity expansion system, wherein the method comprises the following steps: filling sampling data in the same clock cycle in the FPGA equipment into a PCM waveform according to a sampling mode of a designated sampling frequency; wherein the PCM waveform carries a plurality of channel data; sequentially and uniformly distributing channel data according to the number of the data cache areas to obtain a plurality of data strings; and sequentially storing the data strings into the data buffer area through corresponding receiving channels according to a specified transmission rule. By implementing the embodiment of the invention, the aim of expanding the capacity of the PCM channel can be fulfilled, so that the data transmission efficiency is effectively improved.

Description

PCM channel capacity expansion method and capacity expansion system

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a PCM channel capacity expansion method and a capacity expansion system.

Background

Currently, a PCM module is provided in a chip of the MT7621 scheme based on the MTK manufacturer, which can perform processing of receiving and transmitting voice data through a PCM carrier signal.

However, in practice, we find that by using the chip manual of the PCM module, we can obtain 1024 bit data in one clock cycle. In PCM encoding format, each data occupies 16 bits, and because of the limitation of the sampling frequency of 8 KHz, the PCM module can only fill 4 channels of data, that is, 4×16bit=64bit, resulting in waste of 1024-64=960 bit data bits. Moreover, since the PCM module only has 4 fifo buffers with a size of 32 Byte, and the order of reading and writing data in the four buffers is controlled by the CPU, it cannot be done manually, which results in that the order of channel data cannot be determined when we acquire the channel data.

Disclosure of Invention

The embodiment of the invention discloses a PCM channel capacity expansion method and a capacity expansion system, which can realize the aim of expanding the capacity of a PCM channel so as to effectively improve the data transmission efficiency.

The first aspect of the embodiment of the invention discloses a PCM channel capacity expansion method, which comprises the following steps:

filling sampling data in the same clock cycle in the FPGA equipment into a PCM waveform according to a sampling mode of a designated sampling frequency; wherein the PCM waveform carries a plurality of channel data;

the channel data are sequentially and uniformly distributed according to the number of the data cache areas so as to obtain a plurality of data strings;

and storing the data strings into the data buffer area through corresponding receiving channels according to a specified transmission rule.

As another optional implementation manner, in the first aspect of the embodiment of the present invention, before the sampling data in the FPGA device in the same clock cycle is filled into the PCM waveform in the sampling manner with the specified sampling frequency, the method further includes:

and increasing the initial sampling frequency of the FPGA equipment by adopting an external synchronous clock mode so as to obtain the appointed sampling frequency.

As another optional implementation manner, in the first aspect of the embodiment of the present invention, after the storing, by a specified transmission rule, the plurality of data strings in the data buffer area through corresponding receiving channels in sequence, the method further includes:

And when receiving a data output instruction, outputting the appointed data strings in the same appointed clock period in the data buffer area through corresponding transmission channels respectively.

As another optional implementation manner, in the first aspect of the embodiment of the present invention, before the increasing the initial sampling frequency of the FPGA device by using an external synchronous clock to obtain the specified sampling frequency, the method further includes:

detecting whether the position information of the receiving channel is in an unknown state; if yes, sequentially and uniformly distributing the first positioning test data according to the number of the data cache areas to obtain a plurality of positioning test data strings;

disassembling each positioning test data string into a plurality of positioning test data string groups; wherein, one of the positioning test data string packets contains N transmission data, and N is the maximum transmission number which can be received by the data buffer area when receiving the data each time;

transmitting a plurality of positioning test data string packets in sequence according to the appointed transmission rule;

and determining the position information of each receiving channel according to the data content received by each receiving channel.

As another optional implementation manner, in the first aspect of the embodiment of the present invention, after determining the location information of each receiving channel according to the data content received by each receiving channel and before increasing the initial sampling frequency of the FPGA device by using an external synchronization clock to obtain the specified sampling frequency, the method further includes:

detecting whether the position information of the sending channel is in an unknown state; if yes, outputting the second positioning test data in the data buffer area one by one;

and determining the position information of each sending channel according to the data content output by each sending channel.

A second aspect of the embodiment of the present invention discloses a capacity expansion system, which includes:

the filling unit is used for filling sampling data in the same clock period in the FPGA equipment into the PCM waveform according to a sampling mode of a designated sampling frequency; wherein the PCM waveform carries a plurality of channel data;

the distribution unit is used for sequentially and uniformly distributing the channel data according to the number of the data cache areas so as to obtain a plurality of data strings;

And the storage unit is used for sequentially storing the plurality of data strings into the data buffer area through corresponding receiving channels according to a specified transmission rule.

As another optional implementation manner, in the second aspect of the embodiment of the present invention, the capacity expansion system further includes:

the frequency increasing unit is used for increasing the initial sampling frequency of the FPGA equipment by adopting an external synchronous clock mode before the sampling data in the same clock period in the FPGA equipment are filled in the PCM waveform according to the sampling mode of the specified sampling frequency so as to obtain the specified sampling frequency.

and the first output unit is used for respectively outputting the specified data strings in the same specified clock period in the data buffer area through the corresponding sending channels when receiving the data output instruction after the storage unit stores the data strings into the data buffer area through the corresponding receiving channels according to the specified transmission rule.

As another optional implementation manner, in the second aspect of the embodiment of the present invention, the capacity expansion system includes:

The first detection unit is used for improving the initial sampling frequency of the FPGA equipment in a mode of externally connecting a synchronous clock so as to detect whether the position information of the receiving channel is in an unknown state before the appointed sampling frequency is obtained;

the distribution unit is further configured to uniformly distribute first positioning test data in sequence according to the number of the data buffer areas when the first detection unit detects that the position information of the receiving channel is in an unknown state, so as to obtain a plurality of positioning test data strings;

a disassembling unit, configured to disassemble each of the positioning test data strings into a plurality of positioning test data string packets; wherein, one of the positioning test data string packets contains N transmission data, and N is the maximum transmission number which can be received by the data buffer area when receiving the data each time;

the transmission unit is used for sequentially transmitting a plurality of positioning test data string packets according to the appointed transmission rule;

and the first determining unit is used for determining the position information of each receiving channel according to the data content received by each receiving channel.

A third aspect of the embodiment of the present invention discloses a capacity expansion system, which includes:

a memory storing executable program code;

a processor coupled to the memory;

the processor calls the executable program code stored in the memory to execute the PCM channel capacity expansion method disclosed in the first aspect of the embodiment of the present invention.

A fourth aspect of the embodiments of the present invention discloses a computer-readable storage medium storing a computer program, wherein the computer program causes a computer to execute a PCM channel capacity expansion method disclosed in the first aspect of the embodiments of the present invention.

A fifth aspect of the embodiments of the present invention discloses a computer program product which, when run on a computer, causes the computer to perform part or all of the steps of any one of the PCM channel expansion methods of the first aspect.

A sixth aspect of the embodiments of the present invention discloses an application publishing platform for publishing a computer program product, wherein the computer program product, when run on a computer, causes the computer to perform part or all of the steps of any one of the PCM channel capacity expansion methods of the first aspect.

Compared with the prior art, the embodiment of the invention has the following beneficial effects:

according to the embodiment of the invention, sampling data in the same clock period in the FPGA equipment are filled into the PCM waveform according to a sampling mode of a designated sampling frequency; wherein the PCM waveform carries a plurality of channel data; the channel data are sequentially and uniformly distributed according to the number of the data cache areas so as to obtain a plurality of data strings; and storing the data strings into the data buffer area through corresponding receiving channels according to a specified transmission rule. Therefore, the embodiment of the invention can realize the aim of expanding the PCM channel so as to effectively improve the data transmission efficiency.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic flow chart of a PCM channel capacity expansion method according to an embodiment of the present invention;

FIG. 2 is a flow chart of another PCM channel expansion method according to an embodiment of the invention;

fig. 3 is a schematic structural diagram of a capacity expansion system according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of another capacity expansion system according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of another capacity expansion system according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that the terms "first," "second," "third," "fourth," and the like in the description and in the claims of the present invention are used for distinguishing between different objects and not necessarily for describing a particular sequential or chronological order. The terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or apparatus.

The embodiment of the application discloses a PCM channel capacity expansion method and a capacity expansion system, which can realize the aim of expanding the capacity of a PCM channel so as to effectively improve the data transmission efficiency.

The following detailed description refers to the accompanying drawings.

Example 1

Referring to fig. 1, fig. 1 is a flow chart of a PCM channel capacity expansion method according to an embodiment of the application. As shown in fig. 1, the PCM channel capacity expansion method may include the following steps.

101. The capacity expansion system fills sampling data in the same clock period in the FPGA equipment into the PCM waveform according to a sampling mode of a designated sampling frequency; wherein the PCM waveform carries a plurality of channel data.

As an alternative implementation manner, in the embodiment of the present application, the system may obtain 1024 bit data in one clock cycle through chip manual calculation. Under the PCM coding format, each data occupies 16 bits, because of the limitation of sampling frequency 8 KHz, the PCM module can only fill 4 channels of data, namely 4 x 16 bits = 64 bits, resulting in 1024-64 = 960 bits of data waste, in order to be able to use the 960 bits of data, the application can adopt the method of externally connecting synchronous clock, the sampling frequency is forced to be increased to 128 KHz, in order to realize the transmission of voice data of 64 channels by totally using 1024 bits of data, the result is expanded by 16 times than before.

As an alternative implementation manner, in the embodiment of the application, because the standard sampling frequency of the PCM voice protocol is 8 KHz, only 4 channels of data can be acquired in the standard sampling frequency period, and the sampling frequency is increased for a plurality of times, an FPGA chip is introduced to be used for filling the standard 8 KHz sampling data into the PCM waveform according to a 128 KHz sampling mode when the external voice data and the PCM module are in butt joint, and the voice data of other channels are also filled into the PCM waveform together, so that the PCM waveform carrying 64 channels of data is formed.

As an alternative implementation manner, in the embodiment of the application, the FPGA chip has more preferential price compared with the traditional CPU chip, and has more purchase channels, so that the cost of the FPGA chip can be reduced while the capacity expansion of the PCM channel is realized.

102. The capacity expansion system sequentially and uniformly distributes channel data according to the number of the data cache areas so as to obtain a plurality of data strings.

As an alternative implementation manner, in the embodiment of the present application, since the PCM module only has 4 FIFO buffers with a size of 32 bytes, i.e. data buffers, we need to divide the data of 64 channels into 4 parts and equally divide the data into 4 buffers for buffering, i.e. in the present application, step 102, the channel data is sequentially and evenly distributed according to the number of data buffers, so as to obtain a plurality of data strings, so that the CPU can conveniently transport the data to the physical memory for storage through DMA when idle.

103. And the capacity expansion system sequentially stores the plurality of data strings into the data buffer area through corresponding receiving channels according to a specified transmission rule.

As an alternative implementation manner, in the embodiment of the present application, since each data buffer area can only receive data of one channel at a time before the PCM channel is expanded, and 16 channels of data can now be received in each data buffer area at a time, the system is required to extract the data and buffer the data in other spaces, and the data is not sent to the dsp for processing until the 160 Byte data required by PCM speech is collected.

In the embodiment of the application, a plurality of SLIC modules for collecting voice data can be connected to the FPGA chip through the SPI interface, and the data collected by the SLIC chips are converted into digital data through the FPGA chip to be transmitted out so as to perform unified management of the data, so that the plurality of SLIC chips share FS (synchronous clock signal) and CLK (periodic clock), and the synchronism of the data can be ensured. The sampling frequency of one SLIC module is 8 KHz, 160 Byte data can be sent within 20ms of each SLIC module, and one FPGA chip can theoretically support 64 SLIC modules;

in addition, the PCM module is connected with the FPGA chip through the SPI interface, and the sampling frequency output by the FPGA chip is 128 KHz at the moment, and the clock period is 8 MHz. The FPGA chip can integrate and segment the data of a plurality of SLICs to be sent to the PCM module for a plurality of times, so that the PCM module can receive 160 Byte data of 64 channels in 20 ms;

In addition, due to the fact that the sampling frequency is accelerated, the PCM module receives voice data transmitted by the FPGA 16 times within 20ms, each channel receives 10 bytes of data each time, and the data needs to be placed in a data buffer area until 160 bytes are received and then sent to a DSP chip for driving processing.

As an alternative implementation, in the previous operation in the embodiment of the present application, the sampling frequency of PCM is 8Khz normally, and since there are only four FIFO buffers, only 4 channels of data can be transferred in one data transmission, and thus the FIFO buffers can only receive 160 bytes of data within 20 ms. The sampling frequency is modified to 128 KHZ, so that the times of the FPGA chip transmitted to the FIFO buffer area are increased, the FIFO buffer area can receive more data within 20ms, and further under the same chip, 64 paths of calls can be supported, which is 4 paths before, the number of times of the sampling frequency is directly increased, the use of 16 CPU chips is reduced, and the cost is greatly reduced.

As an alternative implementation manner, in the embodiment of the present application, since the PCM module is configured with 4 FIFOs as a buffer space for receiving data, and each FIFO buffer is provided with a DMA connected to a physical memory as a storage space for data, the entire PCM module can support 4 voice channels, and if PCM data is encoded and decoded by using an a-rate or u-rate codec, the PCM data can be reduced by half. The PCM module under the MT7621 scheme is able to process voice data of 8 channels. We also take this scheme as our voice scheme for voice data transfer. Point-to-point voice communication is implemented.

In the PCM channel capacity expansion method of fig. 1, a capacity expansion system is described as an example of an execution body. It should be noted that, the execution body of the PCM channel capacity expansion method of fig. 1 may also be a stand-alone device associated with the capacity expansion system, which is not limited by the embodiment of the present application.

Therefore, implementing the PCM channel capacity expansion method described in fig. 1 can achieve the purpose of PCM channel capacity expansion, so as to effectively improve the data transmission efficiency.

In addition, implementing a PCM channel expansion method as described in fig. 1 can reduce the cost while realizing PCM channel expansion.

Example two

Referring to fig. 2, fig. 2 is a flow chart of another PCM channel expansion method according to the embodiment of the application. As shown in fig. 2, the PCM channel capacity expansion method may include the steps of:

201. the capacity expansion system detects whether the position information of the receiving channel is in an unknown state, if so, step 202 to step 206 are executed, and if not, step 206 is executed.

In the embodiment of the present application, the data buffer area of the present application may include 4, that is, 4 FIFO buffers, and since the plurality of channel data is transmitted through the 4 FIFO buffers in multiple combinations, the receiving order of the data in the 4 FIFO buffers cannot be determined every time it is started, and the receiving order cannot be fixed until the subsequent stable operation. So that the data between FIFO buffers is biased, when we fetch the data from FIFO buffers and combine them into data, we need to locate the running order and position of each FIFO buffer in the current situation when running.

In the embodiment of the application, a total of 16 channel numbers are contained in one FIFO buffer area, the FPGA equipment can only occupy 4 channel numbers for transmission at each transmission, the data transmission is regular, and the PCM equipment can obtain the whole string of data transmitted by the FPGA equipment through repeated data reception in the same time period.

202. And the capacity expansion system sequentially and uniformly distributes the first positioning test data according to the number of the data cache areas so as to obtain a plurality of positioning test data strings.

203. The capacity expansion system disassembles each positioning test data string into a plurality of positioning test data string groups; wherein, a positioning test data string packet contains N transmission data, N is the maximum transmission number which can be received by the data buffer area when receiving data each time.

204. And the capacity expansion system sequentially transmits the plurality of positioning test data string packets according to a designated transmission rule.

205. And the capacity expansion system determines the position information of each receiving channel according to the data content received by each receiving channel.

In the embodiment of the application, since the PCM module only has 4 FIFO buffers with the size of 32 Byte, the data of 64 channels needs to be sequentially and uniformly distributed into 4 parts according to the number of data buffers, so as to be uniformly distributed into 4 buffers for buffering, the CPU conveniently transfers the data to a physical memory for storage through DMA when in idle, the sequence of reading and writing the data of the four buffers is controlled by the CPU, and the CPU cannot be used for drying, which results in that the sequence of the channel data cannot be determined when the system acquires the channel data, therefore, the application also needs to perform positioning operation on the data of each channel to prevent the channel data from generating offset.

In the embodiment of the present invention, the 16 serial number channels in each FIFO buffer are not orderly arranged, even if the serial number of the channel is not marked from the beginning, the position information of the receiving channel is in an unknown state, but because the data is orderly and known to be transmitted, and therefore, during the data transmission, the system can identify which serial number data the receiving channel is responsible for receiving according to the character content received by the receiving channel, so as to determine the serial number of the receiving channel and the position where the receiving channel is located.

As an alternative implementation manner, in the embodiment of the present invention, when the FPGA device starts to transmit data from the start and starts to transmit 4-bit data from 0 to 0123, but the PCM device does not start to receive the data at this time, the data that the FPGA device may transmit to is 12, 13, 14, 15 when the PCM device starts to receive the data, and if the location information of the received channel is not located at this time, the system cannot predict where the specific storage location of the data is, and further, when the channel data is acquired, the sequence of the channel data cannot be determined.

206. The capacity expansion system detects whether the position information of the sending channel is in an unknown state, if so, step 207 to step 213 are executed, and if not, step 209 to step 213 are executed.

207. And the capacity expansion system outputs the second positioning test data in the data buffer area one by one.

208. And the capacity expansion system determines the position information of each sending channel according to the data content output by each sending channel.

In an embodiment of the present application, after determining the position information of the receiving channel, the system may sequentially extract the data from the data buffer, but since the position information of the receiving channel and the position information of the transmitting channel are designed independently, after the system sequentially extracts the data in the data buffer, the sequence of the channel data cannot be determined because the position information of the transmitting channel cannot be determined, which may further result in that the system may not be able to determine the sequence of the channel data when acquiring the channel data.

As an alternative implementation manner, in the embodiment of the present application, the location information of the sending channels of the present application may be confirmed one by occupying data, for example, only one data may be sent in one data transmission of the PCM module, when the PCM module sends the data 0, we can see which channel the data 0 is output through, and then determine which serial number data is responsible for sending the channel outputting the data 0, so as to determine the serial number of the sending channel and the location where the channel is located; and so on until the location information of all the transmission channels is confirmed.

As an optional implementation manner, in the embodiment of the present application, regarding the positioning operation of the receiving channel and the sending channel, the present application may also perform annular connection between the PCM module and the FPGA module first, so that the PCM module can receive the data sent by the FPGA module according to the 128 KHz frequency, by writing 0x0001 in the first bit, writing 0x0203 in the second bit, and so on, where the last bit is 0x7e7f. The PCM module records the data written with the positioning value, calculates the first bit value of each FIFO buffer area in the current period time, calculates the data offset of the transmission channel of the current FIFO buffer through subtraction calculation, thus positioning the position information of the PCM receiving end, transmitting the same data to the FPGA module through the transmitting end of the PCM module, adjusting the direction of the data transmitted by the FPGA module, transmitting the received data back to the PCM module, calculating the offset value of the data transmitted by the PCM through calculation, and modifying the connection mode between the FPGA logic and the PCM module through related software to enable the FPGA to connect the PCM module and the external voice module. The voice transmitted data can determine the channel number according to the offset value, and can send the data to the correct channel according to the offset value.

209. The capacity expansion system adopts an external synchronous clock mode to increase the initial sampling frequency of the FPGA equipment so as to obtain the designated sampling frequency.

In the embodiment of the application, a plurality of SLIC modules for collecting voice data can be connected to the FPGA chip through the SPI interface, and the data collected by the SLIC chips are converted into digital data through the FPGA chip to be transmitted out so as to perform unified management of the data, so that the plurality of SLIC chips share FS (synchronous clock signal) and CLK (periodic clock), and the synchronism of the data can be ensured. Wherein, the sampling frequency of one SLIC module is 8 KHz, 160 Byte data will be sent within 20ms of each SLIC module, and an FPGA chip can theoretically support 64 SLIC modules.

210. And the capacity expansion system fills sampling data in the same clock period in the FPGA equipment into the PCM waveform according to a sampling mode with a specified sampling frequency.

211. The capacity expansion system sequentially and uniformly distributes channel data according to the number of the data cache areas so as to obtain a plurality of data strings.

212. And the capacity expansion system sequentially stores the plurality of data strings into the data buffer area through corresponding receiving channels according to a specified transmission rule.

213. When receiving the data output instruction, the capacity expansion system outputs the appointed data strings in the same appointed clock period in the data buffer area through the corresponding transmission channels.

Therefore, another PCM channel expansion method described in fig. 2 can be implemented to achieve the purpose of PCM channel expansion, so as to effectively improve the data transmission efficiency

In addition, implementing another PCM channel expansion method described in fig. 2 enables a positioning operation for each channel to prevent the channel data from being shifted.

Example III

Referring to fig. 3, fig. 3 is a schematic structural diagram of a capacity expansion system according to an embodiment of the invention. As shown in fig. 3, the capacity expansion system 300 may include a filling unit 301, a distributing unit 302, and a storing unit 303, wherein:

A filling unit 301, configured to fill sampling data in the same clock cycle in the FPGA device into the PCM waveform according to a sampling manner with a specified sampling frequency; wherein the PCM waveform carries a plurality of channel data.

An allocation unit 302, configured to sequentially and uniformly allocate channel data according to the number of data buffers, so as to obtain a plurality of data strings.

The storage unit 303 is configured to store the plurality of data strings into the data buffer area sequentially through corresponding receiving channels according to a specified transmission rule.

As an alternative implementation manner, in the embodiment of the present application, since the standard sampling frequency of the PCM voice protocol is 8 KHz, only 4 channels of data can be obtained in the standard sampling frequency period, and the sampling frequency is increased by multiple times, so that the present application introduces an FPGA chip for interfacing external voice data with the PCM module, the filling unit 301 may fill the standard 8 KHz sampling data into the PCM waveform in a 128 KHz sampling manner, and fill the voice data of other channels into the PCM waveform together, so as to form a PCM waveform carrying 64 channels of data.

As an alternative implementation manner, in the embodiment of the present application, since the PCM module only has 4 FIFO buffers with a size of 32 bytes, that is, data buffers, the allocation unit 302 needs to divide the data of 64 channels into 4 parts and equally divide the data into 4 buffers for buffering, that is, the allocation unit 302 of the present application evenly allocates the channel data sequentially according to the number of data buffers, so as to obtain a plurality of data strings, so that the CPU can conveniently transport the data to the physical memory for storage through DMA when idle.

As an alternative implementation manner, in the embodiment of the present application, since each data buffer area can only receive data of one channel at a time before the PCM channel is expanded, and 16 channels of data can now be received in each data buffer area at a time, the storage unit 303 is required to extract the data and buffer the data in other spaces, and the data is not sent to the dsp for processing until the 160 Byte data required by PCM speech is collected.

Therefore, the capacity expansion system described in fig. 3 can realize the purpose of expanding the PCM channel, so as to effectively improve the data transmission efficiency.

In addition, implementing the expansion system described in fig. 3 can reduce the cost of the PCM channel while achieving expansion.

Example IV

Referring to fig. 4, fig. 4 is a schematic structural diagram of another capacity expansion system according to an embodiment of the present invention. The capacity expansion system of fig. 4 is optimized by the capacity expansion system of fig. 3. In comparison with the capacity expansion system of fig. 3, the capacity expansion system of fig. 4 further includes:

the frequency raising unit 304 is configured to raise the initial sampling frequency of the FPGA device by using an external synchronous clock before the filling unit 301 fills the sampling data in the same clock cycle in the PCM waveform according to the sampling mode of the specified sampling frequency, so as to obtain the specified sampling frequency.

As an alternative implementation manner, in the embodiment of the present invention, the system may obtain 1024 bit data in one clock cycle through chip manual calculation. Under the PCM coding format, each data occupies 16 bits, because of the limitation of the sampling frequency of 8 KHz, the PCM module can only fill 4 channels of data, namely, 4×16bit=64 bits, resulting in waste of 1024-64=960 bits of data bits, in order to be able to use the upper 960 bits of data bits, the frequency raising unit 304 can adopt a method of externally connecting a synchronous clock, so as to raise the sampling frequency to 128 KHz forcedly, thereby realizing transmission of voice data of 64 channels by 1024 Bit data bits, and the result is enlarged by 16 times compared with the previous result.

In comparison with the capacity expansion system of fig. 3, the capacity expansion system of fig. 4 further includes:

the first output unit 305 is configured to store, by the storage unit 303, a plurality of data strings sequentially through corresponding receiving channels according to a specified transmission rule into the data buffer, and when receiving a data output instruction, output, by the storage unit 303, the specified data strings in the data buffer in a specified same clock period through corresponding transmitting channels, respectively.

In comparison with the capacity expansion system of fig. 3, the capacity expansion system of fig. 4 includes:

the first detecting unit 306 is configured to detect whether the position information of the receiving channel is in an unknown state before the frequency increasing unit 304 increases the initial sampling frequency of the FPGA device by adopting a mode of externally connecting a synchronous clock to obtain the specified sampling frequency.

As another optional implementation manner, in this embodiment of the present application, when the first detecting unit 306 detects that the position information of the receiving channel is in an unknown state, the allocating unit 302 is further configured to sequentially and uniformly allocate the first positioning test data according to the number of data buffers, so as to obtain a plurality of positioning test data strings.

A disassembling unit 307, configured to disassemble each positioning test data string into a plurality of positioning test data string packets; wherein, a positioning test data string packet contains N transmission data, N is the maximum transmission number which can be received by the data buffer area when receiving data each time.

The transmission unit 308 is configured to sequentially transmit the plurality of positioning test data string packets according to a specified transmission rule.

A first determining unit 309 is configured to determine the location information of each receiving channel according to the data content received by each receiving channel.

In the embodiment of the present application, since the PCM module has only 4 FIFO buffers with a size of 32 Byte, the allocation unit 302 needs to sequentially and uniformly allocate the data of 64 channels into 4 copies according to the number of data buffers, so as to uniformly allocate the data into the 4 buffers for caching, so that the CPU can conveniently transport the data to the physical memory for storage through DMA when the CPU is idle, and the sequence of reading and writing the data of the four buffers is controlled by the CPU and cannot be manually dried, which results in that the sequence of channel data cannot be determined when the system acquires the channel data.

In the embodiment of the present invention, the 16 serial number channels in each FIFO buffer are not orderly arranged, and even the serial number of the channel is not marked from the beginning, at this time, the location information of the receiving channel is in an unknown state, but because the data is orderly and known to be transmitted, and thus, during the data transmission, the first determining unit 309 can identify which serial number data the receiving channel is responsible for receiving according to the character content received by the receiving channel, so as to determine the serial number of the receiving channel and the location where the channel is located.

the second detecting unit 310 is configured to detect whether the position information of the transmitting channel is in an unknown state after the first determining unit 309 determines the position information of each receiving channel according to the data content received by each receiving channel, and before the frequency raising unit 304 raises the initial sampling frequency of the FPGA device by adopting a mode of externally connecting a synchronous clock to obtain the specified sampling frequency.

The second output unit 311 is configured to output the second positioning test data in the data buffer one by one when the second detection unit 310 detects that the position information of the transmission channel is in an unknown state.

The second determining unit 312 is configured to determine the location information of each transmission channel according to the data content output by each transmission channel.

As an alternative implementation manner, in the embodiment of the present invention, after the first determining unit 309 determines the location information of the receiving channel, the first output unit 305 may sequentially extract the data from the data buffer, but since the location information of the receiving channel and the location information of the transmitting channel are designed independently, after the first output unit 305 sequentially extracts the data in the data buffer, the location information of the transmitting channel cannot be determined, which may result in that the order of the channel data cannot be determined when the first output unit 305 acquires the channel data.

Therefore, another capacity expansion system described in fig. 4 can be implemented to achieve the purpose of expanding the PCM channel, so as to effectively improve the data transmission efficiency.

In addition, implementing the alternative expansion system depicted in fig. 4, a positioning operation can be performed for each channel to prevent the channel data from being shifted.

Example five

Referring to fig. 5, fig. 5 is a schematic structural diagram of another capacity expansion system according to an embodiment of the present invention. As shown in fig. 5, the capacity expansion system may include:

a memory 501 in which executable program codes are stored;

a processor 502 coupled to the memory 501;

the processor 502 invokes executable program codes stored in the memory 501 to execute any PCM channel expansion method of fig. 1-2.

The embodiment of the invention discloses a computer readable storage medium which stores a computer program, wherein the computer program enables a computer to execute a PCM channel expansion method shown in any one of figures 1-2.

The embodiments of the present invention also disclose a computer program product, wherein the computer program product, when run on a computer, causes the computer to perform some or all of the steps of the method as in the method embodiments above.

Those of ordinary skill in the art will appreciate that all or part of the steps of the various methods of the above embodiments may be implemented by hardware associated with a program that may be stored in a computer-readable storage medium, including Read-Only Memory (ROM), random-access Memory (Random Access Memory, RAM), programmable Read-Only Memory (Programmable Read-Only Memory, PROM), erasable programmable Read-Only Memory (Erasable Programmable Read Only Memory, EPROM), one-time programmable Read-Only Memory (OTPROM), electrically erasable programmable Read-Only Memory (EEPROM), compact disc Read-Only Memory (Compact Disc Read-Only Memory, CD-ROM), or other optical disk Memory, magnetic disk Memory, tape Memory, or any other medium that can be used to carry or store data that is readable by a computer.

The PCM channel capacity expansion method and system disclosed in the embodiments of the present invention are described in detail, and specific examples are applied to illustrate the principles and embodiments of the present invention, and the description of the above examples is only used to help understand the method and core idea of the present invention; meanwhile, as those skilled in the art will vary in the specific embodiments and application scope according to the idea of the present invention, the present disclosure should not be construed as limiting the present invention in summary.

Claims

1. A PCM channel expansion method, comprising:

sequentially storing a plurality of data strings into the data buffer area through corresponding receiving channels according to a designated transmission rule;

before the sampling data in the same clock cycle in the FPGA equipment is filled into the PCM waveform according to the sampling mode of the appointed sampling frequency, the method further comprises the following steps:

The initial sampling frequency of the FPGA equipment is increased in a mode of externally connecting a synchronous clock so as to obtain the appointed sampling frequency;

the method further comprises the steps of:

2. The method according to claim 1, wherein after the plurality of data strings are sequentially stored in the data buffer through corresponding receiving channels according to a specified transmission rule, the method further comprises:

3. The method according to claim 1, wherein after determining the location information of each of the receiving channels according to the received data content of each of the receiving channels and before increasing the initial sampling frequency of the FPGA device by using an external synchronous clock to obtain the specified sampling frequency, the method further comprises:

4. A capacity expansion system, the capacity expansion system comprising:

the storage unit is used for sequentially storing the data strings into the data cache area through corresponding receiving channels according to a specified transmission rule;

the capacity expansion system further includes:

the frequency increasing unit is used for increasing the initial sampling frequency of the FPGA equipment by adopting an external synchronous clock mode before the sampling data in the same clock period in the FPGA equipment are filled in the PCM waveform according to the sampling mode of the appointed sampling frequency so as to obtain the appointed sampling frequency;

the capacity expansion system comprises:

5. The expansion system of claim 4, further comprising:

6. A capacity expansion system, the capacity expansion system comprising:

a memory storing executable program code;

A processor coupled to the memory;

the processor invokes the executable program code stored in the memory to perform the PCM channel expansion method of any of claims 1-3.