CN116779589A - 封装器件及其制作方法 - Google Patents

封装器件及其制作方法 Download PDF

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Publication number
CN116779589A
CN116779589A CN202210339615.1A CN202210339615A CN116779589A CN 116779589 A CN116779589 A CN 116779589A CN 202210339615 A CN202210339615 A CN 202210339615A CN 116779589 A CN116779589 A CN 116779589A
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China
Prior art keywords
layer
bridge chip
photosensitive
chip
substrate
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CN202210339615.1A
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English (en)
Inventor
张简上煜
林南君
徐宏欣
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Powertech Technology Inc
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Powertech Technology Inc
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Publication of CN116779589A publication Critical patent/CN116779589A/zh
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Abstract

本发明提供了一种封装器件及其制作方法。封装器件包括基板、多个导电柱、至少一桥接芯片、感光封装层、重布线层以及至少两个主动芯片。导电柱与桥接芯片设置于基板上，且感光封装层围绕桥接芯片以及导电柱，其中桥接芯片的上表面与感光封装层的上表面之间的间距小于导电柱中的一个的上表面与感光封装层的上表面之间的间距。重布线层设置于感光封装层上，主动芯片设置于重布线层上，且桥接芯片耦接于主动芯片之间。本发明可提升信号传输效率，保护桥接芯片，降低桥接芯片的破裂或断线，降低制作成本。

Description

封装器件及其制作方法
技术领域
本发明有关于一种封装器件及其制作方法，特别是一种利用桥接芯片耦接主动芯片的封装器件及其制作方法。
背景技术
近年来，为了整合各种功能，以满足使用需求，已发展出将多个主动芯片密封在同一个封装器件中。然而，随着主动芯片的功能越多或运算能力越高，对耦接主动芯片之间的互连(interconnection)结构的效率需求也越高。有鉴于此，如何提升主动芯片之间的互连效率并降低封装器件的制作成本以及工艺复杂度实为业界的一大课题。
发明内容
根据本发明的一实施例，提供一种封装器件，其包括基板、多个导电柱、至少一个桥接芯片、感光封装层、重布线层(redistribution layer)、至少两个主动芯片以及封装体。导电柱并排设置于基板上。桥接芯片设置于基板上。感光封装层围绕桥接芯片以及导电柱，其中桥接芯片的上表面与感光封装层的上表面之间的间距小于导电柱中的一个的上表面与感光封装层的上表面之间的间距。重布线层设置于感光封装层上。主动芯片设置于重布线层上，且桥接芯片耦接于主动芯片之间。封装体设置于重布线层上，并围绕主动芯片。
根据本发明的另一实施例，提供一种封装器件的制作方法。首先，于衬底上形成多个导电柱并设置至少一个桥接芯片。然后，于导电柱与桥接芯片上形成感光封装层，其中感光封装层围绕桥接芯片以及导电柱，且桥接芯片的上表面与感光封装层的上表面之间的间距小于导电柱中的一个的上表面与感光封装层的上表面之间的间距。接着，于感光封装层上形成重布线层。随后，于重布线层上设置至少两个主动芯片，并于重布线层上形成封装体，其中封装体围绕主动芯片。接着，移除衬底。
在本发明的封装器件中，通过桥接芯片耦接不同的主动芯片，可提升主动芯片之间的互连密度，从而提升信号传输效率。
附图说明
图1至图9绘示本发明一实施例的封装器件的制作方法流程示意图。
图10绘示本发明另一实施例的封装器件的剖面示意图。
附图标号
1,2:封装器件
12:衬底
12s,20s,28s:上表面
14:剥离层
16:导电柱
18,38,40:介电层
20:桥接芯片
20b:背面
20m:主体部
20n:绝缘层
20p:焊垫
22:黏着层
28:感光封装层
28a,28b,38a,38b,40a,40b:穿孔
30:重布线层
32,34,36:导电层
32a,32b,34a,34b:走线
36a,36b:区块
42a,42b,46:导电凸块
44,44a,44b:主动芯片
48,60:底部填充层
50:封装体
52:半成品结构
54:导电端子
56:封装结构
58:基板
62:加固件
64:焊球
66:金属盖
68:散热膏
CG:芯片群组
D1,D3:间距
D2:深度
H1,H2:高度
ND:法线方向
OP:开口
T:厚度
W1,W2:宽度
具体实施方式
下文结合具体实施例和附图对本发明的内容进行详细描述，且为了使本发明的内容更加清楚和易懂，下文各附图为可能为简化的示意图，且其中的器件可能并非按比例绘制。并且，附图中的各器件的数量与尺寸仅为示意，并非用于限制本发明的范围。
以下实施例中所提到的方向用语，例如：上、下、左、右、前或后等，仅是参考附加图式的方向。因此，使用的方向用语是用来说明并非用来限制本发明。必需了解的是，为特别描述或图示的器件可以本领域技术人员所熟知的各种形式存在。
当器件或膜层被称为在另一器件或另一膜层上或之上时，应被了解为所述的器件或膜层是直接位于另一器件或另一膜层上，也可以是两者之间存在有其他的器件或膜层(非直接)。但相反地，当器件或膜层被称为“直接”在另一个器件或膜层“上”时，则应被了解两者之间不存在有插入的器件或膜层。
于文中提及一器件“电连接”或“耦接”另一器件时，可包括“器件与另一器件之间可更存在其它器件而将两者电连接”的情况，或是包括“器件与另一器件之间未存有其它器件而直接电连接”的情况。若于文中提及一器件“直接电连接”或“直接耦接”另一器件时，则指“器件与另一器件之间未存有其它器件而直接电连接”的情况。
请参考图1至图9。图1至图9绘示本发明一实施例的封装器件的制作方法流程示意图，其中图5绘示图4的区域R的放大示意图，图9绘示本发明一实施例的封装器件的剖面示意图。图1至图9所显示的结构可分别为在制作封装器件的不同过程中的部分结构，且可省略部分膜层或器件，但不限于此。如图1所示，首先提供衬底12，其中衬底12上可具有剥离层(release layer)14。衬底12可用以承载形成于其上的膜层或器件，衬底12可例如包括玻璃、芯片基板、金属或其他合适的支撑材料，但不限于此。剥离层14可用以在完成后续步骤之后将衬底12与其上所形成的器件(例如，图7所示的封装结构52)分离。剥离层14的解离方式可例如包括光解离或其他合适的方式。剥离层14可例如包括聚乙烯(polyethylene,PE)、聚对苯二甲酸乙二醇酯(polyethylene terephthalate,PET)、环氧树脂(epoxy)、定向聚丙烯(oriented polypropylene,OPP)或其他合适的材料，但不限于此。
如图1所示，可于衬底12上形成多个并排设置的导电柱16。导电柱16可例如通过沉积工艺搭配光刻与刻蚀工艺、电镀工艺搭配刻蚀工艺或其他适合的工艺所形成，但不限于此。在图1的实施例中，导电柱16可例如为单层结构或多层结构。导电柱16可例如由铜(copper)所形成，但不限于此。在一些实施例中，如图1所示，可于形成导电柱16之前，于剥离层14上选择性形成介电层18。在此情况下，导电柱16可形成于介电层18上，相较于形成在剥离层14上，导电柱16与介电层18之间的接合度较佳，因此通过介电层18，可有助于提升导电柱16与衬底12之间的接合度，并降低以直立方式设置于衬底12上的导电柱16从衬底12上脱落或倾倒。介电层18可例如包括聚酰亚胺(polyimide,PI)或其他合适的有机材料，但不限于此。
如图2所示，在形成导电柱16之后，可以面朝上(face up)的方式将至少一个桥接芯片20设置于衬底12上。换言之，桥接芯片20可具有多个焊垫20p，朝上设置，而桥接芯片20的背面20b朝向衬底12设置。举例来说，设置桥接芯片20可通过固晶(die attach)工艺利用黏着层22将桥接芯片20接合于剥离层14(或介电层18)上。黏着层22可例如包括芯片黏着膜(die attach film,DAF)、双面胶或其他合适的材料。桥接芯片20可例如包括多条走线，用以耦接后续工艺所形成的主动芯片(例如，图6所示的主动芯片44)。桥接芯片20中的走线间距(例如，细间距(fine pitch))可例如为1微米(μm)到2微米或为次微米等级，但不限于此。图2所示的桥接芯片20的数量可为多个，但不限于此。桥接芯片20的数量可例如依据芯片群组(例如，图6所示的芯片群组CG)中的主动芯片或芯片群组的数量而定。在一些实施例中，桥接芯片20可选择性另包括被动器件，例如电阻、电容、电感或其他类似的器件。在一些实施例中，桥接芯片20也可选择性另包括主动器件。在一些实施例中，桥接芯片20在垂直于衬底12的上表面12s的法线方向ND上的厚度可例如为约10微米到100微米或更高。在本文中，芯片也可以称为晶粒，但不限于此。本文中的“耦接”也可称为“电连接”，但不限于此。
在图2的实施例中，桥接芯片20的焊垫20p上可不具有凸块(bump)，因此焊垫20p可被曝露出。由于桥接芯片20的焊垫20p不需形成凸块，因此可降低制作成本。举例来说，桥接芯片20可包括主体部20m以及绝缘层20n，其中焊垫20p可设置于主体部20m上，且绝缘层20n设置于焊垫20p上，并具有曝露出对应的焊垫20p的开口OP。焊垫20p可例如为铝垫，但不限于此。
在图2的实施例中，导电柱16的高度H1可例如低于桥接芯片20相对于衬底12的上表面20s的高度H2(例如，为上表面20s与介电层18相对于剥离层14的表面之间的距离、或为桥接芯片20的厚度与黏着层22的厚度的总和)，如此可降低制作导电柱16的时间与成本。桥接芯片20的上表面20s可例如为图2所示绝缘层20n的上表面与焊垫20p的上表面所形成，但不限于此。在一些实施例中，两相邻导电柱16之间的间距可例如大于两相邻焊垫20p之间的间距，但不限于此。
如图3所示，接着可于导电柱16与桥接芯片20上形成感光封装层(photosensitiveencapsulation layer)28。举例来说，感光封装层28可为干膜，并通过贴合工艺(lamination process)设置在导电柱16与桥接芯片20上，其中感光封装层28可围绕导电柱16以及桥接芯片20。然后，可通过光刻工艺(即，曝光与显影工艺)，于感光封装层28中形成多个穿孔28a以及多个穿孔28b，其中穿孔28a可曝露出对应的导电柱16，且穿孔28b可曝露出对应的桥接芯片20的焊垫20p。由于感光封装层28可延伸到导电柱16与桥接芯片20上，因此桥接芯片20的上表面20s与感光封装层28相对于衬底12的上表面28s之间的间距D3可小于导电柱16相对于衬底12的上表面16s与感光封装层28的上表面28s之间的间距D1。
需说明的是，相较于一般光阻材料，感光封装层28可具有较大的厚度，因此在桥接芯片20具有一定厚度(例如，10微米到100微米)的情况下，感光封装层28的厚度T仍可大于导电柱16的高度H1以及桥接芯片20的上表面20s的高度H2，使得感光封装层28的上表面28s可高于导电柱16的上表面16s以及桥接芯片20的上表面20s。在一些实施例中，穿孔28a的深度(即，导电柱16的上表面16s与感光封装层28的上表面28s之间的间距D1)可例如大于穿孔28b的深度D2(即，焊垫20p的上表面与感光封装层28的上表面28s之间的间距)。在一些实施例中，穿孔28a的宽度W1可例如大于穿孔28b的宽度W2。值得说明的是，由于感光封装层28中可通过光刻工艺形成曝露出导电柱16的穿孔28a与曝露出桥接芯片20的穿孔28b，因此导电柱16的高度H1可设计为小于桥接芯片20的上表面20s的高度H2，进而降低制作成本。
此外，感光封装层28除了具有感光的特性之外，还可具有填充与密封的特性，因此可设置于导电柱16之间以及导电柱16与桥接芯片20之间，并用以保护导电柱16以及桥接芯片20。举例来说，感光封装层28可包括硅氧烷聚合物(例如中国台湾地区信越硅利光(shin-etsu chemical)的SINR)，或其他合适的有机材料。值得一提的是，相较于传统封装材料(例如，环氧树脂或模塑(molding)材料)而言，感光封装层28具有较低杨氏模量(Young’smodulus)，换言之，感光封装层28不会对导电柱16、桥接芯片20与衬底12造成明显的应力影响，因此在后续工艺中可降低衬底12的翘曲，从而降低导电柱16与桥接芯片20的焊垫20p的位置以及后续所形成的器件(例如，图4与图5所示的重布线层30)的相对位置受到感光封装层28的影响，并降低封装器件的制作复杂度。
如图4与图5所示，于感光封装层28上形成重布线层30，使得部分感光封装层28可设置于导电柱16与重布线层30之间以及桥接芯片20与重布线层30之间。重布线层30可包括至少两层导电层以及至少一层介电层。在图5的实施例中，重布线层30的导电层以包括导电层32、导电层34与导电层36为例，且介电层以包括介电层38与介电层40为例，但不以此为限。在一些实施例中，导电层的层数以及介电层的层数可依据实际需求作调整。
在图5的实施例中，导电层32可设置于感光封装层28上，并包括多条走线32a以及多条走线32b，其中走线32a分别通过对应的穿孔28a耦接对应的导电柱16，且走线32b分别通过对应的穿孔28b耦接对应的桥接芯片20的焊垫20p。举例来说，由于导电柱16与焊垫20p可分别被穿孔28a与穿孔28b曝露出，因此导电层32的走线32a可延伸到穿孔28a中并直接接触导电柱16，且走线32b可延伸到穿孔28b中并直接接触桥接芯片20的焊垫20p，故桥接芯片20的焊垫20p上可不需额外制作用以接合的凸块，进而可降低桥接芯片20的厚度以及导电柱16的厚度。介电层38可设置于导电层32上，并具有多个穿孔38a以及多个穿孔38b，分别曝露出对应的走线32a与走线32b的一部分。导电层34可设置于介电层38上，并包括多条走线34a以及多条走线34b，走线34a可分别通过对应的穿孔38a耦接对应的走线32a，且走线34b可分别通过对应的穿孔38b耦接对应的走线32b。介电层40可设置于导电层34与介电层38上，并具有多个穿孔40a以及多个穿孔40b，分别曝露出对应的走线34a与走线34b的一部分。导电层36可包括多个区块36a以及多个区块36b，分别设置于穿孔40a与穿孔40b中。在一些实施例中，重布线层30可选择性另包括导电凸块(conductive bump)42a以及导电凸块42b，分别设置于对应的区块36a与区块36b上，以助于与后续工艺中的器件(例如，主动芯片)接合。导电凸块42a以及导电凸块42b可例如选择性为多层结构。多层结构可例如包括铜(copper)、镍(nickel)、金(gold)、其他合适的材料、上述至少两者的合金或上述的组合，但不限于此。在一些实施例中，重布线层30中同一层导电层的走线间距(例如，细间距)可例如为2微米到10微米。
如图6所示，于重布线层30上设置至少两个主动芯片44，使得主动芯片44可通过重布线层30耦接桥接芯片20，进而可彼此耦接。在图6的实施例中，主动芯片44的数量可例如为多个，且主动芯片44可区分为至少两个芯片群组CG，分别对应所欲形成的封装器件(例如图9所示的封装器件1)，但不限于此。
在图6的实施例中，主动芯片44可例如包括多个导电凸块46，以助于与重布线层30接合，但不限于此。主动芯片44的导电凸块46可例如以面朝下(face down)的方式通过覆晶(flip chip)接合工艺与重布线层30的导电凸块42a和导电凸块42b接合。导电凸块46与导电凸块42a和导电凸块42b之间可另包括金属焊料(未绘示)，例如锡合金焊料，但不限于此。举例来说，主动芯片44可另包括主体部44m、多个输入/输出焊垫44p以及绝缘层44n，其中输入/输出焊垫44p可设置于主体部44m与绝缘层44n之间，且绝缘层44n具有多个开口，曝露出对应的输入/输出焊垫44p。导电凸块46可分别形成在对应的输入/输出焊垫44p上。
在一些实施例中，主动芯片44的两相邻导电凸块46之间的间距可小于或等于桥接芯片20的两相邻焊垫(如图5所示的焊垫20p)之间的间距。当导电凸块46之间的间距等于焊垫20p之间的间距时，重布线层30中用于将彼此耦接的导电凸块46与焊垫20p耦接的走线(如图5所示的走线32b与走线34b)、区块(如图5所示的区块36b)以及导电凸块42b在垂直于衬底12的上表面12s的法线方向ND上可彼此对齐，但不限于此。在一些实施例中，两相邻导电凸块46之间的间距可小于两相邻导电柱16之间的间距。
主动芯片44可例如包括电源管理芯片(power management integrated circuit,PMIC)、微机电系统(micro-electro-mechanical-system,MEMS)芯片、专用集成电路芯片(application-specific integrated circuit,ASIC)、动态随机存取存储器(dynamicrandom access memory,DRAM)芯片、静态随机存取存储器(static random accessmemory,SRAM)芯片、高带宽存储器(high bandwidth memory,HBM)芯片、系统芯片(systemon chip,SoC)、高性能运算(high performance computing,HPC)芯片或其他类似的主动芯片，但不限于此。导电凸块46可例如包括多层结构。导电凸块46可例如包括铜、镍、锡(tin)、银(silver)、其他合适的材料、上述至少两者的合金或上述的组合，但不限于此。
在图6的实施例中，芯片群组CG可包括同质(homogeneous)或异质(heterogeneous)的主动芯片44a与主动芯片44b。当主动芯片44a与主动芯片44b为异质时，主动芯片44a与主动芯片44b可例如分别为系统芯片与高带宽存储器芯片，但不限于此。举例来说，一个芯片群组CG可包括一颗主动芯片44a以及四颗主动芯片44b，但不限于此。在本文中，主动芯片44可指包括主动器件的芯片，主动器件44可包括晶体管、二极管、集成电路、光电器件或其他具有增益的合适器件，但不限于此。在一些实施例中，当桥接芯片20包括主动器件时，桥接芯片20中的主动器件与主动芯片44的主动器件可由不同的半导体工艺技术节点所制作出，举例来说，桥接芯片20中的主动器件的密度大于主动芯片44的主动器件的密度，但不限于此。
在一些实施例中，由于重布线层30可在设置主动芯片44之前形成，因此可在设置主动芯片44之前，选择性对重布线层30进行自动光学检测(automated opticalinspection,AOI)及/或开路与短路测试(open/short test,O/S test)，以确保重布线层30的品质，因此可避免因重布线层30的不良所造成的芯片损失或浪费。在一些实施例中，自动光学检测及/或开路与短路测试可在完成重布线层30之后进行或在形成重布线层30的过程中重复进行多次。
在一些实施例中，如图6所示，在将主动芯片44设置于重布线层30上之后，可选择性于主动芯片44与重布线层30之间填入底部填充层48，以助于强化主动芯片44与重布线层30之间的接合度，从而降低导电凸块42a与导电凸块46之间以及导电凸块42b与导电凸块46之间的断裂。底部填充层48可例如包括毛细填充胶(capillary underfill,CUF)或其他合适的填充材料，但不限于此。底部填充层48可例如通过点胶工艺形成，但不限于此。
如图7所示，在设置主动芯片44之后，可于重布线层30上形成封装体50，且封装体50可围绕主动芯片44，用以保护主动芯片44。具体来说，封装体50可例如通过模封工艺形成在主动芯片44之间以及主动芯片44的背面上。封装体50可例如包括模塑化合物(moldingcompound)或其他合适的封装材料，但不限于此。封装体50的杨氏模量可大于感光封装层28的杨氏模量。
需说明的是，由于重布线层30是在设置主动芯片44以及需在高温环境进行并降温的模封工艺之前形成，因此主动芯片44可在尚未遇到高温差的环境下设置于重布线层30上，如此可降低重布线层30因受到高温差所产生的翘曲影响，从而简化工艺的复杂度。
在图7的实施例中，可选择性对封装体50进行减薄工艺，移除封装体50位于主动芯片44上的部分，以露出主动芯片44的背面，从而可有助于主动芯片44的散热。减薄工艺可例如包括化学机械抛光(chemical mechanical polishing,CMP)工艺、机械研磨(mechanicalgrinding)、刻蚀(etching)或其他合适的工艺，但不限于此。
如图8所示，在形成封装体50之后，可从导电柱16、黏着层22以及感光封装层28上移除衬底12，以曝露出导电柱16、黏着层22以及感光封装层28相对于重布线层30的表面。移除衬底12的方式可例如包括对剥离层14照射光线，以降低剥离层14的黏着力，进而移除衬底12，但不限于此。接着，将包含有封装体50、主动芯片44、重布线层30、导电柱16、感光封装层28以及桥接芯片20的半成品结构52上下翻转，使得桥接芯片20的背面20b朝上，而主动芯片44的背面朝下。随后，于每个导电柱16上形成导电端子54。导电端子54可例如通过电镀、沉积、植球(ball mounting)、回焊(reflow)及/或其他合适的工艺所形成。导电端子54可例如包括焊球(solder ball)、导电凸块或其他合适的导电端子。焊球可例如包括锡球。导电凸块可例如包括多层结构。导电凸块可例如包括铜、镍、锡、银、其他合适的材料、上述至少两者的合金或上述的组合，但不限于此。
如图8所示，可对半成品结构52进行单一化工艺(singulation process)，以形成至少一个封装结构56。在图8的实施例中，半成品结构52可包括至少两个芯片群组CG，因此单一化工艺可将不同的芯片群组CG分隔开，且将对应不同芯片群组CG的桥接芯片20与导电柱16分隔开，以形成至少两个封装结构56。单一化工艺可例如包括切割工艺或其他合适的工艺。在一些实施例中，形成导电端子54的步骤以及进行切割工艺的步骤的顺序也可彼此互换。
如图9所示，在形成导电端子54之后，可将封装结构56上下翻转，并将封装结构56的导电端子54设置于基板58上。通过导电端子54，可将封装结构56的导电柱16接合并耦接于基板58。然后，于封装结构56的感光封装层28与基板58之间形成底部填充层60，以形成封装器件1。基板58可例如包括封装基板、电路板或其他合适的基板。封装结构56可通过导电端子54与基板58接合并耦接。底部填充层60可延伸到封装结构56的感光封装层28与封装体50的侧壁上，并可强化封装结构56与基板58之间的接合度。底部填充层60的材料与形成方式可例如相同或类似底部填充层48的材料与形成方式，因此在此不多赘述。
在一些实施例中，基板58上可设置有加固件62，且加固件62可例如围绕封装结构56，并与底部填充层60分隔开。加固件62可例如包括金属。在一些实施例中，基板58下方可选择性设置有焊球64，以助于封装器件1进一步与其他器件的耦接与接合，但不限于此。
在图9的封装器件1中，由于桥接芯片20的走线间距可小于重布线层30的走线间距，因此通过桥接芯片20耦接不同的主动芯片44，可提升主动芯片44之间的互连密度，从而降低主动芯片44之间的信号传输路径或时间，并提升信号传输效率。在此情况下，重布线层30的走线间距可不需达到细间距，以简化工艺复杂度并降低制作成本。并且，通过走线间距较小的桥接芯片20，重布线层30的层数可降低，从而可降低封装结构56的翘曲，并有助于封装结构56与基板58中的焊垫的接合良率。
再者，由于黏着层22设置于桥接芯片20的背面20b上，因此在将封装结构56设置于基板58时，黏着层22可保护桥接芯片20，以降低桥接芯片20的破裂或断线。通过黏着层22的保护，桥接芯片20在法线方向(例如垂直基板58的上表面的法线方向ND)上的厚度可在不会产生破裂或断线的情况下进一步被减薄，藉此可降低封装器件1在法线方向ND上的整体厚度。在此情况下，导电柱16的高度(如图2所示的高度H1)可进一步降低，从而可降低制作时间与成本。并且，导电柱16的间距也可降低，以提供较高的信号输出密度，及/或缩小封装器件1的尺寸。
需说明的是，在封装器件1中，由于重布线层30设置于主动芯片44与导电柱16以及桥接芯片20之间，因此主动芯片44可通过重布线层30同时耦接到具有不同间距的导电柱16以及桥接芯片20的焊垫(如图5所示的焊垫20p)。此外，主动芯片44可通过重布线层30以及导电柱16耦接至基板58，相较于通过硅中介层(silicon interposer)耦接到基板58，导电柱16的制作成本可明显低于硅中介层的制作成本，因此可有效地降低封装器件1的制作成本。
图10绘示本发明另一实施例的封装器件的剖面示意图。如图10所示，本实施例的封装器件2与图9所示的封装器件1的区别在于，封装器件2可另包括金属盖66，取代图9的加固件62，并设置于封装结构56以及基板58上。金属盖66可例如覆盖并围绕封装结构56，以保护封装结构56。金属盖66可例如为一体成形的结构，但不限于此。在一些实施例中，封装器件2可选择性另包括散热膏68，设置于主动芯片44的背面上。散热膏68可例如直接接触主动芯片44与金属盖66，以助于对主动芯片44散热。散热膏68可例如在设置金属盖66之前涂布于主动芯片44的背面上，但不限于此。
综合上述，在本发明的封装器件中，通过桥接芯片耦接不同的主动芯片，可提升主动芯片之间的互连密度，从而提升信号传输效率。并且，由于黏着层可设置于桥接芯片的背面上，因此在将桥接芯片设置于基板时，黏着层可保护桥接芯片，以降低桥接芯片的破裂或断线。另外，重布线层可设置于主动芯片与导电柱以及桥接芯片之间，因此主动芯片可通过重布线层耦接到具有不同间距的导电柱以及桥接芯片的焊垫，并可通过导电柱耦接至基板，进而可降低封装器件的制作成本。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求范围所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (20)

1.一种封装器件，其特征在于，包括：
一基板；
多个导电柱，并排设置于该基板上；
至少一桥接芯片，设置于该基板上；
一感光封装层，围绕该至少一桥接芯片以及该多个导电柱，其中该至少一桥接芯片的上表面与该感光封装层的上表面之间的间距小于该多个导电柱中的一个的上表面与该感光封装层的该上表面之间的间距；
一重布线层，设置于该感光封装层上；
至少两主动芯片，设置于该重布线层上，且该至少一桥接芯片耦接于该至少两主动芯片之间；以及
一封装体，设置于该重布线层上，并围绕该至少两主动芯片。
2.如权利要求1所述的封装器件，其特征在于，还包括一黏着层，设置于该至少一桥接芯片与该基板之间。
3.如权利要求1所述的封装器件，其特征在于，该感光封装层具有多个第一穿孔以及多个第二穿孔，该多个第一穿孔中的一个曝露出该多个导电柱中的一个，该至少一桥接芯片具有多个焊垫，且该多个第二穿孔中的一个曝露出该多个焊垫中的一个。
4.如权利要求3所述的封装器件，其特征在于，该多个第一穿孔中的一个的宽度大于该多个第二穿孔中的一个的宽度。
5.如权利要求3所述的封装器件，其特征在于，该多个第一穿孔中的一个的深度大于该多个第二穿孔中的一个的深度。
6.如权利要求1所述的封装器件，其特征在于，该感光封装层设置于该至少一桥接芯片与该重布线层之间。
7.如权利要求1所述的封装器件，其特征在于，该至少一桥接芯片不具有凸块。
8.如权利要求1所述的封装器件，其特征在于，该封装体的杨氏模量大于该感光封装层的杨氏模量。
9.如权利要求1所述的封装器件，其特征在于，该重布线层设置于该至少一桥接芯片与该至少两主动芯片之间。
10.如权利要求1所述的封装器件，其特征在于，还包括一底部填充层，围绕该感光封装层，并设置于该感光封装层与该基板之间。
11.一种封装器件的制作方法，其特征在于，包括：
于一衬底上形成多个导电柱并设置至少一桥接芯片；
于该多个导电柱与该至少一桥接芯片上形成一感光封装层，其中该感光封装层围绕该至少一桥接芯片以及该多个导电柱，且该至少一桥接芯片的上表面与该感光封装层的上表面之间的间距小于该多个导电柱中的一个的上表面与该感光封装层的该上表面之间的间距；
于该感光封装层上形成一重布线层；
于该重布线层上设置至少两主动芯片；
于该重布线层上形成一封装体，其中该封装体围绕该至少两主动芯片；以及
移除该衬底。
12.如权利要求11所述的封装器件的制作方法，其特征在于，设置该至少一桥接芯片包括利用一黏着层将该至少一桥接芯片接合于该衬底上。
13.如权利要求11所述的封装器件的制作方法，其特征在于，形成该感光封装层包括通过一光刻工艺，于该感光封装层中形成多个第一穿孔以及多个第二穿孔，该多个第一穿孔中的一个曝露出该多个导电柱中的一个，该至少一桥接芯片具有多个焊垫，且该多个第二穿孔中的一个曝露出该多个焊垫中的一个。
14.如权利要求11所述的封装器件的制作方法，其特征在于，该感光封装层设置于该至少一桥接芯片与该重布线层之间。
15.如权利要求11所述的封装器件的制作方法，其特征在于，该至少一桥接芯片具有多个焊垫，且该重布线层直接接触该多个焊垫。
16.如权利要求11所述的封装器件的制作方法，其特征在于，该感光封装层的杨氏模量小于该封装体的杨氏模量。
17.如权利要求11所述的封装器件的制作方法，其特征在于，还包括对该封装体进行减薄工艺，以露出该至少两主动芯片的背面。
18.如权利要求11所述的封装器件的制作方法，其特征在于，于形成该重布线层与设置该至少两主动芯片之间，该制作方法另包括对该重布线层进行自动光学检测。
19.如权利要求11所述的封装器件的制作方法，其特征在于，还包括于该多个导电柱的每一个相对于该重布线层的表面上形成一导电端子。
20.如权利要求19所述的封装器件的制作方法，其特征在于，还包括：
将该多个导电端子设置于一基板上；以及
于该感光封装层与该基板之间形成一底部填充层。
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