CN116779451A - Method for forming 3C-SIC layer in direct contact with 4H-SIC material - Google Patents
Method for forming 3C-SIC layer in direct contact with 4H-SIC material Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000000463 material Substances 0.000 title claims abstract description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 41
- 239000010703 silicon Substances 0.000 claims abstract description 41
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 38
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 32
- 238000002844 melting Methods 0.000 claims abstract description 19
- 230000008018 melting Effects 0.000 claims abstract description 19
- 238000010438 heat treatment Methods 0.000 claims abstract description 18
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 130
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 20
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 20
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 claims description 14
- 229910002090 carbon oxide Inorganic materials 0.000 claims description 14
- 230000001590 oxidative effect Effects 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 239000002019 doping agent Substances 0.000 claims description 5
- 229910021389 graphene Inorganic materials 0.000 claims description 5
- 229910002804 graphite Inorganic materials 0.000 claims description 5
- 239000010439 graphite Substances 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 5
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- 235000012431 wafers Nutrition 0.000 description 60
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- 238000002425 crystallisation Methods 0.000 description 10
- 230000008025 crystallization Effects 0.000 description 10
- 238000002513 implantation Methods 0.000 description 7
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910003465 moissanite Inorganic materials 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000000859 sublimation Methods 0.000 description 2
- 230000008022 sublimation Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000002178 crystalline material Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
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- 239000012467 final product Substances 0.000 description 1
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- 229910052757 nitrogen Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/42—Bombardment with radiation
- H01L21/423—Bombardment with radiation with high-energy radiation
- H01L21/428—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
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Abstract
The present disclosure relates to methods of forming a 3C-SIC layer in direct contact with a 4H-SIC material. A method for manufacturing a 3C-SiC layer, comprising the steps of: providing a 4H-SiC wafer having a surface; heating a selective portion of the wafer by a laser beam to at least a melting temperature of a material of the selective portion; cooling and crystallizing the melted selective portion to form a 3C-SiC layer, a silicon layer on the 3C-SiC layer, and a carbon-rich layer on the silicon layer; the carbon-rich layer and the silicon layer are completely removed, exposing the 3C-SiC layer. If the silicon layer remains on the 4H-SiC wafer, the process results in the formation of a silicon layer on the 4H-SiC wafer. The 3C-SiC or silicon layer thus formed can be used for integration of electrical or electronic components, even only partially.
Description
Technical Field
The present disclosure relates to a process for processing a 4H-SiC wafer to form a layer, such as a 3C-SiC or silicon layer, on the 4H-SiC wafer having a reduced bandgap relative to 4H-SiC.
Background
Semiconductor devices are commonly manufactured in silicon wafers, as is well known. Silicon carbide (SiC) wafers, however, are becoming increasingly popular due, at least in part, to the favorable physicochemical properties of SiC. For example, siC generally has a higher bandgap relative to silicon, with the result that a greater barrier height is obtained when, for example, schottky contacts are formed. In addition, the breakdown voltage of SiC is also greater than that of silicon. This is because the critical electric field of silicon carbide is about ten times that of silicon. In general, an advantage associated with fabricating devices on a 4H-SiC substrate (bulk) is the advantage of maintaining breakdown voltage, but with a lower bandgap material (e.g., silicon or 3C-SiC) on the surface, thereby reducing the barrier height of, for example, a Schottky contact. In other words, it is desirable to maintain the advantages of reverse bias and optimize the voltage drop of forward bias.
Silicon carbide (SiC) has different crystal forms, also known as polytypes. The most common polytypes are cubic polytype (polytype 3C-SiC), hexagonal polytype (polytype 4H-SiC and 6H-SiC) and rhombohedral polytype (polytype 15R-SiC). Among them, cubic polytype 3C-SiC is currently being studied intensively because of its unique properties compared to other wafer polytypes. Polytype 3C-SiC offers several advantages for Metal Oxide Semiconductor (MOS) device applications, for example, it can help increase drift mobility by reducing oxide/3C-SiC interface trap density. The reduced bandgap of 3C-SiC helps to reduce the electric field strength required to achieve channel inversion. Other characteristics that make 3C-SiC interesting are the low value of on-state resistance Ron, which is particularly useful in the case of devices that operate up to and exceeding 650V.
For easier fabrication relative to other polytypes, 4H-SiC is typically used as a substrate. However, the band gap of 4H-SiC is larger (3.2 eV) relative to the corresponding band gap of 3C-SiC (2.3 eV) or silicon (1.12 eV), making 4H-SiC unattractive for some electronic applications relative to 3C-SiC or relative to silicon. For example, in the case of schottky barrier diodes, the possibility of controlling the Schottky Barrier Height (SBH) is an important aspect in order to reduce power consumption and minimize conduction losses. For this reason, the implementation of metal/3C-SiC or metal/Si contacts requires lower SBH values relative to those of metal/4H-SiC contacts, enabling more efficient schottky diodes to be fabricated.
Different methods have been proposed for growing cubic silicon carbide (3C-SiC) on hexagonal silicon carbide (4H-SiC or 6H-SiC) substrates. One of these mechanisms is known as the vapour-Liquid-solid (VLS) mechanism, described for example by Soueidan M et al, "A Vapor-Liquid-Solid Mechanism for Growing C-SiC Single-Domain Layers on 6H-SiC (0001)" Advanced functional materials, volume.16, pages 975-979, month 5, 2, 2006.
Another method is known as Sublimation Epitaxy (SE).
However, the above-described methods require multiple growth steps and high control over the surface morphology (particularly with respect to layers or films grown on off-axis 4H-SiC substrates using SE methods).
An alternative to the above described techniques for fabricating 3C-SiC layers is Chemical Vapor Deposition (CVD) on a silicon substrate. However, the 3C-SiC layer thus formed has a high defect density (at 10 8 -10 9 /cm 2 Caused by a lattice mismatch of about 20% between the two materials).
Other solutions have also been proposed, such as heteroepitaxial growth of 3C-SiC on coaxial 6H-SiC substrates by CVD techniques or sublimation. However, the large number of parameters set to obtain a final product with good quality and the large number of parameters affecting the formation of the 3C-SiC layer limit the use of the known methods, in particular in the field of industrial and mass production.
Disclosure of Invention
The present disclosure provides at least one embodiment of a process for processing 4H-SiC wafers in a manner that overcomes the shortcomings and limitations of the prior art.
At least one embodiment of a method for processing a wafer of 4H-SiC material may include the steps of: heating a selective portion at a surface of the wafer by a laser beam to at least reach a melting temperature of a material of the selective portion; crystallizing the melted selective portion to form a stack of superimposed layers, the superimposed layers comprising: a 3C-SiC layer in contact with the 4H-SiC material of the wafer, a silicon layer on the 3C-SiC layer and a carbon-rich layer on the silicon layer; and completely removing the carbon-rich layer.
Drawings
For a better understanding of the present disclosure, preferred embodiments thereof will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:
FIGS. 1A-1F illustrate successive steps of a process for fabricating a 3C-SiC layer according to embodiments of the disclosure;
FIG. 2 illustrates steps of a process for fabricating a 3C-SiC layer according to another embodiment of the disclosure;
3A-3E illustrate successive steps of a process for fabricating a 3C-SiC layer according to another embodiment of the disclosure; and
fig. 4 illustrates steps of a process for fabricating a 3C-SiC layer according to another embodiment of the present disclosure.
Detailed Description
1A-1F, a method for forming a silicon carbide layer of polytype 3C-SiC is shown and described in accordance with embodiments of the disclosure. FIGS. 1A-1F are represented by three axes of reference in the X, Y, Z axes orthogonal to each other.
Referring to fig. 1A, a silicon carbide wafer 1 of polytype 4H-SiC, in particular crystalline 4H-SiC, and even more particularly single crystal 4H-SiC, is provided. The wafer 1 includes a front side 1a and a rear side 1b opposite to each other along the Z-axis. In one embodiment, wafer 1 has a first conductivity type, such as an N-type conductivity type, and is shown at 10 18 -10 22 Atoms/cm 3 Is doped within the range of (a). Wafer 1 has a thickness or dimension T1, for example as shown in FIG. 1A, measured along the Z-axis, equal to about 100-400 μm. The lateral side 1c extends from the front side 1a to the rear side 1b and is transverse to the front side 1a and the rear side 1b. The front side 1a comprises a front surface and the rear side 1b comprises a rear surface. The front surface may be referred to as a first surface and the rear surface may be referred to as a second surface.
In general, the present invention is applicable to any 4H-SiC substrate.
In another embodiment, the wafer 1 has a different conductivity (i.e., P-type). However, for the purposes of the present invention, the conductivity or the starting doping type of the wafer 1 is not relevant.
The wafer 1 is manufactured in a manner known per se and is not an object of the invention. However, 4H-SiC wafers are commercially available.
Referring to fig. 1B, an implantation (parallel to the Z-axis, indicated by arrow 2) step of the dopant is performed. Implantation occurs at the anterior side 1a and is performed without an implantation mask (use of an implantation mask may still be provided as needed and as a matter of design choice).
Thereby forming a doped layer 3 extending uniformly at the front side 1 a. The doped layer 3 extends in depth into the wafer 1 and reaches a maximum depth comprised between 100nm and 1000nm measured from the surface of the front side 1 a.
In one embodiment, the doping step of fig. 1B may provide doping of a dopant having a first conductivity (N), such as nitrogen (N) and phosphorus (P). At an implantation energy of between 20 and 500keV and 10 14 To 10 16 Atoms/cm 2 The dose between them is implanted to form a doping concentration of 10 17 To 10 20 Atoms/cm 3 Is provided, is provided (3).
In various embodiments, the doping step of fig. 1B may provide for the doping of a dopant having a second conductivity (P) opposite the first conductivity, such as aluminum. At an implantation energy of between 20 and 500keV and 10 14 To 10 16 Atoms/cm 2 The dose between them is implanted to form a doping concentration of 10 17 To 10 20 Atoms/cm 3 A doped layer 3 in between.
The implantation step "breaks" the crystal structure of the 4H-SiC so that the melting step described below can be performed at a lower temperature relative to the case of crystalline material (e.g., the case described in fig. 3B).
Subsequently, in fig. 1C, a thermal budget (ridge) is generated at the surface of the front side 1a for causing local melting of a portion of the wafer 1 at the front side 1 a.
For this purpose, a laser source 100 configured to generate a beam 102 is used such that it heats the front side 1a, in particular the doped layer 3, to a temperature comprised between about 1600 ℃ and 3000 ℃. Given the maximum depth reached by the doped layer 3, a temperature of about 2000 ℃ at the level of the surface of the front side 1a is sufficient to ensure that the temperature is within the above-mentioned range even at the maximum depth reached by the doped layer 3.
As described above, the temperature is such that it causes melting of doped layer 3; by interrupting the generation of the beam 102, i.e. interrupting the heating of the wafer 1, resolidification and crystallization of the previously melted portions is observed. In particular, applicants have observed that crystallization of wafer 1 produces a plurality of superimposed layers, including a 3C-SiC layer 4 on a 4H-SiC material that is not melted, a silicon layer 6a on 3C-SiC layer 4, and one or more carbon-rich layers 6b (including, for example, one or more graphite layers and/or one or more graphene layers) on silicon layer 6a, as shown in fig. 1D.
For example, choi, i., jeong, h., shin, H et al demonstrate that the above-described layer "Laser-induced phase separation of silicon carbide," Nature communications, 13562 (2016) is formed by melting and subsequent crystallization of a 4H-SiC substrate.
In one embodiment, the transition of doped layer 3 to layers 4,6a and 6b occurs by heating the entire front side 1a of wafer 1, moving laser 100 appropriately. For example, multiple scans of the laser 100 are performed on the XY plane (e.g., multiple scans parallel to each other and to the X-axis and/or the Y-axis).
In another embodiment, only a predetermined portion of doped layer 3 is processed by laser 100 to obtain formation of a 3C-SiC layer only in some regions of wafer 1 and not in other regions (e.g., only in regions where active regions of devices intended to be provided/integrated in wafer 1 are to be formed). This region or regions may be spaced inwardly from the lateral sides 1c of the wafer 1.
The laser 100 is for example an excimer UV laser. Other types of lasers may be used, including lasers having wavelengths in the visible range.
Configuration and operating parameters of laser 100 optimized for the purposes of the present disclosure in accordance with the embodiments of fig. 1A-1D are as follows:
wavelengths between 290nm and 370nm, in particular 310nm;
the pulse duration is between 100ns and 300ns, in particular 160ns;
the number of pulses is between 1 and 16, in particular 2;
the energy density is 1.6J/cm 2 And 4J/cm 2 Between, in particular 2.6J/cm 2 (considered on the surface level of the front side 1 a);
the temperature is between 1400 ℃ and 3000 ℃, in particular 1800 ℃ (considered at the level of the surface 1 a).
The area of the spot of the beam 102 at the level of the front side 1a comprises, for example, between 0.7 and 1.5cm 2 Between them.
Crystallization of the molten portion occurs in an environment having a temperature between 1600 ℃ and 2700 ℃ for a time between 100ns and 300ns.
Then, in fig. 1E, an oxidation step of the carbon-rich layer 6b and the underlying silicon layer 6a is performed, thereby forming a corresponding oxide layer (denoted together with reference numeral 8 in fig. 1E). This step is performed by inserting the wafer 1 into a furnace at 800 c for 60 minutes in an oxidizing atmosphere (e.g., an oxygen-rich atmosphere). This facilitates oxidation of the carbon-rich layer and the silicon layer. The applicant did not observe corresponding oxidation of the 3C-SiC layer and the 4H-SiC substrate.
Then, a subsequent bath in a suitable wet etching solution, such as BOE (buffered oxide etchant), fig. 1F, allows complete removal of the oxide layer 8, thereby exposing the underlying 3C-SiC layer 4.
Since the etching chemistry solution selectively removes the material of the oxide layer 8, the etching is performed to completely remove the oxide layer 8 without removing the underlying 3C-SiC layer 4.
In another embodiment of the present disclosure, as shown in fig. 2, after performing the steps already described with reference to fig. 1A-1C, the melting and subsequent resolidification (recrystallization) of the material of wafer 1 results in the formation of another 6H-SiC layer 9 intermediate between the 4H-SiC material and 3C-SiC layer 4 of wafer 1.
The formation of the 6H-SiC layer 9 is caused by a suitable choice of the thermal budget provided to the 4H-SiC wafer by the laser 100, i.e. by adjusting the configuration and operating parameters of the laser 100 during the melting step of the wafer portion being processed. Subsequent crystallization of the molten portion results in additional formation of the 6H-SiC layer 9 in a natural manner (i.e., without further intervention by the operator). The configuration/operating parameters of the laser 100 (i.e., the radiation emitted by the laser) are as follows:
wavelengths between 290nm and 370nm, in particular 310nm;
the pulse duration is between 100ns and 300ns, in particular 160ns;
the number of pulses is between 1 and 16, in particular between 1 and 10, for example 2;
the energy density is 1.6J/cm 2 And 4J/cm 2 Between, in particular 2.6J/cm 2 (considered on the surface level of the front side 1 a);
the temperature is between 1400 ℃ and 2600 ℃, in particular 1800 ℃ (considered at the level of the surface 1 a).
Crystallization of the molten portion occurs in an environment having a temperature between 1600 ℃ and 2700 ℃ for a time between 100ns and 300ns.
Then, the oxidation and etching steps already described with reference to fig. 1E and 1F are performed.
Fig. 3A-3E illustrate another embodiment of the present invention. Fig. 3A-3E illustrate three-axis reference frames of X, Y, Z axes orthogonal to each other.
Referring to fig. 3A, a silicon carbide wafer 21 of polytype 4H-SiC, particularly crystalline 4H-SiC, and even more particularly single crystal 4H-SiC, is provided. Wafer 21 includes a front side 21a and a back side 21b opposite each other along the Z-axis. In one embodiment, wafer 21 has a first conductivity type, such as N-type conductivity, and is doped between 1e18 and 1e22 atoms/cm 3 Within a range of (2). The lateral side 21c extends from the front side 21a to the rear side 21b and is transverse to the front side 21a and the rear side 21b. The front side 21a includes a front surface and the rear side 21b includes a rear surface. The front surface may be referred to as a first surface and the rear surface may be referred to as a second surface.
Wafer 21 has a thickness T1 measured along the Z axis, for example equal to about 100 and 400 μm.
In another embodiment, the wafer 21 has a different conductivity (i.e., P-type). However, for the purposes of the present invention, the conductivity or starting doping type of wafer 21 is not relevant.
The wafer 1 is manufactured in a manner known per se and is not an object of the invention. However, 4H-SiC wafers are commercially available.
Subsequently, in fig. 3B, a thermal budget is generated at the surface of the front side 21a for causing local melting of a portion of the wafer 21 at the front side 21 a.
To this end, a laser source 100 is used, which is configured to generate a light beam 102 for heating the front side 21a to a temperature equal to about 1600-3000 ℃. A temperature of about 3000 c at the level of the surface of the front side 21a is sufficient to ensure that the temperature is within the above-mentioned range of depths in the wafer 21, for example equal to about 10 μm. This temperature causes a partial melting of the wafer 21 processed by the laser 100. By interrupting the generation of the beam 102, i.e. by interrupting the heating of the wafer 21, a resolidification of the melted portion, in particular a recrystallization of its predetermined and predictable form, is observed. In particular, applicants have observed that crystallization of wafer 21 produces a plurality of superimposed layers, including a 3C-SiC layer 24 on a 4H-SiC material that has not been melted, a silicon layer 26a on 3C-SiC layer 24, and one or more carbon-rich layers 26b (including, for example, a graphite layer or graphene multilayer) on silicon layer 26a, as shown in FIG. 3C.
In one embodiment, the transition of portions of wafer 1 to layers 24, 26a and 26b occurs by heating the entire front side 21a of wafer 21, moving laser 100 appropriately. For example, multiple scans of the laser 100 are performed on the XY plane (e.g., multiple scans parallel to each other and to the X-axis and/or the Y-axis). In another embodiment, only some regions of wafer 1 (in the XY plane top view) are processed by laser 100 to obtain formation of 3C-SiC layer 24 only in some regions of wafer 21 and not in other regions (e.g., only in regions where active regions of devices intended to be provided/integrated in wafer 21 are to be formed). This region or regions may be spaced inwardly from the lateral sides 1c of the wafer 1.
The configuration and operating parameters of the laser 100 optimized for the purposes of the present disclosure in accordance with the embodiments of fig. 3A-3C are as follows:
wavelengths between 290nm and 370nm, in particular 310nm;
the pulse duration is between 100ns and 300ns, in particular 160ns;
the number of pulses is between 1 and 16, in particular between 1 and 10, for example 2;
the energy density is 1.6J/cm 2 To 5J/cm 2 Between, in particular 3.8J/cm 2 (considered on the surface level of the front side 1 a);
the temperature is between 2000 ℃ and 3000 ℃, in particular 2600 ℃ (considered at the level of the surface 1 a).
The area of the spot of the beam 102 at the level of the front side 1a comprises, for example, between 0.7 and 1.5cm 2 Between them.
Crystallization of the molten portion occurs in an environment at a temperature of 1600-2700 c for a time of 100ns-300ns.
Then, in fig. 3D, an oxidation step of the silicon layer 26a and the carbon-rich layer 26b is performed, similar to what has been described previously, forming corresponding oxide layers (indicated in the figure by the general reference numeral 28).
This step is performed by inserting the wafer 21 in an oxidizing atmosphere, in particular in an oxygen atmosphere, in a furnace at 800 c for 60 minutes. This facilitates oxidation of the carbon-rich layer and the silicon layer. The applicant did not observe corresponding oxidation of the 3C-SiC layer and the 4H-SiC substrate.
Then, fig. 3E, a subsequent bath, such as BOE (buffered oxide etchant), in a suitable wet etching solution allows complete removal of oxide layer 28, exposing underlying 3C-SiC layer 24.
Since the etching chemistry solution selectively removes the material of oxide layer 28, the etching is performed to completely remove oxide layer 28 without removing underlying 3C-SiC layer 24.
In another embodiment of the present disclosure, as shown in fig. 4, after performing the steps already described with reference to fig. 3A-3B, melting and subsequent recrystallization of the material of wafer 21 results in the formation of another 6H-SiC layer 29 intermediate between the 4H-SiC material of wafer 21 and 3C-SiC layer 24.
The 6H-SiC layer 29 is formed (as already discussed with reference to fig. 2) by appropriately adjusting the configuration and operating parameters of the laser 100 for emitting an appropriate beam as follows:
wavelengths between 290nm and 370nm, in particular 310nm;
the pulse duration is between 100ns and 300ns, in particular 160ns;
the number of pulses is between 1 and 16, in particular between 1 and 10, for example 2;
the energy density is 1.6J/cm 2 To 4J/cm 2 Between, in particular 2.6J/cm 2 (considered on the surface level of the front side 1 a);
the temperature is between 1400 ℃ and 2600 ℃, in particular 1800 ℃ (considered at the level of the surface 1 a).
Crystallization of the molten portion occurs in an environment having a temperature between 1600 ℃ and 2700 ℃ for a time between 100ns and 300ns.
Then, the oxidation and etching steps already described with reference to fig. 3d,3e are performed.
The advantages offered by this disclosure are apparent from a review of the features offered in accordance with the present disclosure.
In particular, 3C-SiC layers having the desired electrical characteristics of reduced band gap and high electron mobility can be fabricated in a fast and inexpensive manner and can be integrated into known industrial processes.
Furthermore, the applicant has verified that the 3C-SiC layer thus manufactured has a low defect density.
The possibility of fabricating 3C-SiC layers on 4H-SiC substrates allows the silicon carbide properties to be fully exploited.
Furthermore, the heating and melting process occurs in a single step, where the laser parameters (e.g., in terms of energy and pulse number) can be precisely controlled, making the process highly reproducible.
Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present disclosure.
A method for processing a wafer (1; 1) of 4H-SiC material can be summarized as including the step of heating selective portions at a surface (1 a,21 a) of the wafer (1) by a laser beam (102); 21 At least to the melting temperature of the material of the selective portion; crystallizing the melted selective portion to form a stack of superimposed layers, the superimposed layers comprising: a 3C-SiC layer (4; 24) is in contact with the wafer (1; 21), a silicon layer (6 a;26 a) is on the 3C-SiC layer (4; 24), and a carbon-rich layer (6 b;26 b) is on the silicon layer (6 a;26 a); and completely removing the carbon-rich layer (6 b;26 b).
The process may further include completely removing the silicon layer (6 a;26 a) to expose the 3C-SiC layer (4; 24).
The selective portion may be a crystalline 4H-SiC material, in particular single crystal 4H-SiC.
The process may further comprise the step of implanting dopants at the surface (1 a;21 a) prior to the heating step, forming an implanted region (3), and the selected portion may comprise the implanted region (3).
The heating step may be performed by generating a temperature between 1600 ℃ and 3000 ℃ at the level of the surface (1 a;21 a).
The step of allowing said molten selective partial crystallization comprises arranging wafers (1; 21); maintaining the temperature at 1600-2700deg.C for 100ns-300 s.
Removing the carbon-rich layer (6 b;26 b) may include performing a step of forming a carbon-rich layer (6 b;26 b) into a carbon oxide layer (8; 28) and a step of etching the oxidized carbon layer (8; 28).
The step of removing the silicon layer (6 a;26 a) may comprise the step of performing the silicon layer (6 a;26 a) to form a silicon oxide layer (8; 28) and the step of etching the silicon oxide layer (8; 28).
The step of oxidizing the silicon oxide layer (6 a;26 a) and oxidizing the carbon-rich layer (6 b;26 b) may be performed simultaneously and/or the etching of the silicon oxide layer (8; 28) and the etching of the carbon oxide layer (8; 28) may be performed simultaneously.
The laser beam (102) may be generated according to the following parameters:
a wavelength between 290nm and 370 nm;
the pulse duration is between 100 and 300 ns;
the number of pulses is between 1 and 16, in particular between 1 and 10, for example 2; an energy density of 1.6-5J/cm 2 。
The laser beam (102) may be generated according to the following parameters: a wavelength between 290nm and 370 nm; the pulse duration is between 100 and 300 ns; the number of pulses being between 1 and 16The method comprises the steps of carrying out a first treatment on the surface of the And 1.6-4J/cm 2 Is a high energy density.
The selected portion may have a shape and an extension corresponding to those of the wafer (1; 21) in plan view.
The selection portion may have an extension lower than that of the wafer (1; 21) in plan view.
The selective portion may extend to a maximum depth of the wafer (1; 21) of between 10 and 100 nm.
The carbon-rich layer (6; 26) may comprise one or more graphene layers and/or one or more graphite layers.
The process may further comprise forming a 6H-SiC layer (9; 29) interposed between the 4H-SiC material of the wafer (1; 21) and the 3C-SiC layer (4; 24), said laser beam (102) being generated according to the following parameters: a wavelength between 290nm and 370 nm; the pulse duration is between 100 and 300 ns; the number of pulses is between 1 and 16, in particular between 1 and 10; 1.6-4J/cm 2 Is a high energy density.
The various embodiments described above may be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to employ concepts of the various patents, applications and publications to provide yet further embodiments.
These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the present disclosure.
Claims (20)
1. A method, comprising:
processing a wafer, comprising:
heating a selective portion at a surface of the wafer with a laser beam at least up to a melting temperature of a material at the selective portion;
allowing the selective portion to crystallize after melting, thereby forming a stack of superimposed layers comprising:
a 3C-SiC layer in contact with the 4H-SiC material of the wafer, a silicon layer on the 3C-SiC layer, and a carbon-rich layer on the silicon layer; and
the carbon-rich layer is completely removed.
2. The method of claim 1, further comprising exposing the 3C-SiC layer by completely removing the silicon layer.
3. The method of claim 1, wherein the selective portion comprises a crystalline 4H-SiC material.
4. The method of claim 1, further comprising: an implant region is formed in the selective portion by implanting dopants at the surface prior to heating the selective portion with the laser beam.
5. The method of claim 1, wherein heating with the laser beam is performed by generating a temperature between 1600 ℃ and 3000 ℃ at a level of the surface.
6. The method of claim 1, wherein allowing the selective portion to crystallize after melting comprises disposing the wafer in an environment having a temperature between 1600 ℃ and 2700 ℃ for a time between 100ns and 300 s.
7. The method of claim 1, wherein removing the carbon-rich layer comprises:
performing oxidation on the carbon-rich layer, thereby forming a carbon oxide layer; and
etching the carbon oxide layer.
8. The method of claim 7, wherein removing the silicon layer comprises:
performing oxidation on the silicon layer, thereby forming a silicon oxide layer; and
etching the silicon oxide layer.
9. The method of claim 8, wherein the oxidizing of the silicon layer and the oxidizing of the carbon-rich layer are performed simultaneously; and is also provided with
Wherein etching the silicon oxide layer and etching the carbon oxide layer are performed simultaneously.
10. The method of claim 8, wherein etching the silicon oxide layer and etching the carbon oxide layer are performed simultaneously.
11. The method of claim 8, wherein the oxidizing of the silicon layer and the oxidizing of the carbon-rich layer are performed simultaneously.
12. A method according to claim 3, wherein the laser beam is generated according to the following parameters:
a wavelength between 290nm and 370 nm;
the pulse duration is between 100 and 300 ns;
the number of pulses is between 1 and 16; and
the energy density is 1.65J/cm 2 -5J/cm 2 Between them.
13. The method of claim 4, wherein the laser beam is generated according to the following parameters:
a wavelength between 290nm and 370 nm;
the pulse duration is between 100 and 300 ns;
the number of pulses is between 1 and 16; and
the energy density is 1.6J/cm 2 -4J/cm 2 Between them.
14. The method of claim 1, wherein the selective portion extends into the wafer up to a maximum depth between 10nm and 100 nm.
15. The method of claim 1, wherein the carbon-rich layer comprises at least one of: one or more graphene layers, one or more graphite layers, and one or more graphene and one or more graphite layers.
16. The method of claim 1, further comprising forming a 6H-SiC layer interposed between the 4H-SiC material and the 3C-SiC layer of the wafer by generating the laser beam according to:
a wavelength between 290nm and 370 nm;
the pulse duration is between 100 and 300 ns;
the number of pulses is between 1 and 16; and
the energy density is 1.6J/cm 2 -4J/cm 2 Between them.
17. A method, comprising:
forming a doped layer on a wafer, the wafer comprising a first silicon carbide polytype layer;
heating the doped layer to a melting point of the doped layer with a laser beam;
after heating the doped layer to the melting point, crystallizing the melted portion of the doped layer into a carbon-rich layer and a silicon layer, and thereby forming a second silicon carbide polytype layer;
forming a carbon oxide layer by oxidizing the carbon-rich layer;
forming a silicon oxide layer by oxidizing the silicon layer;
removing the carbon oxide layer by etching the carbon oxide layer; and
the silicon oxide layer is removed by etching the silicon oxide layer.
18. The method according to claim 17, wherein:
the first silicon carbide polytype layer is at least one of: 4H-silicon carbide polytype layer and 6H-silicon carbide polytype layer;
the second silicon carbide polytype layer is a 3C-silicon carbide polytype layer;
forming the carbon oxide layer and forming the silicon oxide layer occur simultaneously with each other; and
the removing of the silicon oxide layer and the removing of the silicon oxide layer occur simultaneously with each other.
19. A method, comprising:
forming a doped layer on a wafer, the wafer comprising a first silicon carbide polytype layer;
forming a second silicon carbide polytype layer and a third silicon carbide polytype layer by heating the doped layer with a laser beam to the melting point of the doped layer, the second silicon carbide polytype layer being located between the first silicon carbide polytype layer and the third silicon carbide polytype layer;
after heating the doped layer to the melting point, crystallizing a molten portion of the doped layer into a carbon-rich layer and a silicon layer;
forming a carbon oxide layer by oxidizing the carbon-rich layer;
forming a silicon oxide layer by oxidizing the silicon layer;
removing the carbon oxide layer by etching the carbon oxide layer; and
the silicon oxide layer is removed by etching the silicon oxide layer.
20. The method according to claim 19, wherein:
the first silicon carbide polytype layer is a 4H-silicon carbide polytype layer;
the second silicon carbide polytype layer is a 6H-silicon carbide polytype layer;
the third silicon carbide polytype layer is a 3C-silicon carbide polytype layer;
forming the carbon oxide layer and forming the silicon oxide layer occur simultaneously with each other; and
the removal of the silicon oxide layer and the removal of the silicon oxide layer occur simultaneously with each other.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT102022000005357 | 2022-03-18 | ||
| US18/181,415 US20230298887A1 (en) | 2022-03-18 | 2023-03-09 | Process for working a wafer of 4h-sic material to form a 3c-sic layer in direct contact with the 4h-sic material |
| US18/181,415 | 2023-03-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116779451A true CN116779451A (en) | 2023-09-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310260665.5A Pending CN116779451A (en) | 2022-03-18 | 2023-03-17 | Method for forming 3C-SIC layer in direct contact with 4H-SIC material |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116779451A (en) |
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2023
- 2023-03-17 CN CN202310260665.5A patent/CN116779451A/en active Pending
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