JP5127235B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device in which the lifetime of carriers is adjusted by intentionally forming crystal defects and a method for manufacturing the same.

A technique for controlling the lifetime of carriers (electrons and holes) of a semiconductor device is known. For example, Patent Document 1 discloses a PN diode in which crystal defects are formed in the vicinity of a pn junction interface by implanting protons. Crystal defects serve as carrier recombination centers. Therefore, when crystal defects are formed in the PN diode, the carrier lifetime is shortened. By controlling the amount of crystal defects formed in the PN diode, it is possible to control the change pattern with respect to time of the current flowing through the PN diode during reverse recovery that appears after the PN diode is turned off.
Also, in an IGBT (Insulated Gate Bipolar Transistor) which is a bipolar transistor, a technique is known in which crystal defects are formed in the drift region by implanting charged particles, thereby shortening the turn-off time.
As exemplified above, a technique for adjusting the characteristics of a semiconductor device by intentionally forming a crystal defect in a semiconductor crystal constituting a semiconductor device (for example, a PN diode, an IGBT, or the like) is known.
In semiconductor crystals, there are crystal defects formed unintentionally during crystal growth (during crystal ingot production) or the like. In order to distinguish a crystal defect formed unintentionally from a crystal defect intentionally formed by implanting charged particles or the like, in the following description, the crystal defect formed intentionally is referred to as a formation defect.

JP-A-8-102545

The silicon crystal constituting the semiconductor device contains impurities introduced intentionally and impurities mixed unintentionally during the growth of the crystal. In order to distinguish the two, in the following description, the former impurity is referred to as a dopant impurity, and the latter impurity is referred to as a mixed impurity.
When charged particles are implanted into a silicon crystal containing mixed impurities, two types of formation defects are generally formed. That is, a vacancy-type defect in which atoms do not exist at lattice points (sites) in the silicon crystal and an interstitial-type defect formed by impurities mixed in the silicon crystal are formed.
For example, when charged particles are implanted into a silicon crystal containing carbon and oxygen, the following reaction occurs. First, by the implantation of charged particles, silicon existing at lattice points is ejected to the interstitial positions, and vacancies are formed at the lattice points. As a result, a large number of vacancy-type defects and interstitial silicon are generated in the crystal. The generated vacancy-type defects are in a stable state when they have a predetermined positional relationship with other vacancy-type defects. Thereby, a VV defect constituted by two hole type defects is formed. In addition, the silicon that is ejected to the interstitial position is replaced with the carbon existing at the lattice point in the crystal. That is, the carbon at the lattice point moves to the interstitial position, and the silicon at the interstitial position moves to the lattice point. The carbon that has moved to the interstitial position becomes stable when it has a predetermined positional relationship with oxygen present at the interstitial position in the crystal. As a result, C _i O _i defects constituted by carbon at interstitial positions and oxygen at interstitial positions are formed.

Thus, when charged particles are implanted into a silicon crystal, VV defects and defects due to mixed impurities (for example, C _i O _i defects formed by carbon and oxygen) are formed. These defects all act as carrier recombination centers. Therefore, the lifetime of carriers can be changed by forming defects due to VV defects and mixed impurities in the silicon crystal. In other words, the characteristics of the semiconductor device can be adjusted to appropriate characteristics by appropriately controlling the amount of defects formed by VV defects and mixed impurities.

  The amount of VV defects formed in the silicon crystal when charged particles are implanted can be controlled by the amount of charged particles implanted. On the other hand, the amount of defects due to mixed impurities also depends on the amount of mixed impurities in the silicon crystal to which charged particles are to be implanted. That is, defects due to mixed impurities are likely to be formed in silicon crystals having a high concentration of mixed impurities, and defects due to mixed impurities are difficult to form in silicon crystals having a low concentration of mixed impurities. The concentration of impurities contained in the silicon crystal varies greatly from silicon crystal ingot to silicon ingot. Even in the same ingot, the concentration of mixed impurities varies depending on the site. Therefore, the amount of defects formed due to the mixed impurities formed by implanting charged particles varies greatly for each silicon substrate. As a result, the amount of formation defects formed in the silicon crystal (the total amount of defects due to VV defects and mixed impurities) also varies from silicon substrate to silicon substrate. If the amount of formation defects varies, the characteristics of the manufactured semiconductor device will vary. The conventional technique has a problem that the variation in characteristics of the manufactured semiconductor device is large.

  The present invention has been made in view of the above-described circumstances, and a manufacturing method for mass-producing a group of semiconductor devices with little variation between semiconductor devices when forming formation defects in a silicon crystal to adjust the characteristics of the semiconductor devices. The purpose is to provide.

In the manufacturing method of the present invention, a semiconductor device including a crystal defect region in which crystal defects are formed in a predetermined range is manufactured. This manufacturing method includes an interstitial silicon generation step of generating interstitial silicon in the predetermined range by implanting silicon ions with energy that is injected into the predetermined range from the surface of the silicon substrate, and silicon that has undergone the interstitial silicon generation step. There is provided a crystal defect forming step of forming a crystal defect in the predetermined range by implanting charged particles with energy that is implanted into the predetermined range from the surface of the substrate.
When silicon ions are implanted into the predetermined range in the interstitial silicon generation step, the number of silicon existing in the predetermined range increases. At this time, since the number of silicon that can exist at the lattice point is determined, most of the increased silicon is interstitial silicon. Interstitial silicon is energetically unstable by itself. However, it becomes stable when a plurality of interstitial silicons gather. Therefore, many clusters (aggregates) of interstitial silicon exist within the predetermined range after the interstitial silicon generation step is performed.
After the interstitial silicon generation step, a crystal defect formation step is performed. In the crystal defect forming step, charged particles are implanted in a range where many clusters of interstitial silicon exist. When charged particles are implanted, the silicon existing at the lattice points in the silicon crystal is ejected to the interstitial positions and becomes interstitial silicon. By this reaction, vacancies are formed at lattice points, and VV defects are formed in the silicon crystal. In addition, the interstitial silicon generated by this reaction becomes a part of a cluster of interstitial silicons present in a large number in the silicon crystal and becomes a stable state. Therefore, the interstitial silicon hardly reacts with the mixed impurities (for example, the position is switched). For this reason, it is difficult to form defects due to mixed impurities. For example, the silicon atoms and oxygen are present as mixed impurities crystals, since the reaction where the position of the carbon present in interstitial silicon lattice points generated by the charged particles are driven are switched becomes difficult to occur, C _i O _i defects are hardly formed.
As described above, according to this manufacturing method, most of the formed crystal defects (formation defects) are VV defects. As described above, the amount of VV defect formation can be accurately controlled by the amount of charged particles to be implanted. Therefore, according to this manufacturing method, the amount of crystal defects (formation defects) to be formed can be stabilized despite variations in the concentration of mixed impurities contained in the silicon substrate. It is possible to mass-produce semiconductor device groups with little variation in characteristics between semiconductor devices.

The present invention also provides another manufacturing method that can solve the above-described problems. This manufacturing method uses a silicon substrate on which a concentration profile that increases as the concentration of interstitial silicon increases from one surface to the other surface by crystal growth while changing the pulling rate during ingot manufacturing. A semiconductor device having a crystal defect region in which crystal defects are formed is manufactured. This manufacturing method includes a crystal defect forming step of forming a crystal defect in the surface portion by implanting charged particles from the surface having the higher interstitial silicon concentration of the silicon substrate with energy remaining in the surface portion. .
A large number of interstitial silicon clusters exist on the surface portion of the silicon substrate where the concentration of interstitial silicon is higher. In the crystal defect forming step, a crystal defect is formed on the surface portion of the silicon substrate having a higher interstitial silicon concentration by implanting charged particles. Therefore, most of the formation defects formed on the surface portion are VV defects. Also by this manufacturing method, the amount of formation defects can be accurately controlled, and a semiconductor device group with little variation can be mass-produced.

The present invention also provides a method of manufacturing a PN diode having a crystal defect region in which crystal defects are formed in a predetermined range. In this manufacturing method, a dopant impurity is introduced into a silicon substrate to form a pn junction within the predetermined range, and silicon ions are implanted with energy that is implanted into the predetermined range from the surface of the silicon substrate. The interstitial silicon generation step for generating interstitial silicon in the predetermined range, and crystal defects in the predetermined range by implanting charged particles with the energy that is injected into the predetermined range from the surface of the silicon substrate that has undergone the interstitial silicon generation step And a crystal defect forming step of forming.
According to this manufacturing method, the amount of formation defects can be accurately controlled, and PN diode groups with little variation can be mass-produced.

The present invention also provides a method for manufacturing a further PN diode. This manufacturing method uses a silicon substrate on which a concentration profile that increases as the concentration of interstitial silicon increases from one surface to the other by growing crystals while changing the pulling rate during ingot manufacture. Then, a PN diode having a crystal defect region in which crystal defects are formed is manufactured. In this manufacturing method, a dopant impurity is introduced into the silicon substrate to form a pn junction in a surface portion of the silicon substrate having a higher interstitial silicon concentration, and interstitial silicon of the silicon substrate. A crystal defect forming step of forming a crystal defect in the surface portion by implanting charged particles with energy remaining in the surface portion from the surface having a higher concentration of.
Also by this manufacturing method, the amount of formation defects can be accurately controlled, and PN diode groups with little variation can be mass-produced.

The present invention also provides a method for manufacturing an IGBT including a crystal defect region in which crystal defects are formed in a predetermined range. In this manufacturing method, a dopant region is introduced from the upper surface side of the silicon substrate to form a body region and an emitter region, and a dopant region is introduced from the lower surface side of the silicon substrate to form a collector region. A lower surface side introducing step for forming an interface between the collector region and the drift region on the lower surface portion, and interstitial silicon in the predetermined range by implanting silicon ions with energy to be injected into the predetermined range from the surface of the silicon substrate. And a crystal defect forming step of forming a crystal defect in the predetermined range by implanting charged particles with energy that is injected into the predetermined range from the surface of the silicon substrate on which the interstitial silicon generation step is performed. It has.
According to this manufacturing method, the amount of formation defects can be accurately controlled, and an IGBT group with little variation can be mass-produced.

The present invention also provides a further method for manufacturing an IGBT. In this manufacturing method, crystal defects are generated by using a silicon substrate on which a concentration profile in which the concentration of interstitial silicon increases from the upper surface toward the lower surface is formed by growing crystals while changing the pulling speed during ingot manufacturing. An IGBT having the formed crystal defect region is manufactured. In this manufacturing method, a dopant region is introduced from the upper surface side of the silicon substrate to form a body region and an emitter region, and a collector region is formed by introducing a dopant impurity from the lower surface side of the silicon substrate. A lower surface side introducing step for forming an interface between the collector region and the drift region in the lower surface portion, and by implanting charged particles from the lower surface side of the silicon substrate with energy remaining in the surface portion, A crystal defect forming step for forming defects is provided.
Also by this manufacturing method, the amount of formation defects can be accurately controlled, and an IGBT group with little variation can be mass-produced.

One embodiment of a semiconductor device disclosed in this specification includes a crystal defect region formed by implanting charged particles. The predetermined range of the silicon substrate of this semiconductor device has a higher concentration of interstitial silicon than outside the predetermined range, and the region having the highest crystal defect concentration among the crystal defect regions is formed in the predetermined range. ing.
In this semiconductor device, formation defects are formed in a range where the concentration of interstitial silicon is high. Therefore, many of the formation defects formed in the range are VV defects. Therefore, a semiconductor device group with little variation is provided.

Another embodiment of the semiconductor device disclosed in this specification has a concentration profile in which the concentration of interstitial silicon increases from one surface of the silicon substrate to the other surface, and the crystal defect region is silicon. It is characterized by being formed on the surface portion of the substrate where the interstitial silicon concentration is higher.
In this semiconductor device, the crystal defect region is formed on the surface portion of the silicon substrate having the higher interstitial silicon concentration. Therefore, many of the formation defects formed on the surface portion are VV defects. Therefore, a semiconductor device group with little variation is provided.

One embodiment of a PN diode disclosed herein comprises an anode region, a drift region in contact with the anode region, and a cathode region in contact with the drift region, wherein the dopant impurity concentration in the drift region is the anode. There is a crystal defect region formed by implanting charged particles, which is lower than the dopant impurity concentration in the region and the cathode region. Then, the concentration of interstitial silicon is higher within the predetermined range of the silicon substrate than outside the predetermined range, the pn junction is formed within the predetermined range, and the concentration of crystal defects in the crystal defect region is The highest region is formed in the predetermined range.
In this PN diode, formation defects are formed in a range where the concentration of interstitial silicon is high. Therefore, a PN diode group with little variation is provided.

Another embodiment of the PN diode disclosed herein comprises an anode region, a drift region in contact with the anode region, and a cathode region in contact with the drift region, wherein the dopant impurity concentration in the drift region Is lower than the dopant impurity concentration of the anode region and the cathode region, and has a crystal defect region formed by implanting charged particles. A concentration profile is formed in which the concentration of interstitial silicon increases from one surface of the silicon substrate to the other surface, and a pn junction is formed on the surface portion of the silicon substrate where the concentration of interstitial silicon is higher. The crystal defect region is formed in the surface portion of the silicon substrate having a higher interstitial silicon concentration.
In this PN diode, the crystal defect region is formed on the surface portion of the silicon substrate having the higher interstitial silicon concentration. Therefore, a PN diode group with little variation is provided.

One embodiment of the IGBT disclosed herein includes a crystal defect region formed by implanting charged particles. The first conductivity type collector region, the second conductivity type drift region in contact with the collector region, the first conductivity type body region in contact with the drift region, and the drift region are separated from the drift region by the body region. An emitter region of the second conductivity type, and a gate electrode facing the body region separating the emitter region and the drift region via an insulating film, and a predetermined range of the drift region is within the predetermined range The concentration of interstitial silicon is higher than that of the outer silicon substrate, and a stacked structure of a collector region and a drift region is formed within the predetermined range, and the concentration of crystal defects is the highest among the crystal defect regions. The region is formed in the predetermined range.
In this IGBT, formation defects are formed in a range where the concentration of interstitial silicon is high. Therefore, an IGBT group with little variation is provided.

Another embodiment of the IGBT disclosed in this specification includes a crystal defect region formed by implanting charged particles. The first conductivity type collector region, the second conductivity type drift region in contact with the collector region, the first conductivity type body region in contact with the drift region, and the drift region are separated from the drift region by the body region. An emitter region of the second conductivity type, and a gate electrode facing the body region separating the emitter region and the drift region through an insulating film, and the interstitial silicon concentration is one of the silicon substrates A concentration profile that increases from the surface toward the other surface is formed, and a stacked structure of a collector region and a drift region is formed on the surface portion of the silicon substrate where the interstitial silicon concentration is higher. Is arranged on the surface side where the concentration of interstitial silicon is higher, and the drift region is arranged on the deep side. The highest region is the concentration of crystal defects, characterized in that it is formed in the drift region near the interface of the collector region and the drift region.
In this IGBT, crystal defects are formed on the surface portion of the silicon substrate having a higher interstitial silicon concentration. Therefore, an IGBT group with little variation is provided.

In the above-described IGBT, it is preferable that a buffer region having a higher concentration of the second conductivity type impurity than the drift region outside the drift region is formed in a region in contact with the collector region in the drift region.
According to such a configuration, the breakdown voltage characteristics of the IGBT can be improved.

The main features of the embodiments described in detail below are listed first.
(Feature 1) The semiconductor device further includes an interstitial silicon stabilization step of stabilizing the interstitial silicon by heat-treating the silicon substrate subjected to the interstitial silicon generation step.
(Characteristic 2) It further includes an unstable defect removing step of removing unstable crystal defects by heat-treating the silicon substrate subjected to the crystal defect forming step.
(Feature 3) The heat treatment in the interstitial silicon stabilization step is performed at a higher temperature than the heat treatment in the unstable defect removal step.
(Feature 4) The interstitial silicon stabilization step is performed before the unstable defect removal step.

(First embodiment)
A semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a schematic configuration of the PN diode 10a of the first embodiment.
As shown in the figure, the PN diode 10a includes a silicon substrate 12, an anode electrode 20 formed on the upper surface 12a of the silicon substrate 12, and a cathode electrode 22 formed on the lower surface 12b. The silicon substrate 12 is mainly made of silicon. A p-type diffusion layer (anode layer: p ⁺ layer) 14 containing a p-type impurity (boron in this embodiment) is formed on the upper surface 12a side of the silicon substrate 12. The p-type diffusion layer 14 is in ohmic contact with the anode electrode 20. An n-type drift layer (n ⁻ layer) 16 containing an n-type impurity (phosphorus in the present embodiment) is formed on the lower surface side of the p-type diffusion layer 14. Therefore, the interface between the p-type diffusion layer 14 and the n-type drift layer 16 is a pn junction interface 30. On the lower surface 12b side of the n-type drift layer 16, an n-type diffusion layer (cathode layer: n ⁺ layer) 18 containing an n-type impurity at a high concentration is formed. The n-type diffusion layer 18 is in ohmic contact with the cathode electrode 22.

In the silicon crystal, there is interstitial silicon existing at interstitial positions in addition to silicon existing at lattice points (sites). Interstitial silicon is unstable by itself. However, it becomes stable when a plurality of interstitial silicons gather. Accordingly, in the silicon crystal, the interstitial silicon exists as a cluster (aggregate) in which a plurality of interstitial silicons are aggregated.
A high concentration field 26 in which the concentration of interstitial silicon is locally increased is formed in the silicon substrate 12. FIG. 2A shows the distribution of the interstitial silicon concentration N1 in the thickness direction in the silicon substrate 12 (the direction of the arrow V1 in FIG. 1). 2A indicates the position (depth) in the thickness direction of the silicon substrate 12a, the origin is the position of the upper surface 12a of the silicon substrate 12, and the right end of the horizontal axis is the lower surface 12b of the silicon substrate 12. Indicates the position. Further, a position A1 in FIG. 2A indicates the position of the pn junction interface 30.
As shown in the drawing, the concentration of interstitial silicon in the region between the positions A2 and A3 is about 10 ¹⁴ atoms / cm ³ , and the concentration of interstitial silicon is higher than that outside the region (outside the region). The concentration of interstitial silicon is about 10 ¹³ atoms / cm ³ ). That is, the region between the position A2 and the position A3 is a high concentration field 26 in which the concentration of interstitial silicon is high. The high concentration field 26 is formed in the n-type drift layer 16 near the pn junction interface 30.

  In the silicon substrate 12, there are many crystal defects (hereinafter referred to as formation defects) intentionally generated in the manufacturing process. Hereinafter, a region where a crystal defect exists is referred to as a crystal defect region. FIG. 2B shows a distribution of the concentration N2 of formation defects in the thickness direction in the silicon substrate 12 (the direction of the arrow V1 in FIG. 1). The horizontal axis in FIG. 2B corresponds to the horizontal axis in FIG. As shown in the figure, the formation defect exists in the surface portion of the silicon substrate 12 on the upper surface 12a side. That is, the crystal defect region is formed on the upper surface 12 a side of the silicon substrate 12. Most of the formation defects are formed in the high concentration field 26, and a region having the highest crystal defect concentration among the crystal defect regions is also formed in the high concentration field 26.

As will be described later, these formation defects are generated by implanting helium ions into the silicon substrate 12. There are generally two types of defects formed in the crystal by implanting helium ions.
The first defect is a C _i O _i defect. The C _i O _i defect is constituted by oxygen existing at an interstitial position in the crystal (hereinafter referred to as interstitial oxygen O _i ) and carbon existing at the interstitial position (hereinafter referred to as interstitial carbon C _i ). Is done. When the interstitial oxygen O _i and the interstitial carbon C _i are in a specific positional relationship, a C _i O _i defect occurs. The C _i O _i defect has a property of becoming a recombination center of carriers. Further, the C _i O _i defect has a property of trapping holes in the silicon substrate 12.
The second defect is a VV defect. VV defects are constituted by vacancies at lattice points (sites) in the crystal. If the two holes are in a specific positional relationship, a VV defect occurs. VV defects have the property of becoming recombination centers of carriers. However, the VV defect has a property of trapping electrons in the silicon substrate 12 and not trapping holes.
In the PN diode 10a of the present embodiment, most of the formation defects existing in the high concentration field 26 are VV defects. The amount of formation defects existing in the high concentration field 26 is adjusted to an appropriate amount. In the PN diode 10a, as shown in FIG. 2, most of the formation defects exist in the high concentration field 26, and the formation defects existing outside the high concentration field 26 are very few.

  In general, the amount of formation defects present in the silicon substrate 12 affects the characteristics of the PN diode. FIG. 3 shows the characteristics at the time of turn-off of two PN diodes having the same structure as the PN diode 10a and having different formation defects. More specifically, when a predetermined voltage (forward voltage) is applied between the anode electrode and the cathode electrode and a predetermined reverse voltage is applied at time t0, the current I1 flowing through the PN diode with respect to time t The change pattern is shown. A graph C1 in FIG. 3 shows the characteristics of a PN diode having a large amount of formation defects existing in the high concentration field 26, and a graph C2 shows a characteristic of a PN diode having a small amount of formation defects existing in the high concentration field 26. Is shown.

  As shown in FIG. 3, the current IF flows in the forward direction in any PN diode while the forward voltage is applied. When a reverse voltage is applied to the PN diode at time t0, the current I1 decreases and thereafter a reverse current flows. The reverse current once increases and then decreases with a decrease in carriers remaining in the silicon substrate 12. Thereafter, the reverse current becomes zero.

As can be seen from FIG. 3, the change characteristic of the reverse current is affected by the amount of formation defects. As described above, the formation defect becomes a carrier recombination center. Therefore, when the amount of formation defects is large, carriers are easily recombined and disappear. On the other hand, when the amount of formation defects is small, carriers are difficult to recombine. Therefore, as shown in the graph C2 of FIG. 2, the PN diode with a small amount of formation defects is unlikely to attenuate the reverse current.
As for the characteristics of the PN diode, it is preferable that the peak value of the reverse current is low and the current change rate during reverse current recovery is small. If the peak value of the reverse current is low, the loss at the turn-off time of the PN diode can be reduced. If the current change rate at the time of reverse current recovery is small, the surge voltage applied to the pn junction interface 30 can be reduced due to the influence of the current change rate and the parasitic inductance. In the PN diode 10a of this embodiment, an appropriate amount of formation defects is formed at the time of manufacture. Therefore, the peak value of the reverse current is suppressed to an appropriate value, and the current change rate at the time of reverse current recovery is also an appropriate change rate. Therefore, the loss due to the reverse current does not increase so much, and an excessive surge voltage is suppressed from being applied to the pn junction interface 30 when the reverse current is recovered.

As described above, the formation defects include two types of defects, C _i O _i defects and VV defects. The C _i O _i defect has a property of trapping holes. If a C _i O _i defect exists in the vicinity of the pn junction interface 30 of the PN diode, holes are trapped by the C _i O _i defect when a current flows in the forward direction. Therefore, a large number of holes exist in the vicinity of the pn junction interface 30. In this state, when the voltage applied to the PN diode is turned off, a reverse voltage is applied to the pn junction interface 30 as described above. When a reverse voltage is applied to the pn junction interface 30, the depletion layer tends to spread from the pn junction interface 30 toward the anode electrode side and the cathode electrode side. However, the spread of the depletion layer is suppressed by holes trapped by C _i O _i defects in the vicinity of the pn junction interface 30. Then, strong electric field concentration occurs in the vicinity of the pn junction interface 30, and avalanche breakdown is likely to occur. That is, the PN diode in which many C _i O _i defects exist has a drawback that the avalanche breakdown voltage is low.
In the PN diode 10a of the first embodiment, most of the formation defects are formed in the high concentration field 26, and most of the formation defects formed in the high concentration field 26 are VV defects. That is, there are very few C _i O _i defects. Therefore, the PN diode 10a is unlikely to breakdown at the time of turn-off.

  Next, a manufacturing method of the PN diode 10a will be described based on the flowchart of FIG. The PN diode 10a is manufactured from a silicon wafer made of n-type silicon. A layer containing phosphorus in a high concentration (that is, the n-type diffusion layer 18) is formed in advance on the surface portion of the silicon wafer on the lower surface 12b side. The upper surface 12 a and the lower surface 12 b of the silicon wafer are polished in a mirror shape so that the thickness of the silicon wafer is substantially the same as that of the silicon substrate 12. Carbon and oxygen are present in the silicon wafer. The concentrations of carbon and oxygen in the silicon wafer vary greatly depending on the silicon wafer.

  In step S2, boron, which is a p-type impurity, is implanted from the upper surface 12a side of the silicon wafer to increase the boron concentration in a region (region corresponding to the p-type diffusion layer 14) from the upper surface 12a of the silicon wafer to a predetermined depth. . When boron is implanted in step S2, crystal defects are formed in the silicon wafer.

  In step S4, the silicon wafer is heat treated. Thereby, boron implanted into the silicon wafer is diffused and activated. That is, boron diffuses near the region where boron is implanted in step S2 and is activated. As a result, the region where boron is diffused becomes the p-type diffusion layer 14. Further, the region between the p-type diffusion layer 14 and the n-type diffusion layer 18 becomes the n-type drift layer 16. By executing step S4, the crystal defects formed in the silicon wafer in step S2 are almost eliminated.

  In step S6, silicon ions are implanted into the silicon wafer from the upper surface 12a side. At this time, silicon ions are implanted with energy that the implanted silicon ions remain in the n-type drift layer 16 in the vicinity of the pn junction interface 30 (that is, a range corresponding to the high concentration field 26). As a result, the concentration of silicon in the range increases, and a large number of interstitial silicon is generated in the range. If silicon ions are implanted in step S6, crystal defects are formed in the silicon wafer.

  In step S8, the silicon wafer is heat treated. Specifically, the silicon wafer is held at a temperature of 600 ° C. for about 1 hour. As a result, the interstitial silicon generated in step S6 diffuses, and the interstitial silicon clusters are dispersed and exist. This makes the interstitial silicon more stable. A region where the interstitial silicon is diffused becomes a high concentration field 26. Also, the crystal defects formed in the silicon wafer in step S6 are almost eliminated by this heat treatment.

  In step S10, the anode electrode 20 is formed on the upper surface 12a of the silicon wafer by vapor deposition.

  In step S12, helium ions are implanted from the upper surface 12a side of the silicon wafer. Thereby, crystal defects (formation defects) are formed in the silicon wafer. In step S12, the energy for implanting helium ions is adjusted so that most of the formation defects are formed in the high concentration field 26. As a result, formation defects are formed in the silicon wafer with the concentration distribution shown in FIG.

When helium ions are implanted into a silicon wafer, the following reaction occurs in the silicon wafer.
(Reaction 1) Si _s → V + Si _i
(Reaction 2) V + V → VV defects (Reaction _{3) Si i + Si i n} → Si i n + 1
(Reaction 4) Si _i + C _s → C _i
(Reaction 5) In the C _i + O _i → C _i O _i defect (reaction 1), silicon (Si _s ) existing at the lattice point in the crystal lattice is ejected from the lattice point to the interstitial position by the implantation of helium ions. Thereby, interstitial silicon (Si _i ) is generated, and lattice points after the silicon is ejected become vacancies (V). When (Reaction 1) occurs frequently in the silicon wafer, a large number of interstitial silicon (Si _i ) and a large number of vacancies (V) are generated in the silicon wafer. Since silicon (Si _i ) and vacancies (V) at interstitial positions are unstable in energy state, (Reaction 2) to (Reaction 5) occur.
In (Reaction 2), the two vacancies (V) generated by (Reaction 1) are in a predetermined positional relationship in the crystal lattice and are in a stable state. That is, a VV defect is formed.
In (Reaction 3), the interstitial silicon (Si _i ) generated by (Reaction 1) is taken into a cluster (Si _{i n} ) of interstitial silicon existing in the silicon wafer, and is in a stable state. . That is, to join a new one interstitial silicon interstitial silicon clusters _{(Si i n) (Si i} ) becomes the cluster of larger interstitial silicon _{(Si i n + 1).}
In (Reaction 4), the positions of carbon (C _s ) present as impurities at lattice points in the crystal lattice and silicon (Si _i ) at the interstitial positions generated in (Reaction 1) are interchanged. As a result, carbon (C _i ) existing at interstitial positions is generated. Since carbon (C _i ) at the interstitial position is unstable in energy state, (Reaction 5) occurs.
In (Reaction 5), carbon (C _i ) at the interstitial position generated in (Reaction 4) and oxygen (O _i ) present as a mixed impurity at the interstitial position in the crystal lattice have a predetermined positional relationship. , Become stable. That is, C _i O _i defects are formed.
As described above, when helium ions are implanted into a silicon wafer, VV defects and C _i O _i defects are formed in the silicon wafer.

As can be seen from the above reaction equation, (Reaction 1) and (Reaction 2) occur according to the amount of helium ions implanted. Therefore, the amount of VV defects formed can be adjusted by the amount of helium ions implanted.
In addition, the interstitial silicon (Si _i ) generated by (Reaction 1) is incorporated into the interstitial silicon cluster (Si _{i n} ) by (Reaction 3), (Reaction 4) and (Reaction 5). There is something that causes.
As described above, many clusters of interstitial silicon exist in the high concentration field 26. Therefore, (Reaction 3) is very likely to occur. That is, most of the interstitial silicon generated in (Reaction 1) is taken into the clusters of interstitial silicon by (Reaction 3). Therefore, in the high concentration field 26, (Reaction 4) and (Reaction 5) hardly occur. In other words, C _i O _i defects are hardly formed in the high concentration field 26. Therefore, a large number of VV defects are formed in the silicon wafer without forming much C _i O _i defects.
When helium ions are implanted into a silicon wafer, VV defects and C _i O _i defects are formed, and various formation defects with unstable energy states are also formed.

  In step S14, the silicon wafer is heat treated. Specifically, the silicon wafer is held at a temperature of 400 ° C. for about 1 hour. When the silicon wafer is heat-treated under these conditions, the formation defects with unstable energy states existing in the silicon wafer disappear, and VV defects with stable energy states remain in the silicon wafer. That is, most of the formation defects in the silicon wafer are VV defects.

  In step S16, the cathode electrode 22 is formed on the lower surface 12b of the silicon wafer by vapor deposition.

  In step S18, the silicon wafer is divided into a plurality of pieces by dicing. Thus, a plurality of PN diodes 10a are manufactured.

As described above, in this manufacturing method, the high concentration field 26 is formed on the silicon wafer by implanting silicon ions. Then, formation defects are formed in the high concentration field 26 by implanting helium ions. In the high-concentration field 26, since a large number of interstitial silicon aggregates are formed, it is difficult to form C _i O _i defects. Therefore, most of the formation defects are VV defects. The amount of VV defects can be accurately controlled by the amount of helium ions implanted. Therefore, the amount of formation defects (total amount of VV defects and C _i O _i defects) can be accurately controlled regardless of the concentration of carbon and oxygen in the silicon wafer. That is, according to this manufacturing method, the characteristics at the time of reverse current recovery of the manufactured PN diode 10a can be accurately controlled, and variations in the characteristics at the time of reverse current recovery of the manufactured PN diode 10a can be reduced. .

In addition, according to this manufacturing method, VV defects can be formed without forming too many C _i O _i defects. Therefore, it is possible to manufacture the PN diode 10a in which the characteristic at the time of reverse current recovery is adjusted to an appropriate characteristic and the avalanche breakdown is difficult to occur at the time of turn-off.

Further, in this manufacturing method, the interstitial silicon generated in step S6 is stabilized by the heat treatment in step S8. The heat treatment in step S8 is performed at a higher temperature than the heat treatment in step S14. Therefore, the change of the state of the interstitial silicon is suppressed by the heat treatment in step S14. Therefore, according to this manufacturing method, the characteristics at the time of reverse current recovery of the PN diode 10a can be controlled more accurately.
Moreover, step S8 is implemented before step S14. Therefore, after the execution of step S14, a heat treatment at a temperature higher than that of step S14 is performed, and the VV defects remaining on the silicon wafer after step S14 are prevented from disappearing.

  In the manufacturing method of the first embodiment, the high concentration field 26 is formed in a part of the n-type drift layer 16, but the high concentration field may be formed in another part. Further, the concentration of interstitial silicon in the entire silicon wafer may be increased. Even with such a configuration, it is possible to suppress variations in characteristics during recovery of the reverse current of the PN diode 10a by forming formation defects in a range where the concentration of interstitial silicon is high.

  In the manufacturing method of the first embodiment, the amount of VV defects remaining on the silicon wafer may be further adjusted by adjusting the heat treatment conditions in step S14. By performing step S14 in this way, the amount of VV defects can be adjusted more accurately.

(Second embodiment)
Next, the PN diode 10b of the second embodiment and the manufacturing method thereof will be described. In the description of each part of the PN diode 10b, those having the same configuration as the PN diode 10a of the first embodiment will be described using the same reference numerals.

The PN diode 10b of the second embodiment has substantially the same configuration as the PN diode 10a of the first embodiment. However, the concentration distribution of interstitial silicon in the silicon substrate 12 is different from that of the PN diode 10a. FIG. 5A shows the distribution of the interstitial silicon concentration N3 in the thickness direction in the silicon substrate 12 of the PN diode 10b of the second embodiment. As shown in the drawing, the concentration of interstitial silicon is about 1 × 10 ¹³ atoms / cm ^{3 in} the surface portion on the lower surface 12b side. The interstitial silicon concentration increases from the lower surface 12b toward the upper surface 12a, and the interstitial silicon concentration is about 1 × 10 ¹⁴ atoms / cm ³ at the surface portion on the upper surface 12a side.

FIG. 5B shows a distribution of the concentration N4 of formation defects in the thickness direction in the silicon substrate 12. As shown in the drawing, formation defects exist in the silicon substrate 12 of the PN diode 10b of the second embodiment with the same distribution as the PN diode 10a of the first embodiment. That is, the crystal defect region is formed on the surface portion of the silicon substrate 12 on the upper surface 12a side. More specifically, many crystal defects are formed in the n-type drift layer 16 near the pn junction interface 30. Most of the formation defects formed in the PN diode 10b are VV defects, and there are very few C _i O _i defects.

  As described above, the PN diode 10b of the second embodiment has substantially the same characteristics as the PN diode 10a of the first embodiment. That is, formation defects are formed in a range where the concentration of interstitial silicon is high, and the amount of formation defects is appropriately adjusted. Therefore, the PN diode 10b has an appropriate characteristic at the time of reverse current recovery, and is difficult to avalanche breakdown.

Next, a method for manufacturing the PN diode 10b will be described. Also in the manufacturing method of the second embodiment, the PN diode 10b is manufactured from a silicon wafer made of n-type silicon. As in the first embodiment, this silicon wafer has an n-type diffusion layer 18 formed on the surface portion on the lower surface 12b side, and the upper surface 12a and the lower surface 12b are polished in a mirror shape.
However, unlike the first embodiment, the silicon wafer has a concentration profile that increases as the concentration of interstitial silicon increases from the lower surface 12b toward the upper surface 12a. This silicon wafer is manufactured by growing a silicon ingot while changing the pulling speed and cutting it out from the ingot. That is, when an ingot is grown at a high pulling speed, a silicon crystal with less interstitial silicon grows. When an ingot is grown at a slow pulling speed, a silicon crystal with a lot of interstitial silicon grows. Therefore, when the ingot is grown while changing the pulling speed, an ingot in which the concentration of interstitial silicon varies depending on the position in the pulling direction can be formed. By cutting out a silicon wafer from the ingot, the silicon wafer can be manufactured. The concentration profile of the interstitial silicon in the silicon wafer in the thickness direction is substantially the same as the concentration profile of the silicon substrate 12 shown in FIG.

  The PN diode 10b is manufactured in substantially the same manner as the manufacturing method of the first embodiment shown in FIG. That is, by performing steps S2 and S4, the p-type diffusion layer 14 is formed on the surface portion on the upper surface 12a side of the silicon wafer. Steps S6 and S8 are not performed in the manufacturing process of the PN diode 10b. Therefore, after the p-type diffusion layer 14 is formed, the anode electrode 20 is formed by performing Step S10.

After the anode electrode 20 is formed, helium ions are implanted into the silicon wafer in step S12. That is, helium ions are implanted into the silicon wafer with energy remaining at the surface portion on the upper surface 12a side of the silicon wafer. As a result, formation defects are formed in the silicon wafer with the distribution shown in FIG. As described above, the surface portion of the silicon wafer on the upper surface 12a side has a high concentration of interstitial silicon. Therefore, it is difficult to form C _i O _i defects in the silicon wafer, and most of the formation defects are VV defects. That is, the amount of formation defects formed in the silicon wafer can be accurately controlled.

  After step S12 is performed, unstable formation defects in the silicon wafer are removed by the heat treatment in step S14. Next, the cathode electrode 22 is formed in step S16, and dicing is performed in step S18. Thereby, a plurality of PN diodes 10b are manufactured.

  As described above, this manufacturing method can also accurately control the amount of formation defects formed in the silicon wafer. Therefore, it is possible to reduce variations in characteristics of the manufactured PN diode 10b during reverse current recovery. Further, it is possible to manufacture the PN diode 10b which is difficult to avalanche breakdown at turn-off.

(Third embodiment)
Next, an IGBT 50a having a trench gate electrode according to a third embodiment will be described. FIG. 6 shows a schematic configuration of the IGBT 50a. As shown in the figure, the IGBT 50 a is composed of a silicon substrate 51, an emitter electrode 70, and a collector electrode 72. The collector electrode 72 is formed on the lower surface 51 b of the silicon substrate 51. The emitter electrode 70 is formed on the upper surface 51 a of the silicon substrate 51.
The silicon substrate 51 is mainly made of silicon. A p-type collector layer 52 is formed in a region in contact with the collector electrode 72 of the silicon substrate 51. The p-type collector layer 52 is in ohmic contact with the collector electrode 72. An n-type drift layer 54 is formed on the upper surface side of the p-type collector layer 52. The n-type drift layer 54 is formed by a first drift layer (buffer layer) 54a having a high n-type impurity concentration and a second drift layer 54b having a low n-type impurity concentration. The first drift layer 54a is formed on the upper surface side of the p-type collector layer 52, and the second drift layer 54b is formed on the upper surface side of the first drift layer 54a. A p-type body layer 56 is formed on the upper surface side of the n-type drift layer 54. An n-type emitter region 58 and a p-type body contact region 60 are formed on the upper surface side of the p-type body layer 56. A plurality of trenches are formed in the upper surface 51 a of the silicon substrate 51. Each trench extends from the upper surface 51 a of the silicon substrate 51 to a depth in contact with the upper end of the n-type drift layer 54. An insulating film of SiO ₂ is formed on the wall surface (side surface, bottom surface) of each trench. A gate electrode 74 is formed in each trench. The n-type emitter region 58 is formed in a region in contact with each trench (insulating film of the trench) in the surface portion on the upper surface 51 a side of the silicon substrate 51. N-type emitter region 58 is in ohmic contact with emitter electrode 70. The p-type body contact region 60 is formed in a region where the n-type emitter region 58 is not formed in the surface portion on the upper surface 51 a side of the silicon substrate 51. The p-type body contact region 60 has a higher p-type impurity concentration than the p-type body layer 56. The p-type body contact region 60 is in ohmic contact with the emitter electrode 70.

A high concentration field 66 in which the concentration of interstitial silicon is locally increased is formed in the silicon substrate 51. FIG. 7A shows the distribution of the interstitial silicon concentration N5 in the thickness direction of the silicon substrate 51 (the direction of the arrow V2 in FIG. 6). The horizontal axis of FIG. 7A indicates the position (depth) in the thickness direction of the silicon substrate 51, the origin is the position of the upper surface 51a of the silicon substrate 51, and the right end of the horizontal axis is the lower surface 51b of the silicon substrate 51. Indicates the position. 7A, the position A4 is the position of the interface 53 between the p-type collector layer 52 and the n-type drift layer 54, the position A5 is the position of the interface 55 between the first drift layer 54a and the second drift layer 54b, A position A6 indicates the position of the interface 57 between the n-type drift layer 54 and the p-type body layer 56.
As shown in the figure, the concentration of interstitial silicon in the region between the positions A7 and A8 is about 10 ¹⁴ atoms / cm ³ , and the concentration of interstitial silicon is higher than outside the region. That is, the region between the position A2 and the position A3 is the high concentration field 26. The high concentration field 26 is formed in the n-type drift layer 54 in the vicinity of the interface 53. More specifically, it is formed from the first drift layer 54 a near the interface 55 to the second drift layer 54 b near the interface 55.

  In the silicon substrate 51, there are a number of formation defects formed by implanting helium ions. FIG. 7B shows the distribution of the formation defect concentration N6 in the thickness direction in the silicon substrate 12 (the direction of the arrow V2 in FIG. 6). As shown in the drawing, the formation defect exists in the surface portion of the silicon substrate 51 on the lower surface 51b side. That is, the crystal defect region is formed in the surface portion of the silicon substrate 51 on the lower surface 51b side. Most of the formation defects are formed in the high concentration field 66. Of the crystal defect regions, the region having the highest crystal defect concentration is also formed in the high concentration field 66. Most of the formation defects existing in the silicon substrate 51 are VV defects. The amount of formation defects present in the silicon substrate 51 is adjusted to an appropriate amount.

  In general, the amount of formation defects existing in the silicon substrate 51 affects the characteristics of the IGBT. FIG. 8 shows the characteristics (change of current I1 with respect to time t) at the time of turn-off of two IGBTs having the same structure as the IGBT 50a and different amounts of formation defects. More specifically, a change pattern with respect to time t of the current I1 flowing between the emitter and the collector when a voltage is applied in the forward direction between the emitter and the collector and the gate voltage is switched from ON to OFF at time t1. Show. A graph C4 in FIG. 8 shows the characteristics of an IGBT having a large amount of formed defects, and a graph C5 shows a characteristic of an IGBT having a small amount of formed defects. As described above, the formation defect acts as a carrier recombination center. Therefore, if the amount of formation defects is large, carriers remaining in the silicon substrate 51 at the time of IGBT turn-off are likely to disappear due to recombination. That is, when the amount of formation defects is large, as shown in the graph C4, the IGBT turn-off time (time until the current becomes zero) is shortened. However, when the amount of formation defects is too large, there is a problem that the ON resistance increases and the loss at the time of ON increases. On the other hand, when the amount of formation defects is small, the turn-off time becomes long. Therefore, the amount of formation defects present in the silicon substrate 51 is preferably adjusted to an appropriate amount.

  In the IGBT 50a of the present embodiment, the amount of formation defects formed on the surface portion on the lower surface 51b side is adjusted to an appropriate amount during manufacture. Therefore, the characteristics at turn-off are appropriate characteristics.

Further, as described above, the C _i O _i defect has a property of trapping holes. If C _i O _i defects are formed in the n-type drift layer 54 of the IGBT, the concentration of holes in the n-type drift layer 54 increases. Then, when the IGBT is turned off, spreading of the depletion layer from the interface between the n-type drift layer 54 and the p-type body layer 56 into the n-type drift layer 54 is suppressed by holes in the n-type drift layer 54. Therefore, a high electric field is generated at the interface between the n-type drift layer 54 and the p-type body layer 56, and the avalanche breakdown is likely to occur.
In the IGBT 50a of the present embodiment, most of the formation defects in the high concentration field 66 are VV defects, and there are very few C _i O _i defects. Therefore, the IGBT 50a is unlikely to yield an avalanche.

  FIG. 9 shows a flowchart for manufacturing the IGBT 50a. The IGBT 50a is manufactured from a silicon wafer made of n-type silicon. The upper surface 51 a and the lower surface 51 b of the silicon wafer are polished in a mirror shape so that the thickness of the silicon wafer is substantially the same as that of the silicon substrate 51. Carbon and oxygen are present in the silicon wafer. The concentrations of carbon and oxygen in the silicon wafer vary greatly depending on the silicon wafer.

  In step S22, in order to form each semiconductor region (p-type body layer 56, n-type emitter region 58, p-type body contact region 60) on the upper surface 51a side of the silicon wafer, phosphorous and boron ions are formed from the upper surface 51a of the silicon wafer. Implant dopant impurities. This dopant impurity implantation step is performed by selecting a region to be implanted by forming a resist mask or the like on the silicon wafer. Also, the implantation depth is adjusted, and dopant impurities are implanted to a depth corresponding to each region. Thereby, dopant impurities are implanted into regions corresponding to the p-type body layer 56, the n-type emitter region 58, and the p-type body contact region 60, respectively.

  In step S24, the silicon wafer is heat-treated, and phosphorus and boron implanted in step S22 are diffused and activated. As a result, as shown in FIG. 6, the p-type body layer 56, the n-type emitter region 58, and the p-type body contact region 60 are formed on the silicon wafer.

  In step S26, a trench is formed in the upper surface 51a of the silicon wafer. Then, an insulating film is formed on the wall surface of the trench, and a gate electrode 74 is formed in the trench. The trench, the insulating film, and the gate electrode 74 can be formed using a known technique, but a detailed description thereof is omitted here.

  In step S28, the emitter electrode 70 is formed on the upper surface 51a of the silicon wafer by vapor deposition.

In step S30, phosphorus is implanted by adjusting the implantation depth from the lower surface 51b side of the silicon wafer. As a result, phosphorus is implanted into a region corresponding to the first drift layer 54a.
In step S32, boron is implanted by adjusting the implantation depth from the lower surface 51b side of the silicon wafer. As a result, boron is implanted into a region corresponding to the p-type collector layer 52.

  In step S34, silicon ions are implanted into the silicon wafer from the lower surface 51b side. At this time, silicon ions are implanted with an energy that allows the implanted silicon ions to remain in a range corresponding to the high concentration field 66. As a result, the concentration of silicon in the range increases, and a large number of interstitial silicons are generated in the range.

In step S36, the surface portion on the lower surface 51b side of the silicon wafer is locally heated by the laser annealing apparatus. Thereby, phosphorus and boron implanted in steps S30 and S32 are diffused and activated. That is, as shown in FIG. 6, the p-type collector layer 52 and the first drift layer 54a are formed on the silicon wafer. A region between the first drift layer 54a and the p-type body layer 56 becomes the second drift layer 54b.
In addition, when the heat treatment in step S36 is performed, the interstitial silicon generated in step S34 diffuses, and the interstitial silicon clusters are dispersed and exist. This makes the interstitial silicon more stable. The region in which the interstitial silicon is diffused becomes a high concentration field 66. As shown in FIG. 6, the high concentration field 66 is formed in the n-type drift layer 54 in the vicinity of the interface 55.

In step S38, crystal defects are formed in the silicon wafer by implanting helium ions into the silicon wafer from the lower surface 51b side. At this time, many formation defects are formed in the high concentration field 66 by adjusting the energy for implanting helium ions. As a result, formation defects are formed in the silicon wafer with the distribution shown in FIG. As described above, since the concentration field 66 has a high concentration of interstitial silicon, VV defects can be formed without forming too many C _i O _i defects.

  In step S40, the silicon wafer is heat treated. Specifically, the silicon wafer is held at a temperature of 400 ° C. for about 1 hour. When the silicon wafer is heat-treated under these conditions, the formation defects with unstable energy states existing in the silicon wafer disappear, and VV defects with stable energy states remain in the silicon wafer. That is, most of the formation defects in the silicon wafer are VV defects.

  In step S42, the collector electrode 72 is formed on the lower surface 51b of the silicon wafer by vapor deposition.

  In step S44, the silicon wafer is diced. Thereby, a plurality of IGBTs 50a are manufactured.

As described above, according to the manufacturing method of the third embodiment, VV defects can be formed while suppressing the formation of C _i O _i defects in the silicon crystal. Therefore, the characteristics of the IGBT 50a to be manufactured can be accurately controlled. In addition, the IGBT 50a which is difficult to avalanche yield can be manufactured.

(Fourth embodiment)
Next, the IGBT 50b of the fourth embodiment and the manufacturing method thereof will be described. In the description of each part of the IGBT 50b, those having the same configuration as the IGBT 50a of the third embodiment will be described using the same reference numerals.

The IGBT 50b of the fourth embodiment has substantially the same configuration as the IGBT 50a of the third embodiment. However, the concentration distribution of interstitial silicon in the silicon substrate 51 is different from that of the IGBT 50a. FIG. 10A shows the distribution of the interstitial silicon concentration N7 in the thickness direction in the silicon substrate 51 of the IGBT 50b of the fourth embodiment. As shown in the drawing, the interstitial silicon concentration is about 1 × 10 ¹³ atoms / cm ^{3 in} the surface portion on the upper surface 51a side. The concentration of interstitial silicon increases from the upper surface 51a toward the lower surface 51b, and the concentration of interstitial silicon is about 1 × 10 ¹⁴ atoms / cm ³ at the surface portion on the lower surface 51b side.

FIG. 10B shows the distribution of the formation defect concentration N8 in the thickness direction in the silicon substrate 12. FIG. As shown in the figure, formation defects are present in the silicon substrate 51 of the IGBT 50b of the fourth embodiment with a distribution substantially similar to that of the IGBT 50a of the third embodiment. That is, the crystal defect region is formed in the surface portion of the silicon substrate 51 on the lower surface 51b side. Most of the crystal defects are formed in the n-type drift layer 54 near the interface 53. The region having the highest concentration of crystal defects among the crystal defect regions is formed in the first drift layer 54a. Most of the formation defects formed in the IGBT 50b are VV defects, and there are very few C _i O _i defects. The amount of formation defects present in the silicon substrate 51 is adjusted to an appropriate amount.

  As described above, the IGBT 50b of the fourth embodiment has substantially the same characteristics as the IGBT 50a of the third embodiment. That is, formation defects are formed in a range where the concentration of interstitial silicon is high, and the amount of formation defects is appropriately adjusted. Therefore, the IGBT 50b has an appropriate characteristic at the time of reverse current recovery, and it is difficult for the avalanche to breakdown.

Next, the manufacturing method of IGBT50b is demonstrated. Also in the manufacturing method of the fourth embodiment, the PN diode 10b is manufactured from a silicon wafer made of n-type silicon. As in the third embodiment, the upper surface 51a and the lower surface 51b of this silicon wafer are polished in a mirror shape.
However, unlike the third embodiment, the silicon wafer has a concentration profile that increases as the concentration of interstitial silicon increases from the upper surface 51a toward the lower surface 51b. The concentration profile of the interstitial silicon in the silicon wafer in the thickness direction is substantially the same as the concentration profile of the silicon substrate 51 shown in FIG.

  The IGBT 50b is manufactured in substantially the same manner as the manufacturing method of the third embodiment shown in FIG. That is, the p-type body layer 56, the n-type emitter region 58, and the p-type body contact region 60 are formed by performing steps S22 and S24. Next, a trench, an insulating film, and a gate electrode 74 are formed (step S26), and an emitter electrode 70 is formed (step S28). After the emitter electrode 70 is formed, phosphorus is implanted into a region corresponding to the first drift layer 54a (step S30). When phosphorus is implanted, boron is implanted into a region corresponding to the p-type collector layer 52 (step S32). In the manufacturing method of the fourth embodiment, step 34 is not performed. Therefore, next, step S36 is implemented. In step S36, the surface portion on the lower surface 51b side of the silicon wafer is heat-treated, so that phosphorus and boron implanted in steps S30 and S32 are diffused and activated. As a result, the p-type collector layer 52, the first drift layer 54a, and the second drift layer 54b are formed.

In step S38, helium ions are implanted into the silicon wafer. That is, helium ions are implanted into the silicon wafer from the lower surface 51b side of the silicon wafer with energy remaining at the surface portion. Thereby, formation defects are formed in the silicon wafer with the distribution shown in FIG. As described above, the surface portion of the silicon wafer on the lower surface 51b side has a high concentration of interstitial silicon. Therefore, VV defects can be formed without forming too many C _i O _i defects. The amount of formation defects formed in the silicon wafer is adjusted to an appropriate amount. After step S38 is performed, unstable formation defects in the silicon wafer are removed by the heat treatment in step S40. Next, the collector electrode 72 is formed in step S42, and dicing is performed in step S44. Thereby, a plurality of PN diodes 10b are manufactured.

As described above, the VV defect can be formed while suppressing the formation of C _i O _i defects in the silicon crystal also by the manufacturing method of the fourth embodiment. Accordingly, the characteristics of the manufactured IGBT 50b can be accurately controlled. In addition, an IGBT 50b that does not easily yield an avalanche can be manufactured.

  In the first to fourth embodiments, the manufacturing method of the PN diode and the IGBT has been described. However, other semiconductor devices can be manufactured by the manufacturing method of the present invention. For example, various kinds of semiconductor devices such as NPN type or PNP type bipolar transistors and thyristors can be manufactured.

  In the manufacturing methods of the first to fourth embodiments described above, the formation defect is formed by implanting helium ions. However, the formation defect may be formed by implanting other charged particles. For example, formation defects can also be formed by implanting various charged particles such as electrons and protons.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

The figure which shows schematic structure of the PN diode 10a. The figure which shows the density distribution of the interstitial silicon in the silicon substrate 12 of the PN diode 10a, and the density distribution of the formation defect. The figure which shows the turn-off characteristic of a PN diode. The flowchart which shows the manufacturing method of PN diode 10a. The figure which shows the density distribution of the interstitial silicon in the silicon substrate 12 of the PN diode 10b, and the density distribution of the formation defect. The figure which shows schematic structure of IGBT50a. The figure which shows the density distribution of the interstitial silicon in the silicon substrate 51 of IGBT50a, and the density distribution of a formation defect. The figure which shows the turn-off characteristic of IGBT. The flowchart which shows the manufacturing method of IGBT50a. The figure which shows the density distribution of the interstitial silicon in the silicon substrate 12 of IGBT50b, and the density distribution of a formation defect.

Explanation of symbols

10a: PN diode 10b: PN diode 12: silicon substrate 12a: upper surface 12b: lower surface 14: p-type diffusion layer 16: n-type drift layer 18: n-type diffusion layer 20: anode electrode 22: cathode electrode 26: high concentration field 30: pn junction interface 50a: IGBT
50b: IGBT
51: silicon substrate 51a: upper surface 51b: lower surface 52: p-type collector layer 54: n-type drift layer 54a: first drift layer 54b: second drift layer 56: p-type body layer 58: n-type emitter region 60: p-type Body contact region 66: High concentration field 70: Emitter electrode 72: Collector electrode 74: Gate electrode

Claims (6)

A method of manufacturing a semiconductor device having a crystal defect region in which crystal defects are formed in a predetermined range,
An interstitial silicon generation step of generating interstitial silicon in the predetermined range by implanting silicon ions with energy to be injected into the predetermined range from the surface of the silicon substrate;
A method of manufacturing a semiconductor device, comprising: a crystal defect forming step of forming a crystal defect in the predetermined range by implanting charged particles with energy that is injected into the predetermined range from a surface of a silicon substrate. Form crystal defects by using a silicon substrate with a concentration profile that increases as the concentration of interstitial silicon increases from one surface to the other by growing the crystal while changing the pulling speed during ingot production A method of manufacturing a semiconductor device having a crystal defect region,
A method of manufacturing a semiconductor device comprising a crystal defect forming step of forming a crystal defect in a surface portion by implanting charged particles with energy remaining in the surface portion from a surface having a higher interstitial silicon concentration of the silicon substrate . A method of manufacturing a PN diode having a crystal defect region in which crystal defects are formed in a predetermined range,
A pn junction forming step of introducing a dopant impurity into the silicon substrate to form a pn junction within the predetermined range;
An interstitial silicon generation step of generating interstitial silicon in the predetermined range by implanting silicon ions with energy to be injected into the predetermined range from the surface of the silicon substrate;
A method of manufacturing a PN diode, comprising: a crystal defect forming step of forming a crystal defect in the predetermined range by implanting charged particles with energy that is implanted into the predetermined range from the surface of the silicon substrate on which the interstitial silicon generation step has been performed. Form crystal defects by using a silicon substrate with a concentration profile that increases as the concentration of interstitial silicon increases from one surface to the other by growing the crystal while changing the pulling speed during ingot production A method of manufacturing a PN diode having a crystal defect region, comprising:
A pn junction introducing step of introducing a dopant impurity into the silicon substrate to form a pn junction in the surface portion of the silicon substrate having a higher interstitial silicon concentration;
A method of manufacturing a PN diode comprising a crystal defect forming step of forming a crystal defect in a surface portion by implanting charged particles with energy remaining in the surface portion from a surface having a higher interstitial silicon concentration of the silicon substrate . A method of manufacturing an IGBT having a crystal defect region in which crystal defects are formed in a predetermined range,
An upper surface side introducing step of introducing a dopant impurity from the upper surface side of the silicon substrate to form a body region and an emitter region;
A lower surface side introducing step of forming an interface between the collector region and the drift region in the surface portion on the lower surface side by introducing a dopant impurity from the lower surface side of the silicon substrate to form a collector region;
An interstitial silicon generation step of generating interstitial silicon in the predetermined range by implanting silicon ions with energy to be injected into the predetermined range from the surface of the silicon substrate;
A method of manufacturing an IGBT, comprising: a crystal defect forming step of forming a crystal defect in the predetermined range by implanting charged particles with energy that is implanted into the predetermined range from a surface of a silicon substrate on which an interstitial silicon generation step is performed. A crystal defect region in which a crystal defect is formed by using a silicon substrate on which a concentration profile in which the concentration of interstitial silicon increases from the upper surface to the lower surface is formed by crystal growth while changing the pulling speed during ingot production. A method of manufacturing an IGBT comprising:
An upper surface side introducing step of introducing a dopant impurity from the upper surface side of the silicon substrate to form a body region and an emitter region;
A lower surface side introducing step of forming an interface between the collector region and the drift region in the surface portion on the lower surface side by introducing a dopant impurity from the lower surface side of the silicon substrate to form a collector region;
An IGBT manufacturing method comprising a crystal defect forming step of forming a crystal defect in a surface portion by implanting charged particles with energy remaining on the surface portion from a lower surface side of the silicon substrate.

Images