CN116779442A - Method for forming semiconductor structure - Google Patents
Method for forming semiconductor structure Download PDFInfo
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- CN116779442A CN116779442A CN202210243381.0A CN202210243381A CN116779442A CN 116779442 A CN116779442 A CN 116779442A CN 202210243381 A CN202210243381 A CN 202210243381A CN 116779442 A CN116779442 A CN 116779442A
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- 238000000034 method Methods 0.000 title claims abstract description 113
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000005530 etching Methods 0.000 claims abstract description 96
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 238000000059 patterning Methods 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims description 123
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 8
- 229910052799 carbon Inorganic materials 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 230000004048 modification Effects 0.000 description 15
- 238000012986 modification Methods 0.000 description 15
- 238000000206 photolithography Methods 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 230000007547 defect Effects 0.000 description 5
- 230000005669 field effect Effects 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 230000003746 surface roughness Effects 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000005416 organic matter Substances 0.000 description 2
- 238000012876 topography Methods 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a first region and a second region, and the surface of the substrate is provided with a first mask layer; modifying the first mask layer to form a plurality of modified regions in the first mask layer on the first region; forming a plurality of first mask structures on the first mask layer on the second region; etching the first mask layer by taking the plurality of first mask structures and the modified region as masks to form a plurality of second mask structures and a plurality of third mask structures; and patterning the second region by using the second mask structure, patterning the first region by using the third mask structure, forming a plurality of first fins in the first region, and forming a plurality of second fins in the second region. The method improves the performance and reliability of the formed semiconductor structure.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a method for forming a semiconductor structure.
Background
In the existing semiconductor field, the control capability of a conventional planar metal-oxide semiconductor field effect transistor (MOSFET) on channel current is weakened, resulting in serious leakage current.
Fin field effect transistors (Fin FETs) are an emerging type of multi-gate device that generally include a Fin protruding from a semiconductor substrate surface, a gate structure covering a portion of the top surface and sidewalls of the Fin, and source-drain doped regions in the Fin on either side of the gate structure. Fin field effect transistors (MOSFETs) have a stronger short channel rejection capability and a stronger operating current than planar metal-oxide semiconductor field effect transistors (MOSFETs), and are now widely used in a variety of semiconductor devices.
However, the performance and reliability of existing semiconductor structures still remain to be improved.
Disclosure of Invention
The invention solves the technical problem of providing a method for forming a semiconductor structure to improve the performance and reliability of the semiconductor structure.
In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first region and a second region, and the surface of the substrate is provided with a first mask layer; modifying the first mask layer to form a plurality of mutually independent modified regions in the first mask layer on the first region; forming a plurality of first mask structures which are mutually separated on the first mask layer on the second region, wherein the width of the first mask structures is smaller than that of the modified region; etching the first mask layer by taking the first mask structures and the modified region as masks, forming a plurality of second mask structures which are separated from each other on the second region, and forming a plurality of third mask structures which are separated from each other on the first region; and patterning the second region by using the second mask structure, patterning the first region by using the third mask structure, forming a plurality of mutually separated first fins in the first region, and forming a plurality of mutually separated second fins in the second region.
Optionally, modified ions are doped in the modified region.
Optionally, the method for modifying the first mask layer includes: forming a photoetching pattern layer on the surface of the first mask layer, wherein a plurality of openings are formed in the photoetching pattern layer, and the bottoms of the openings expose the surface of the first mask layer on the first area; and performing ion implantation on the first mask layer by taking the first photoetching pattern layer as a mask.
Optionally, in the ion implantation process, the modified ions include at least one of boron, phosphorus, arsenic and carbon.
Optionally, the material of the first mask layer includes: amorphous silicon.
Optionally, the process of etching the first mask layer by using the plurality of first mask structures as masks includes an atomic layer etching process.
Optionally, the technological parameters of the atomic layer etching process include: the gases used include: o (O) 2 、CF 4 Ar and Cl 2 The method comprises the steps of carrying out a first treatment on the surface of the The pressure ranges from 5 millitorr to 30 millitorr.
Optionally, in the process of etching the first mask layer, an etching selection ratio of a material of the first mask layer to a material of the modified region is above 50.
Optionally, the base includes an initial substrate, and a second mask layer located on a surface of the initial substrate.
Optionally, the method for patterning the second region with the second mask structure and the first region with the third mask structure includes: etching the second mask layer by taking the second mask structures and the third mask structures as masks, forming a plurality of first intermediate mask structures which are separated from each other on the initial substrate of the first area, and forming a plurality of second intermediate mask structures which are separated from each other on the initial substrate of the second area; and etching the initial substrate by taking the first intermediate mask structures and the second intermediate mask structures as masks until a substrate and the first fins and the second fins on the substrate are formed.
Optionally, the second mask layer includes: the mask comprises a lower second mask layer and an upper second mask layer positioned on the surface of the lower second mask layer, wherein the material of the upper second mask layer is different from that of the first mask layer, and the material of the upper second mask layer is different from that of the lower second mask layer.
Optionally, the forming method of the plurality of first intermediate mask structures and the plurality of second intermediate mask structures includes: performing first etching treatment by taking the second mask structures and the third mask structures as masks, and etching the upper second mask layer and the lower second mask layer until the initial substrate surface of the first region is exposed; after the first etching treatment, carrying out second etching treatment on the lower second mask layer until the initial substrate surface of the second region is exposed; the etching rate of the material of the upper second mask layer in the first etching treatment process is larger than that of the material of the upper second mask layer in the second etching treatment process, and the etching selection ratio of the material of the lower second mask layer to the material of the initial substrate in the second etching treatment process is 5.
Optionally, the forming method of the plurality of first intermediate mask structures and the plurality of second intermediate mask structures further includes: and removing the second mask structure and the third mask structure after the first etching treatment and before the second etching treatment.
Optionally, the material of the upper second mask layer includes silicon nitride, and the material of the lower second mask layer includes silicon oxide.
Optionally, in the process of etching the first mask layer, an etching rate of a material of the first mask layer is greater than an etching rate of a material of the modified region.
Optionally, the first mask structure is formed using a self-aligned double patterning process or a self-aligned multiple patterning process.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, a substrate is provided, wherein the substrate comprises a first region and a second region, and the surface of the substrate is provided with a first mask layer; modifying the first mask layer to form a plurality of mutually independent modified regions in the first mask layer on the first region; forming a plurality of first mask structures which are mutually separated on the first mask layer on the second region, wherein the width of the first mask structures is smaller than that of the modified region; and etching the first mask layer by taking the plurality of first mask structures and the modified region as masks, forming a plurality of second mask structures which are mutually separated on the first region, and forming a plurality of third mask structures which are mutually separated on the second region. Therefore, the second region is patterned by the second mask structure, the first region is patterned by the third mask structure, a plurality of first fins which are separated from each other are formed in the first region, and when a plurality of second fins which are separated from each other are formed in the second region, not only the plurality of first fins and the plurality of second fins which have small side wall roughness, good appearance, accurate size, good dimensional stability and small height deviation from each other can be formed, but also the plurality of first fins and the plurality of second fins are less polluted by residues, so that the performance and the reliability of the semiconductor structure are improved.
Drawings
FIGS. 1 to 3 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure;
fig. 4 to 12 are schematic cross-sectional views illustrating steps of forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance and reliability of existing semiconductor structures remains to be improved, and the description will now be made in connection with specific embodiments.
Fig. 1 to 3 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, and the substrate 100 includes a first region I and a second region II.
With continued reference to fig. 1, a plurality of spacers 110 are formed on the surface of the first region I by using a self-aligned double patterning process (SADP) or a self-aligned multiple patterning process (SADP).
The material of the sidewall 110 is a hard mask (hard mask) material, such as silicon nitride.
With continued reference to fig. 1, after forming a plurality of side walls 110, a mask material layer 120 is formed on the surfaces of the first region I, the second region II and the side walls 110; a photoresist pattern layer 130 is formed on the surface of the mask material layer 120 on the second region II.
In order to form and initially transfer the pattern (pattern) of the photoresist pattern layer 130, a carbon-containing organic (SOC) of a soft mask (soft mask) material is generally used as the material of the mask material layer 120.
Referring to fig. 2, the mask material layer 120 is etched using the photoresist pattern layer 130 as a mask until the surfaces of the sidewalls 110 and the substrate 100 are exposed, and a plurality of fin mask structures 121 are formed on the second region II.
Referring to fig. 3, the substrate 100 is etched by using the sidewalls 110 and the fin mask structures 121 as masks, a plurality of first fins 101 are formed in a first region I, a plurality of second fins 102 are formed in a second region II, the first fins 101 are used to form Short channel (Short channel) devices, and the second fins 102 are used to form Long channel (Long channel) devices.
However, since the side wall 110 is made of a hard mask material and the fin mask structure 121 is made of a soft mask material, when the substrate 100 is etched by taking the side wall 110 and the fin mask structure 121 as masks, the soft mask material is easily etched and worn compared with the hard mask material, so that not only is an etching load (loading) defect easily generated, the height deviation between the first fins 101 and the second fins 102 is large, but also the pattern sizes of the plurality of second fins 102 are unstable, that is, the deviation between the sizes of the second fins 102 is large, and the size of the second fins 102 is inaccurate.
Furthermore, since the mask material layer 120 is made of an organic material, the surface roughness and the topography of the fin mask structure 121 formed after etching the mask material layer 120 are large, which results in the sidewall surface roughness and the topography of the second fin 102 formed after pattern transfer, and when the source-drain structure material is formed by an epitaxial growth process, the source-drain structure material is easy to grow on the sidewall surface of the second fin 102.
In addition, because the space between the adjacent side walls 110 is narrow, and a large amount of etching byproducts are generated when etching the carbon-containing organic matter, the mask material layer 120 filled between the adjacent side walls 110 is not easy to remove, residues are easy to generate, and pollution is caused to the plurality of first fins 101 and the plurality of second fins 202.
Thus, the performance and reliability of the semiconductor structure are poor.
In order to solve the technical problem, the technical scheme of the invention provides a method for forming a semiconductor structure, which comprises the steps of providing a substrate, wherein the substrate comprises a first region and a second region, and the surface of the substrate is provided with a first mask layer; modifying the first mask layer to form a plurality of mutually independent modified regions in the first mask layer on the first region; forming a plurality of first mask structures which are mutually separated on the first mask layer on the second region, wherein the width of the first mask structures is smaller than that of the modified region; etching the first mask layer by taking the first mask structures and the modified region as masks, forming a plurality of second mask structures which are separated from each other on the second region, and forming a plurality of third mask structures which are separated from each other on the first region; and patterning the second region by using the second mask structure, patterning the first region by using the third mask structure, forming a plurality of mutually separated first fins in the first region, and forming a plurality of mutually separated second fins in the second region. Therefore, the performance and reliability of the formed semiconductor structure can be improved.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Note that "surface" in this specification is used to describe a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
Fig. 4 to 12 are schematic cross-sectional views illustrating steps of forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4, a substrate 200 is provided, the substrate 200 includes a first region a and a second region B, and a surface of the substrate 200 has a first mask layer 300.
In this embodiment, the substrate 200 includes: an initial substrate 210, and a second mask layer 220 on a surface of the initial substrate 210.
In this embodiment, the initial substrate 210 provides material for a subsequently formed substrate, a number of first fins in the first region a, and a number of second fins in the second region B. Wherein the first fin is used to form a long channel device and the second fin is used to form a short channel device.
In this embodiment, the material of the initial substrate 210 includes a semiconductor material.
Specifically, the material of the initial substrate 210 includes silicon.
In other embodiments, the material of the initial substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. Among them, the iii-v group element-made multi-element semiconductor material includes InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP and the like.
In this embodiment, the second mask layer 220 provides materials for forming a plurality of first intermediate mask structures and a plurality of second intermediate mask structures later.
The second mask layer 220 includes a hard mask (hard mask) material.
In this embodiment, the second mask layer 220 is a composite layer structure. Specifically, the second mask layer 220 includes: a lower second mask layer 221, and an upper second mask layer 222 on the surface of the lower second mask layer 221.
Wherein, the material of the upper second mask layer 222 is different from that of the first mask layer 300, and the material of the upper second mask layer 222 is different from that of the lower second mask layer 221.
In this embodiment, the material of the upper second mask layer 222 includes silicon nitride, and the material of the lower second mask layer 221 includes silicon oxide. Wherein the silicon nitride is a hard mask material.
In this embodiment, the first mask layer 300 is a hard mask material. Specifically, the materials of the first mask layer 300 include: amorphous silicon.
Then, the first mask layer 300 is modified, and a plurality of independent modified regions are formed in the first mask layer 300 on the first region a.
In this embodiment, the modified region is doped with modified ions.
The detailed steps for forming the modified regions are shown in FIGS. 5 and 6.
Referring to fig. 5, a photolithography pattern layer 310 is formed on the surface of the first mask layer 300, the photolithography pattern layer 310 has a plurality of openings 311 therein, and the bottoms of the openings 311 expose the surface of the first mask layer 300 on the first area a.
The pattern of the photolithographic patterning layer 310 is used to define the shape of a number of the first fins. Specifically, the shape of the number of openings 311 is used to define the shape of the number of the first fins.
In this embodiment, the material of the photoresist pattern layer 310 includes photoresist.
Referring to fig. 6, the first mask layer 300 is subjected to ion implantation by using the photolithography pattern layer 310 as a mask, and a plurality of independent modified regions 301 are formed in the first mask layer 300 on the first region a. The modified regions 301 provide material for subsequent formation of third mask structures over the first regions a.
In this embodiment, the modified region 301 penetrates the first mask layer 300 along the normal direction of the surface of the substrate 200, so as to better transfer the pattern of the photolithographic pattern layer 310.
Specifically, the modified region 301 is doped with modified ions.
In this embodiment, the modifying ions include: at least one of boron, phosphorus, arsenic and carbon.
Accordingly, in the process of performing ion implantation on the first mask layer 300, the implanted ions include at least one of boron, phosphorus, arsenic and carbon.
In this embodiment, after forming the plurality of modified regions 301, the photolithographic patterned layer 310 is removed.
In this embodiment, the process of removing the photolithography pattern layer 310 includes an ashing process and the like.
Next, a plurality of first mask structures are formed on the first mask layer 300 on the second region B, wherein the widths of the first mask structures are smaller than the widths of the modified regions 301.
In this embodiment, a self-aligned double patterning process (SADP) is used to form a plurality of first mask structures. In other embodiments, the first mask structure may also be formed using a self-aligned multiple patterning process (SAQP).
In this embodiment, please refer to fig. 7 to 9 for a detailed step of forming a plurality of first mask structures.
Referring to fig. 7, after removing the photolithography pattern layer 310, a third mask material layer 410 is formed on the surface of the first mask layer 300; a photolithography pattern layer 420 is formed on the surface of the third mask material layer 410.
The pattern of the photolithographic patterning layer 420 is used to define the shape of subsequently formed core structures.
The material of the photoresist pattern layer 420 includes photoresist.
In this embodiment, the third mask material layer 410 is used to form and initially transfer the pattern of the photolithography pattern layer 420. The material of the third mask material layer 410 is a soft mask (soft mask) material, and specifically, the material of the third mask material layer 410 is a carbon-containing organic Substance (SOC).
In this embodiment, before the third mask material layer 410 is formed, a fourth mask material layer 400 is formed on the surface of the first mask layer 300.
In this embodiment, the fourth mask material layer 400 provides material for forming several core structures later.
In this embodiment, the material of the fourth mask material layer 400 is different from the material of the first mask layer 300.
In this embodiment, the material of the fourth mask material layer 400 is a hard mask material. Specifically, the material of the fourth mask material layer 400 includes oxide or silicon nitride.
Because the fourth mask material layer 400 is formed between the third mask material layer 410 and the first mask material layer 300, and the material of the fourth mask material layer 400 is a hard mask material, the stability of pattern transfer of the lithography pattern layer 420 can be better improved, and thus, several core structures with better morphology and more accurate size can be formed.
In other embodiments, the fourth masking material layer is not formed. And providing materials for forming a plurality of core structures by using the third mask material layer.
In this embodiment, an anti-reflective coating (ARC) is formed on the surface of the third mask material layer 410 before the photolithography pattern layer 420 is formed.
In other embodiments, no anti-reflective film is formed.
Referring to fig. 8, the third mask material layer 410 is etched by using the photolithography pattern layer 420 as a mask until the surface of the fourth mask material layer 400 is exposed, and a plurality of mask structures 411 separated from each other are formed on the second region B; the fourth mask material layer 400 is etched with the plurality of mutually separated mask structures 411 as a mask until the surface of the first mask layer 300 is exposed, and a plurality of mutually separated core structures 401 are formed on the second region B.
In this embodiment, the second lithographically patterned layer 420 is removed after the mask structure 411 is formed and before the fourth mask material layer 400 is etched.
In this embodiment, the process of removing the second lithographically patterned layer 420 includes an ashing process, etc.
In this embodiment, after forming the plurality of core structures 401, the plurality of mask structures 411 are removed.
Referring to fig. 9, after removing the mask structures 411, first mask structures 430 are formed on the sidewall surfaces of the core structures 401.
The first plurality of mask structures 430 is used to define the shape of the second plurality of fins.
The width of the first mask structures 430 is smaller than the width of the modified regions 301, and the spacing between adjacent first mask structures 430 is smaller than the spacing between adjacent modified regions 301. In this way, subsequently, a number of first fins can be formed in the first region a that are wider and have a larger spacing between adjacent ones for constituting long channel devices in the semiconductor structure, while a number of second fins are formed in the second region B that are narrower and have a smaller spacing between adjacent ones for constituting segment channel devices in the semiconductor structure.
In this embodiment, the method for forming the first mask structures 430 on the sidewall surfaces of the core structures 401 includes: forming a first mask material film (not shown) on the surface of the first mask layer 300 and the surfaces of the plurality of core structures 401; and etching the first mask material film by adopting an anisotropic etching process until the surfaces of the first mask layer 300 and the top surfaces of the plurality of core structures 401 are exposed, and forming side walls on the side wall surfaces of the core structures 401, wherein the side walls are the first mask structures 430.
In this embodiment, the anisotropic etching process includes a plasma etching process.
In this embodiment, the process of forming the first mask material film includes a chemical vapor deposition process, an atomic layer deposition process, or the like.
In this embodiment, after forming the first mask structures 430, the core structures 411 are removed.
Referring to fig. 10, after removing the core structures 411, the first mask layer 300 is etched by using the first mask structures 430 and the modified regions 301 as masks, a plurality of second mask structures 302 are formed on the second region B separately from each other, and a plurality of third mask structures 303 are formed on the first region a separately from each other.
In this embodiment, a number of second mask structures 302 are used to form a number of the second fins, and a number of third mask structures are used to form a number of the first fins. Since the second fin is used to form a short channel device in a semiconductor structure and the first fin is used to form a long channel device in a semiconductor structure, accordingly, the width of the second mask structure 302 is smaller than the width of the third mask structure 303, and the pitch between adjacent second mask structures 302 is smaller than the pitch between adjacent third mask structures 303.
Since the substrate 200 is provided, the substrate 200 includes a first region a and a second region B, the surface of the first region B has a first mask layer 300, the first mask layer 300 is modified, a plurality of modification regions 301 independent of each other are formed in the first mask layer 300 on the first region a, a plurality of first mask structures 430 independent of each other are formed on the first mask layer 300 on the second region B, the width of the first mask structures 430 is smaller than the width of the modification regions 301, the first mask layer 300 is etched by using the plurality of first mask structures 430 and the plurality of modification regions 301 as masks, a plurality of second mask structures 302 independent of each other are formed on the second region B, and a plurality of third mask structures 303 independent of each other are formed on the first region a. Therefore, when the substrate 200 of the first region a and the second region B is patterned by the second mask structure 302 and the third mask structure 303, not only the first fins and the second fins with small sidewall roughness, good morphology, good dimensional stability, accurate dimension and small height deviation from each other can be formed, but also the first fins and the second fins are less contaminated by residues, thereby improving the performance and reliability of the semiconductor structure.
Specifically, by performing the modification treatment on the first mask layer 300, a plurality of modification regions 301 that are independent of each other are formed in the first mask layer 300 on the first region a, so that the material characteristics of the modification regions 301 are different from those of the first mask layer 300, and therefore, when etching the first mask layer 300 by using the plurality of first mask structures 430 and the plurality of modification regions 301 as masks, it is possible to implement that in the process of etching the first mask layer 300, the etching rate of the material of the first mask layer 300 is greater than the etching rate of the material of the modification regions 301. Thus, the third mask structures 303 may be formed based on the modified regions 301 while transferring a pattern based on the first mask structures 430 to form the second mask structures 302. Thus, when the material of the first mask layer 300 is a hard mask material, a plurality of second mask structures 302, which are made of a hard mask material, and a plurality of third mask structures 303, which are made of a hard mask material, can be formed.
Hard mask materials are harder and more wear resistant than soft mask materials. Because the plurality of second mask structures 302 and the plurality of third mask structures 303 of the hard mask material can be formed, the second mask structures 302 and the third mask structures 303 have small surface roughness, good morphology, difficult deformation (few bending defects), and good pattern stability, and when the plurality of second mask structures 302 and the plurality of third mask structures 303 are used as masks for patterning the substrate 200 of the first area a and the second area B, the etching load defect in the etching process can be reduced, so that the plurality of first fins and the plurality of second fins with small sidewall roughness, good morphology, accurate dimension, small height deviation between the first fins can be formed, the pattern dimension deviation between the first fins is small, the dimension stability is good, and the pattern dimension deviation between the second fins is small, and the dimension stability is good.
In addition, since the carbon-containing organic matter does not need to be filled between the adjacent second mask structures 302 with a small pitch, residues between the adjacent second mask structures 302 can be reduced, so that when the substrate 200 of the first region a and the second region B is subsequently patterned with the second mask structures 302 and the third mask structures 303, the number of first fins and the number of second fins are less contaminated by the residues.
Thus, performance and reliability of the semiconductor structure are improved.
Furthermore, in this embodiment, since the modification treatment is performed on the first mask layer 300 before the formation of the plurality of first mask structures 430, the plurality of modification regions 301 that are independent of each other are formed in the first mask layer 300 on the first region a, and thus, the process of forming the modification regions 301 is less affected by the process of forming the plurality of first mask structures 430, and thus, the difficulty and complexity of the process of forming the modification regions 301 are reduced.
In this embodiment, in the process of etching the first mask layer 300, the etching rate of the material of the first mask layer 300 is greater than the etching rate of the material of the modified region 301.
Preferably, in the process of etching the first mask layer 300, the etching selection ratio of the material of the first mask layer 300 to the material of the modified region 301 is more than 50, so as to further reduce the loss of the etching process to the modified region 301, and form the third mask structure 303 with a more accurate size.
In this embodiment, the process of etching the first mask layer 300 with the plurality of first mask structures 430 as masks includes: atomic Layer Etching (ALE).
By adopting the atomic layer etching process with higher control precision, the etching selection ratio of the material of the first mask layer 300 to the material of the modification region 301 in the process of etching the first mask layer 300 is further improved, and the etching selection ratio of the material of the first mask layer 300 to the material of the modification region 301 is more than 50.
In this embodiment, the process parameters of the atomic layer etching process include: the gases used include: o (O) 2 、CF 4 Ar and Cl 2 The method comprises the steps of carrying out a first treatment on the surface of the The pressure ranges from 5 millitorr to 30 millitorr.
In some practical applications, the atomic layer etching process may be performed in an ICP machine.
Next, the substrate 200 of the second region B is patterned with the second mask structure 302, and the substrate 200 of the first region a is patterned with the third mask structure 303, wherein a plurality of first fins are formed separately in the first region a, and a plurality of second fins are formed separately in the second region B. The substrate 200 is specifically patterned, and the detailed steps of forming the first fins and the second fins are shown in fig. 11 and 12.
Referring to fig. 11, the second mask layer 220 is etched by using the second mask structures 302 and the third mask structures 303 as masks, a plurality of first intermediate mask structures 223 are formed on the initial substrate 210 of the first region a, and a plurality of second intermediate mask structures 224 are formed on the initial substrate 210 of the second region B.
Since the second mask layer 220 is formed between the first mask layer 300 and the initial substrate 210, and before the initial substrate is etched to form the first fins and the second fins, the second mask layer 220 is etched with the second mask structures 302 and the third mask structures 303 as masks, the first intermediate mask structures 223 and the second intermediate mask structures 224 are formed, and the initial substrate 210 is etched with the first intermediate mask structures 223 and the second intermediate mask structures 224 as masks, stability of pattern transfer is further improved, and performance and reliability of the semiconductor structure are improved.
In this embodiment, the forming method of the plurality of first intermediate mask structures 223 and the plurality of second intermediate mask structures 224 includes: performing a first etching process by using the second mask structures 302 and the third mask structures 303 as masks, and etching the upper second mask layer 222 and the lower second mask layer 221 until the initial substrate 210 surface of the first region a is exposed; after the first etching process, a second etching process is performed on the lower second mask layer 221 until the surface of the initial substrate 210 of the second region B is exposed.
The etching rate of the material of the upper second mask layer 222 in the first etching process is greater than the etching rate of the material of the upper second mask layer 222 in the second etching process.
Since the second mask layer 220 includes the upper second mask layer 222 and the lower mask layer 221 with different materials, and the second mask layer 220 is etched by the first etching process and the second etching process to form a plurality of first intermediate mask structures 223 and a plurality of second intermediate mask structures 224, etching load defects between the plurality of first intermediate mask structures 223 and the plurality of second intermediate mask structures 224 can be further reduced, and the first intermediate mask structures 223 and the second intermediate mask structures 224 with more accurate dimensions and smaller height deviation from each other can be formed.
Specifically, by reducing the etching rate of the material of the upper second mask layer 222 in the process of the second etching process after the first etching process, the upper second mask layer 222 to which the pattern has been transferred can be reduced or not damaged while etching the remaining lower second mask layer 221, so as to further reduce the etching load defect between the plurality of first intermediate mask structures 223 and the plurality of second intermediate mask structures 224.
In addition, in the second etching process, the etching selectivity of the material of the underlying second mask layer 221 to the material of the initial substrate 210 is greater than or equal to 5. To better reduce the damage to the surface of the initial substrate 210 caused by the etching process for forming the first and second intermediate mask structures 223 and 224, and further improve the performance and reliability of the semiconductor structure.
In this embodiment, the process of the first etching treatment includes at least one of a dry etching process and a wet etching process, and the process of the second etching treatment includes at least one of a dry etching process and a wet etching process.
In this embodiment, the forming method of the plurality of first intermediate mask structures 223 and the plurality of second intermediate mask structures 224 further includes: after the first etching process, the second mask structure 302 and the third mask structure 303 are removed before the second etching process. Thus, the aspect ratio between the adjacent first intermediate mask structures 223 and the adjacent second intermediate mask structures 224 is reduced, and the process difficulty of the second etching treatment is further reduced.
Referring to fig. 12, the initial substrate 210 is etched using the first intermediate mask structures 223 and the second intermediate mask structures 224 as masks until the substrate 210a and the first fins 211 and the second fins 212 on the substrate 210a are formed, so as to form first fins 211 in the first region a and second fins 212 in the second region B.
In this embodiment, the first fin 211 is used to form a long channel device in a semiconductor structure, and the second fin 212 is used to form a short channel device in a semiconductor structure.
In this embodiment, the width of the first fins 211 is greater than the width of the second fins 212, and the spacing between adjacent first fins 211 is smaller than the spacing between adjacent second fins 212.
In this embodiment, the process of etching the initial substrate 210 includes at least one of a dry etching process and a wet etching process using the plurality of first intermediate mask structures 223 and the plurality of second intermediate mask structures 224 as masks.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (16)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first region and a second region, and the surface of the substrate is provided with a first mask layer;
modifying the first mask layer to form a plurality of mutually independent modified regions in the first mask layer on the first region;
forming a plurality of first mask structures which are mutually separated on the first mask layer on the second region, wherein the width of the first mask structures is smaller than that of the modified region;
etching the first mask layer by taking the first mask structures and the modified region as masks, forming a plurality of second mask structures which are separated from each other on the second region, and forming a plurality of third mask structures which are separated from each other on the first region;
and patterning the second region by using the second mask structure, patterning the first region by using the third mask structure, forming a plurality of mutually separated first fins in the first region, and forming a plurality of mutually separated second fins in the second region.
2. The method of forming a semiconductor structure of claim 1, wherein the modified region is doped with modifying ions.
3. The method for forming a semiconductor structure according to claim 2, wherein the method for modifying the first mask layer comprises: forming a photoetching pattern layer on the surface of the first mask layer, wherein a plurality of openings are formed in the photoetching pattern layer, and the bottoms of the openings expose the surface of the first mask layer on the first area; and performing ion implantation on the first mask layer by taking the first photoetching pattern layer as a mask.
4. The method of forming a semiconductor structure of claim 3, wherein the modifying ions comprise at least one of boron, phosphorus, arsenic, and carbon.
5. The method of forming a semiconductor structure of claim 1, wherein the material of the first mask layer comprises: amorphous silicon.
6. The method of claim 1, wherein etching the first mask layer using the plurality of first mask structures as a mask comprises an atomic layer etching process.
7. The method of forming a semiconductor structure of claim 6, wherein the process parameters of the atomic layer etching process comprise: the gases used include: o (O) 2 、CF 4 Ar and Cl 2 The method comprises the steps of carrying out a first treatment on the surface of the The pressure ranges from 5 millitorr to 30 millitorr.
8. The method of claim 1, wherein an etch selectivity ratio of a material of the first mask layer to a material of the modified region is greater than 50 in the process of etching the first mask layer.
9. The method of forming a semiconductor structure of claim 1, wherein the base comprises an initial substrate and a second mask layer on a surface of the initial substrate.
10. The method of forming a semiconductor structure of claim 9, wherein patterning the second region with the second mask structure and patterning the first region with the third mask structure comprises: etching the second mask layer by taking the second mask structures and the third mask structures as masks, forming a plurality of first intermediate mask structures which are separated from each other on the initial substrate of the first area, and forming a plurality of second intermediate mask structures which are separated from each other on the initial substrate of the second area; and etching the initial substrate by taking the first intermediate mask structures and the second intermediate mask structures as masks until a substrate and the first fins and the second fins on the substrate are formed.
11. The method of forming a semiconductor structure of claim 10, wherein the second mask layer comprises: the mask comprises a lower second mask layer and an upper second mask layer positioned on the surface of the lower second mask layer, wherein the material of the upper second mask layer is different from that of the first mask layer, and the material of the upper second mask layer is different from that of the lower second mask layer.
12. The method of forming a semiconductor structure of claim 11, wherein the forming of a plurality of first reticle structures and a plurality of second reticle structures comprises: performing first etching treatment by taking the second mask structures and the third mask structures as masks, and etching the upper second mask layer and the lower second mask layer until the initial substrate surface of the first region is exposed; after the first etching treatment, carrying out second etching treatment on the lower second mask layer until the initial substrate surface of the second region is exposed; the etching rate of the material of the upper layer second mask layer in the first etching treatment process is larger than that of the material of the upper layer second mask layer in the second etching treatment process, and the etching selection ratio of the material of the lower layer second mask layer to the material of the initial substrate in the second etching treatment process is more than 5.
13. The method of forming a semiconductor structure of claim 11, wherein the forming of a plurality of first reticle structures and a plurality of second reticle structures further comprises: and removing the second mask structure and the third mask structure after the first etching treatment and before the second etching treatment.
14. The method of forming a semiconductor structure of claim 11, wherein a material of the upper second mask layer comprises silicon nitride and a material of the lower second mask layer comprises silicon oxide.
15. The method of claim 1, wherein an etch rate of a material of the first mask layer is greater than an etch rate of a material of the modified region in the process of etching the first mask layer.
16. The method of claim 1, wherein the first mask structure is formed using a self-aligned double patterning process or a self-aligned multiple patterning process.
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