CN116761432A - Memory and electronic equipment - Google Patents

Memory and electronic equipment Download PDF

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Publication number
CN116761432A
CN116761432A CN202210204785.9A CN202210204785A CN116761432A CN 116761432 A CN116761432 A CN 116761432A CN 202210204785 A CN202210204785 A CN 202210204785A CN 116761432 A CN116761432 A CN 116761432A
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China
Prior art keywords
control gate
memory
doped region
gate
memory cell
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CN202210204785.9A
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Chinese (zh)
Inventor
焦慧芳
王敬元璋
范鲁明
孙清清
李向辉
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Fudan University
Huawei Technologies Co Ltd
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Fudan University
Huawei Technologies Co Ltd
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Application filed by Fudan University, Huawei Technologies Co Ltd filed Critical Fudan University
Priority to CN202210204785.9A priority Critical patent/CN116761432A/en
Priority to PCT/CN2023/072818 priority patent/WO2023165283A1/en
Publication of CN116761432A publication Critical patent/CN116761432A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

The embodiment of the application provides a memory with a TFET and electronic equipment with the memory with the TFET. Relates to the technical field of memories. Not only can low-power consumption operation be realized, but also the use reliability of the memory can be improved. The memory comprises a substrate with a first doping region and a second doping region with the same doping type, wherein a memory unit is arranged on the substrate, the memory unit comprises a memory part, a gate tube and a tunneling field effect transistor TFET which are positioned at two sides of the memory part, a control gate of the memory part and a control gate of the tunneling field effect transistor TFET are insulated, and the control gate of the memory part and the control gate of the gate tube are insulated. Therefore, the probability of breakdown of the gate dielectric layer of the memory unit can be reduced, and the use reliability and durability of the memory are improved.

Description

Memory and electronic equipment
Technical Field
The present application relates to the field of memory technologies, and in particular, to a split-gate nonvolatile memory with a tunneling field effect transistor, and an electronic device including the nonvolatile memory.
Background
Flash memory (flash memory) is a type of nonvolatile memory that does not lose power-off data. Particularly, embedded flash (eflash) has become a standard of a micro controller unit (microcontroller unit, MCU), which greatly simplifies the supply chain of related products of the MCU, reduces the cost, simplifies the application, and improves the performance and reliability of the MCU.
It is necessary to design a flash memory that can reduce power consumption, improve reliability and durability, for example, to design a memory cell that can not only reduce operating voltage, but also reduce the probability of breakdown of a gate dielectric layer in the memory cell under the action of a strong electric field.
Disclosure of Invention
The application provides a memory and an electronic device with the same. The main purpose is to provide a flash memory structure of a memory unit comprising TFET, a gate tube and a memory part, the flash memory structure not only can reduce the operation voltage, but also can reduce the probability of breakdown of a gate dielectric layer of the memory unit so as to improve the use reliability of the flash memory structure.
In order to achieve the above purpose, the application adopts the following technical scheme:
in one aspect, the present application provides a memory device, the memory device including a substrate made of a semiconductor material, such as a P-type semiconductor substrate, the surface of the semiconductor substrate being doped to form a first doped region and a second doped region having the same doping type, such as the first doped region and the second doped region each being N-type, a region of the semiconductor substrate between the first doped region and the second doped region forming a channel region, at least one memory cell being disposed on the substrate, any of the memory cells including a memory portion, a tunneling field effect transistor, and a gate.
Wherein, a charge storage layer insulated from the substrate is arranged on the substrate, the charge storage layer can be a charge trapping layer, and a first control gate insulated from the charge storage layer is arranged on the charge storage layer; a second control gate insulated from the first doped region is arranged on the first doped region; the second doped region is provided with a third control gate insulated from the second doped region.
The storage part comprises a channel region, a charge storage layer and a first control gate, wherein the first control gate is arranged on one side of the charge storage layer, which is far away from the substrate, and is insulated from the charge storage layer; the tunneling field effect transistor comprises a first doped region, a channel region and a second control gate, wherein the second control gate is arranged on the first doped region and is insulated from the first doped region; the gate tube comprises a second doping region, a channel region and a third control gate, wherein the third control gate is arranged on the second doping region and is insulated from the second doping region.
And the first control gate of the storage part is insulated from the second control gate of the tunneling field effect transistor, and the first control gate of the storage part is also insulated from the third control gate of the gate tube.
From the structural view, the control gate in the memory provided by the application comprises not only the first control gate but also the second control gate and the third control gate, so that the memory unit comprises not only a memory part but also a gate tube and a tunneling field effect transistor (tunneling field effect transistor, TFET). In this way, the operation voltage can be reduced during the program and erase operations, and the power consumption of the memory can be reduced, for example, when the memory cell is in the erase operation, the band-tunneling phenomenon can occur at the interface between the first doped region and the channel region not only under the voltage control of the second control gate of the TFET, but also under the voltage control applied to the first doped region, so that compared with the memory cell which is not formed with the TFET, the voltage applied to the first doped region can be lower, the voltage applied to the second control gate is also smaller, and further, the erase power consumption can be reduced.
In addition, the control gate of the storage portion and the control gates of the two other transistor devices (including the gate tube and the gate tube) are electrically insulated, that is, the storage portion, that is, the gate control of the storage portion, can be controlled by the first control gate separately, which is different from the gate tube and the gate control of the gate tube. In this way, during the programming operation and the erasing operation, different voltages can be applied to the storage part, the gate tube and the TFET respectively, for example, during the programming operation, positive high voltage can be applied to the first control gate of the storage part, and lower positive low voltage can be applied to the second control gate of the TFET and the third control gate of the gate tube, so that the gate dielectric layer of the TFET and the gate dielectric layer of the gate tube cannot be affected by the positive high voltage of the first control gate, and are damaged or even broken down, and therefore, the gate dielectric layer of the TFET and the gate dielectric layer of the gate tube can be protected, so that the working reliability and durability of the storage unit are improved, and the service performance of the memory is improved.
In summary, the memory unit including the memory portion, the TFET and the gate tube provided by the application can realize low power consumption operation, and can control the gate independently, so that the durability and reliability of the whole memory unit can be further improved.
In one implementation, the second control gate and the third control gate are electrically connected.
In the design, the second control gate and the third control gate are electrically connected, so that the gate tube and the TFET can be simultaneously controlled by the control voltage of one control end from the control mode, and compared with the control of the gate tube and the TFET by adopting two control ends respectively, the number of the operation voltages can be reduced, and the control mode is simplified. In addition, if the memory cell is applied to a memory array, the wiring mode of the memory array can be simplified, and the integration density of the memory cell can be improved.
In one possible implementation, a metal interconnection layer is formed on a side of the first control gate away from the charge storage layer, the metal interconnection layer being insulated from the first control gate; and the second control gate, the metal interconnection layer, and the third control gate are connected such that the second control gate is electrically connected to the third control gate through the metal interconnection layer.
The implementation manner shows how to realize the electrical connection between the second control gate and the third control gate, specifically, when the memory unit is manufactured, a metal interconnection layer can be stacked on the side surface of the first control gate, which is away from the charge storage layer, and the third control gate of the gate tube is electrically connected with the second control gate of the TFET through the metal interconnection layer.
In one implementation, the second control gate, the metal interconnect layer, and the third control gate are integrally formed as a layer structure.
That is, a metal layer may be stacked on a side of the first control gate facing away from the charge storage layer, where the metal layer forms a third control gate of the gate tube and a second control gate of the TFET, and forms a metal interconnect layer connecting the second control gate and the third control gate.
In one implementation, the second control gate, the metal interconnect layer, and the third control gate are all fabricated using a previous process.
Namely, when the memory unit is prepared, the third control gate of the gate tube and the second control gate of the TFET can be directly and electrically connected through the metal interconnection layer.
In one implementation, the memory further includes: a metal interconnect layer, a first conductive via and a second conductive via; the metal interconnection layer is formed on one side of the first control gate, the second control gate and the third control gate, which is far away from the substrate; the second control gate is electrically connected with the metal interconnection layer through the first conductive channel; the third control gate is electrically connected to the metal interconnect layer through the second conductive via such that the second control gate is electrically connected to the third control gate through the first conductive via, the second conductive via, and the metal interconnect layer.
In such a process structure for electrically connecting the second control gate and the third control gate, the metal interconnection layer, the first conductive via and the second conductive via are not formed at the time of manufacturing the memory cell, for example, when the memory cell is manufactured by a previous process, the metal interconnection layer, the first conductive via and the second conductive via for electrically connecting the second control gate and the third control gate may be manufactured by a subsequent process. In this way, more setting space can be reserved for the memory unit prepared by adopting the previous process, so that the integration density of the memory unit is improved.
In one implementation, the memory cell is fabricated using a front-end process, and the metal interconnect layer, the first conductive via, and the second conductive via are all fabricated using a back-end process.
In one implementation, the memory further includes: the source line, the bit line, the word line and the gate control line are electrically connected with the second doped region; the bit line is electrically connected with the first doped region; the word line is electrically connected with the second control gate and the third control gate; the gate control line is electrically connected with the first control gate.
That is, in such a memory, only four sets of control signal lines, i.e., source lines, bit lines, word lines, and gate lines, need to be drawn to control the program operation, the erase operation of the memory. In a process structure that can be implemented, these control signal lines can be fabricated by a subsequent process.
In one implementation, the substrate is a P-type substrate, and the first doped region and the second doped region are both N-type doped regions; during programming of the memory, the first control gate is used for receiving a first programming positive voltage, and the second control gate and the third control gate are both used for receiving a second programming positive voltage, wherein the first programming positive voltage is greater than the second programming positive voltage.
Since the storage portions are individually controlled, a larger programming positive voltage can be applied to the first control gate and a lower programming positive voltage can be applied to the second control gate and the third control gate during programming operation, so that the influence of the larger positive voltage on the gate tube region and the TFET region is reduced or even eliminated, for example, the possibility of damage to the gate dielectric of the gate tube and the gate dielectric of the TFET can be reduced.
In one implementation, the substrate is a P-type substrate, and the first doped region and the second doped region are both N-type doped regions; in the erasing process of the memory, the first control gate is used for receiving a first erasing negative voltage, the second control gate and the third control gate are used for receiving a second erasing negative voltage, and the absolute value of the first erasing negative voltage is larger than that of the second erasing negative voltage.
Similarly to the programming operation described above, during the erasing operation, since the storage portion is controlled by the first control gate alone, when a negative voltage is applied to the first control gate, a negative voltage with a lower absolute value can be applied to the second control gate and the third control gate, and the gate dielectric of the gate tube and the gate dielectric of the TFET can be protected, thereby improving the endurance performance of the storage unit.
In one implementation, the at least one memory cell includes a first memory cell and a second memory cell, the first memory cell and the second memory cell being arranged in adjacent rows in a direction parallel to the substrate; the second doped region of the first memory cell and the second doped region of the second memory cell share the same doped region to form a shared second doped region; and the third control gate of the first memory cell is located in the common second doped region and the third control gate of the second memory cell is insulated from the third control gate of the second memory cell.
It can be understood that in this embodiment, the gate tubes of two adjacent memory cells may share a doped region, so that the area occupied by each memory cell may be reduced to improve the integration density.
In another aspect, the present application further provides an electronic device, where the electronic device includes a circuit board and a memory in any of the foregoing implementation manners of the first aspect, and the memory is disposed on the circuit board and electrically connected to the circuit board.
In the electronic equipment provided by the application, the memory is included, and each memory unit of the memory not only comprises a memory part, but also comprises the gate tube and the TFET, so that the low-power-consumption operation of the memory unit can be realized; in addition, the first control gate of the storage part, the third control gate of the gate tube and the second control gate of the TFET are electrically insulated, so that when high voltage is applied to the storage part, the high voltage does not influence the gate tube and the TFET, the gate dielectric layers of the gate tube and the TFET can be prevented from being damaged, and the use reliability and the durability of the storage unit are improved.
Drawings
Fig. 1 is a partial circuit diagram of an electronic device according to an embodiment of the present application;
FIG. 2 is a partial circuit diagram of a memory according to an embodiment of the present application;
FIG. 3 is a process block diagram of a memory cell of a memory;
FIG. 4a is a schematic diagram illustrating the programming principle of the memory shown in FIG. 3;
FIG. 4b is a schematic diagram illustrating the erasing principle of the memory shown in FIG. 3;
FIG. 5 is a process structure diagram of a memory cell of a memory according to an embodiment of the present application;
FIG. 6a is a schematic diagram of the programming principle of the memory shown in FIG. 5;
FIG. 6b is a schematic diagram illustrating the erasing principle of the memory shown in FIG. 5;
FIG. 7 is a process structure diagram of a memory cell of a memory according to an embodiment of the present application;
FIG. 8 is a process structure diagram of a memory cell of a memory according to an embodiment of the present application;
FIG. 9 is a process structure diagram of two memory cells of a memory according to an embodiment of the present application;
FIG. 10 is a process structure diagram of a memory cell of a memory according to an embodiment of the present application;
fig. 11 is a partial circuit diagram of a memory array of a memory according to an embodiment of the present application.
Reference numerals:
100-an electronic device;
200-a central processing unit;
300-memory;
400-memory cell;
1-a substrate;
11-a first doped region;
12-a second doped region;
a 2-charge storage layer;
31-a first control gate;
32-a second control gate;
33-a third control gate;
4. 81, 82-insulating layers;
51. 52, 53-gate dielectric;
61-a storage section;
62-TFET；
63, selecting a tube;
71-a first part;
72-a second part;
73-a third portion;
a 9-metal interconnect layer;
101-a first conductive path;
102-a second conductive path.
Detailed Description
Before describing the embodiments of the present application, the technical terms of the present application will be explained in detail, as follows.
Hot Electron (HE): electrons having high energy, when the electric field in the channel is strong, hot electrons are generated due to channel avalanche breakdown.
Channel hot electron (channel hot electron, CHE) injection: also known as channel avalanche injection, a phenomenon in which some of the high energy hot electrons in the channel are injected into the gate oxide. Because when the electric field in the channel is strong, hot electrons are multiplied by the channel avalanche breakdown, if the energy accumulated between the two collisions is sufficient to cross the Si-gate oxide interface barrier, these hot electrons may be injected into the gate oxide, such injection being called CHE injection.
Band tunneling (band to band Tunneling, BTBT): in the reverse bias state, when some unoccupied energy states in the N-region conduction band and some occupied energy states in the P-region valence band have the same energy, and the potential barrier region is very narrow, electrons tunnel from the P-region valence band to the N-region conduction band, so that band tunneling is realized.
Hot Hole (HH): is a hole with high energy.
Hot hole injection (hot hole injection, HHI) injection: namely, a phenomenon that part of high-energy hot holes in a channel are injected into a gate oxide layer.
Embodiments of the present application will be described below with reference to the accompanying drawings.
The technical scheme of the application can be applied to various electronic devices adopting a memory, for example, fig. 1 is a circuit block diagram of an electronic device 100 provided in an embodiment of the application, where the electronic device 100 may be a terminal device, for example, a mobile phone, a tablet computer, a smart bracelet, or may be a personal computer (personal computer, PC), a server, a workstation, etc.
By way of example, and again as in fig. 1, the electronic device 100 may include a memory 300 and a central processing unit (central processing unit, CPU) 200, etc. Wherein the CPU200 may be electrically connected to the memory 300 through a bus. For example, the memory may be a flash memory (flash memory).
Fig. 2 is a circuit block diagram of a flash memory according to an embodiment of the present application. The memory 300 may include a memory array 310, a decoder 320, a driver 330, a timing controller 340, a buffer 350, and an input-output driver 360. The memory array 310 includes a plurality of memory cells 400 arranged in an array, wherein each memory cell 400 may be used to store 1bit or more of data. The memory array 310 further includes signal control lines such as Word Lines (WL), bit Lines (BL), and the like. Each memory cell 400 is electrically connected to a corresponding word line WL, bit line BL. One or more of the word lines WL and the bit lines BL are used to select the memory cells 400 to be read and written in the memory array by receiving the level output by the control circuit, so as to implement the read and write operation of data.
In the memory 300 structure shown in fig. 2, the decoder 320 is configured to decode according to the received address to determine the memory cell 400 that needs to be accessed. The driver 330 is used to control the level of the signal line according to the decoding result generated by the decoder 320, thereby realizing access to the designated memory cell 400. The buffer 350 is used for buffering the read data, and may be, for example, a first-in first-out (FIFO) buffer. The timing controller 330 is used for controlling the timing of the buffer 350 and controlling the driver 330 to drive the signal lines in the memory array 310. The input-output driver 360 is used to drive transmission signals, such as to drive received data signals and to drive data signals to be transmitted, so that the data signals can be transmitted over a long distance.
In some implementations, the memory 300 and the central processor 200 described above may be integrated in one chip, and such memory may be referred to as embedded memory.
Alternatively, in other implementations, the memory 300 and the central processor 200 are integrated in different chips, which may be referred to as stand-alone memory.
Fig. 3 is a cross-sectional view showing a part of a flash structure, and fig. 3 shows only one of a plurality of memory cells in the flash structure, and as can be seen from fig. 3, the flash structure includes a memory portion 61 for storing charges, a gate tube 63, and further includes tunneling field effect transistors (tunneling field effect transistor, TFET) 62.
Fig. 4a illustrates a programming process of the flash structure shown in fig. 3, and fig. 4b illustrates an erasing process of the flash structure shown in fig. 3. Also, the programming principle and the erasing principle are described by taking the substrate 1 as a P-type substrate, and the first doped region 11 and the second doped region 12 as N-type doping as examples. Specific programming and erase operations are described below.
In connection with fig. 4a, during programming of the flash structure, hot electrons are injected into the charge storage layer 2 using source injection (source side injection, SSI), channel hot electron (channel hot electron, CHE) injection mechanism (also called hot carrier injection). It is simply understood that applying a voltage greater than the threshold voltage to the control gate, grounding the second doped region 12 (which may be the source), applying a suitable positive voltage to the first doped region 11 (which may be the drain), under which conditions the region of the channel region adjacent to the second doped region 12 forms an inversion channel (fig. 4a shows the approximate location of the inversion channel), the strong electric field between the first doped region 11 and the second doped region 12 acts to generate a large number of electron hole pairs, and the generated hot electrons are injected into the charge storage layer 2 and stay in the process of flowing to the drain (i.e., the first doped region 11), enabling programming.
In connection with fig. 4b, during the erasing process of the flash structure, the second doped region 12 is grounded, a negative voltage (greater than a threshold voltage) is applied to the control gate, a proper positive voltage is applied to the first doped region 11, and band-tunneling occurs at the interface between the first doped region 11 and the substrate 1, so that hot holes are injected into the charge storage layer 2 and are neutralized with electrons stored in the charge storage layer 2, thereby realizing the erasing.
In the erasing process shown in fig. 4b, since the present application not only has the storage portion 61 and the gate tube 63, but also has the TFET62, under the control of the TFET62, the voltage value applied to the first doped region 11 is reduced, and the voltage value applied to the control gate of the TFET62 is also reduced, so that the erasing power consumption of the storage unit is reduced.
The reason for the reduced erase power consumption can be understood that when a voltage is applied to the first doped region 11, the interface between the first doped region 11 and the channel region will undergo band-with-band tunneling, i.e. the valence band electrons of the P-well of the substrate tunnel to the first doped region 11, thus leaving a large number of hot holes in the P-well. Also, the band-to-band tunneling phenomenon at the interface of the first doped region 11 and the channel region may occur after the voltage is applied to the control gate of the TFET62, leaving a large number of hot holes in the P-well.
That is, as known from the erase process described above in connection with fig. 4b, the generation of a large number of holes in the P-well is based on the action of two voltages, namely the action of the voltage on the control gate of the TFET and the action of the voltage on the first doped region. In this way, the voltage applied to the first doped region may be lower than in the prior art when the generated hot hole content is comparable, as long as the voltage applied to the control gate of TFET62 is greater than the threshold voltage, and further, the erase power consumption of the memory cell is reduced.
Fig. 5 is a block diagram of one memory cell 400 of a plurality of memory cells in another flash structure according to an embodiment of the present application. The same as the memory unit of fig. 4 described above, the memory unit also includes the memory portion 61, the TFET62, and the gate tube 63, so that low power consumption operation can be realized; the difference is that: the storage part 61, the TFET62 and the gate tube 63, and the storage part 61, the TFET62 and the gate tube 63 adopt a split gate structure.
The structure of the memory cell shown in fig. 5 is specifically described below.
In the memory cell 400 of the flash memory, the substrate 1 is made of a semiconductor material, for example, a P-type semiconductor substrate, a first doped region 11 and a second doped region 12 having the same doping type are formed in the substrate 1 through a doping process, and the first doped region 11 and the second doped region 12 may each be N-type, and one of the first doped region 11 and the second doped region 12 forms a Source (Source), the other one forms a Drain (Drain), and a channel region is formed in a region of the substrate 1 between the first doped region 11 and the second doped region 12.
Of course, the substrate 1 of the semiconductor may be N-type, and the first doped region 11 and the second doped region 12 may each be P-type.
Referring again to fig. 5, the charge storage layer 2 of the memory cell is formed on and insulated from the channel region, for example, an insulating layer 4 may be formed between the charge storage layer 2 and the channel region. In addition, the memory cell further includes a first control gate 31, a second control gate 32, and a third control gate 33.
Wherein a first control gate 31 is formed on the side of the charge storage layer 2 remote from the substrate 1, this first control gate 31 may be referred to as Control Gate (CG). A gate dielectric layer 51 is formed between the first control gate 31 and the charge storage layer 2.
The second control gate 32 is formed over the first doped region 11, which first doped region 11 may be referred to as a Tunneling Gate (TG). A gate dielectric layer 52 is formed between the second control gate 32 and the charge storage layer 2.
A third control gate 33 is formed over the second doped region 12, and this third control gate 33 may be referred to as a Select Gate (SG). A gate dielectric layer 53 is formed between the third control gate 33 and the charge storage layer 2.
It should be explained that: the second control gate 32 is formed on the first doped region 11, meaning that at least part of the orthographic projection of the second control gate 32 on the substrate 1 is located within the boundaries of the first doped region 11. The third control gate 33 is formed on the second doped region 12, meaning that at least part of the orthographic projection of the third control gate 33 on the substrate 1 is located within the boundaries of the second doped region 12. The dashed box in fig. 5 shows the approximate locations of the storage portion 61, TFET62, and gate tube 63.
That is, as shown in fig. 5, the storage section 61 outlined by a dotted line includes: a channel region and a charge storage layer 2, and a first control gate 31.
As further shown in fig. 5, the TFET62 outlined by the dashed line includes: a first doped region 11, a channel region, and a second control gate 32.
As shown in fig. 5, the gate tube 63 outlined by the dotted line includes: a second doped region 12, and a channel region, and a third control gate 33.
It will be appreciated that, in conjunction with fig. 5, the channel region includes a first portion 71, a second portion 72, and a third portion 73, the second portion 72 being adjacent to the first doped region 11, the third portion 73 being adjacent to the second doped region 12, the portion between the second portion 72 and the third portion 73 being the first portion 71. It should be noted that the first portion 71 and the third portion 73 may partially overlap, and the first portion 71 and the second portion 72 may also partially overlap.
The channel region of TFET62 may be the second portion 72, the channel region of the memory portion 61 may be the first portion 71, and the channel region of gate tube 63 may be the third portion 73.
In addition, in the memory cell 400 according to the present application, as shown in fig. 5, the first control gate 31 of the memory portion 61 and the second control gate 32 of the TFET62 are insulated from each other, and the first control gate 31 of the memory portion 61 and the third control gate 33 of the gate tube 63 are insulated from each other.
In a process that can be implemented, an insulating layer 81 may be formed between the second control gate 32 and the first control gate 31; similarly, in order to realize insulation between the first control gate 31 of the memory portion 61 and the third control gate 33 of the gate tube 63, an insulating layer 82 may be formed between the third control gate 33 and the first control gate 31. In this way, the first control gate 31 and the second control gate 32 are electrically isolated, and the first control gate 31 and the third control gate 33 are also electrically isolated.
In the programming operation of the memory cell shown in fig. 5, fig. 6a shows the programming process of the memory cell shown in fig. 5, specifically, the SSI programming is still performed in the flash programming process, it can be understood that when a voltage of 0V is applied to the second doped region 12 and a positive high voltage is applied to the first doped region 11, a positive low voltage is applied to the second control gate 32 and the third control gate 33, and a positive high voltage is applied to the first control gate 33, a large number of electron hole pairs are generated in the channel region between the source and the drain under the action of a strong electric field between the source and the drain, and the generated hot electrons are injected into the charge storage layer 2 (such as a charge floating layer) and stay in the process of flowing to the source, so as to realize programming.
That is, in performing a programming operation, a positive low voltage is applied to the second control gate 32 of the TFET62 and the third control gate 33 of the gate tube 63, and conversely, a positive high voltage is applied to the first control gate 31 of the memory portion 61, so that an electric field is generated to the gate dielectric layer 51 between the first control gate 31 and the charge trapping layer 2 and the insulating layer 4 between the charge trapping layer 2 and the channel region by the voltage applied to the first control gate 33, and similarly, an electric field is generated to the gate dielectric layer 52 between the second control gate 32 and the first doped region 11 by the voltage applied to the second control gate 32, and an electric field is generated to the gate dielectric layer 53 between the third control gate 33 and the second doped region 12 by the voltage applied to the third control gate 33, and, because the voltage applied to the second control gate 32 and the third control gate 33 is lower than the voltage applied to the first control gate 31, a breakdown phenomenon occurs in which a field breakdown phenomenon occurs between the second control gate 32 and the first doped region 11 and the gate dielectric layer 53 is lower than the field between the second control gate 33 by the voltage applied to the second control gate 32 and the third doped region 11.
In connection with fig. 6b, fig. 6b shows an erasing process of the memory cell shown in fig. 5, in the erasing process of the flash structure, the second doped region 12 is grounded, a voltage close to 0V is applied to the third control gate 33, a voltage greater than a threshold value is applied to the first control gate 31, a small positive voltage is applied to the second control gate 32, band-to-band tunneling occurs at the interface between the first doped region 11 and the substrate 1, and hot holes are injected into the charge storage layer 2 and neutralized with electrons stored in the charge storage layer 2, so as to realize erasing.
It can also be seen from the above-described erasing process of the memory cell that, when the erasing operation is performed, the voltages applied to the second control gate 32 and the third control gate 33 are much smaller than the voltages applied to the first control gate 33, so that the high voltage can be prevented from damaging the gate dielectric layer 52 located between the second control gate 32 and the first doped region 11, and the high voltage can be prevented from damaging the gate dielectric layer 53 located between the third control gate 33 and the second doped region 12, so as to improve the reliability of the memory cell.
Continuing with the illustration of fig. 5, the equivalent insulating layer of the storage portion 61 is thicker than the insulating layer of the TFET62 and the insulating layer of the gate tube 63, and thus, whether the programming process or the erasing process is performed, even if a high voltage is applied to the first control gate 31, the probability of being broken down is much smaller than the probability of being broken down of the other two transistors (including the TFET and the gate tube) due to the greater thickness of the equivalent insulating layer of the storage portion 61.
As for the equivalent insulating layer of the above-mentioned memory portion 61, it can be understood that the sum of the thickness (the dimension in the direction perpendicular to the substrate 1) of the gate dielectric layer 51, the thickness of the charge storage layer 2, and the thickness of the insulating layer 4 in fig. 5; the thickness of the insulating layer of the TFET62 is the thickness of the gate dielectric layer 52, and the thickness of the insulating layer of the gate tube 63 is the thickness of the gate dielectric layer 53.
Based on the above description of the structure of the memory cell 400 according to the present application and the description of the program and erase operations of the memory cell, it can be obtained that, since the first control gate 61 of the memory portion 61 is insulated from the third control gate 33 of the gate tube 63 and the second control gate 32 of the TFET62, which are given in the present application, the first control gate 61 to which high voltage is applied does not affect the gate tube 63 and the TFET62 during the program and erase processes, so that the performance of the gate dielectric layers of the gate tube 63 and the TFET62 can not be damaged, and even if high voltage is applied to the first control gate 31, damage to the memory portion 61 is limited.
In addition, for the memory cell 400, a low voltage operation, for example, a voltage applied to the first doped region 11 is approximately 3V and a voltage applied to the second control gate 32 is approximately-1V when an erase operation is performed, so that the memory cell provided by the present application can achieve low power consumption and improve reliability and durability of the memory cell.
The same voltage may be applied to the second control gate 32 and the third control gate 33 during the program, erase, and read operations that may be implemented, and then, in the process structure that may be implemented, the second control gate 32 may be electrically connected to the third control gate 33 so that the same voltage is applied to both the third control gate 33 and the second control gate 32.
Among the process structures that can be implemented, there are various ways of implementing the electrical connection between the second control gate 32 and the third control gate 33, and two of the process structures that can be implemented are described below in conjunction with the accompanying drawings, as will be described in detail below.
Fig. 7 shows a process structure diagram for realizing the electrical connection of the second control gate 32 and the third control gate 33. Specifically, the metal interconnection layer 9 may be formed on the sides of the first, second, and third control gates 31, 32, and 33 remote from the substrate 1, and the metal interconnection layer 9 connects the second and third control gates 32 and 33 together such that the second control gate 32 is electrically connected to the third control gate 33 through the metal interconnection layer 9.
In addition, an insulating layer is formed between the metal interconnection layer 9 and the first control gate 31 to electrically isolate the first control gate 31 and the third control gate 33 and to electrically isolate the first control gate 31 and the second control gate 32.
In the process steps that may be implemented in fabricating the memory cell 400 shown in fig. 7, an insulating layer may be formed on the channel region of the substrate 1, then the charge storage layer 2 may be formed on the insulating layer, then the gate dielectric layer may be formed, then the first control gate 31 may be formed on the gate dielectric layer on the charge storage layer 2, then the gate dielectric layer may be formed on the first control gate 31, and the gate dielectric layer may include a gate dielectric layer formed on the first doped region and the second doped region, and may further include a gate dielectric layer formed on the first control gate 31, and then a metal layer may be formed on the gate dielectric layer to form the second control gate 32, the third control gate 33, and the metal interconnection layer 9. That is, the second control gate 32, the third control gate 33, and the metal interconnection layer 9 are formed as an integrally formed layer structure.
The layer structure in which the second control gate 32, the third control gate 33 and the metal interconnection layer 9 are integrally formed can be understood as: the materials used for the second control gate 32, the third control gate 33 and the metal interconnection layer 9 are the same, and the adjacent second control gate 32 and metal interconnection layer 9 are not divided into interfaces, and similarly, the adjacent third control gate 33 and metal interconnection layer 9 are not divided into interfaces.
Also, as shown in fig. 7, the respective layer structures (including each control gate, gate dielectric layer, charge storage layer) and metal interconnect layer 9 in the memory cells in this structure are fabricated on substrate 1 by a previous process.
When the process structure shown in fig. 7 is adopted, each memory cell has four connection ports, namely, the connection port C1, the connection port C2, the connection port C3 and the connection port C4 shown in fig. 7, compared with the case that the third control gate 33 of the gate tube 63 and the second control gate 32 of the TFET62 are mutually insulated, the number of operating voltages can be reduced, if the memory cell is applied to a memory array, the wiring difficulty of the memory array can be reduced, and the integration density of the memory cell can be improved.
Fig. 8 shows another process configuration for electrically connecting the second control gate 32 and the third control gate 33. Specifically, compared to fig. 7 described above, not only the metal interconnection layer 9 but also the first conductive via 101 and the second conductive via 102 are included, wherein the metal interconnection layer 9 is formed on the sides of the first control gate 31, the second control gate 32, and the third control gate 33 that are away from the substrate 1, the second control gate 32 is electrically connected to the metal interconnection layer 9 through the first conductive via 101, and the third control gate 33 is electrically connected to the metal interconnection layer 9 through the second conductive via 102, so that the second control gate 32 is electrically connected to the third control gate 33 through the first conductive via 101, the second conductive via 102, and the metal interconnection layer 9.
In an alternative manufacturing process, when manufacturing the memory cell shown in fig. 8, the structure shown in fig. 7 may be manufactured first, and the manufacturing method of the structure shown in fig. 7 is described above, which is not described herein again, and then, the metal interconnection layer 9 above the first control gate 31 is removed by using a grinding process, so as to obtain the structure shown in fig. 8.
In the structure shown in fig. 8, the identification metal interconnection layer 9, the first conductive via 101 and the second conductive via 102 are represented by lines, and in a practical alternative process structure, the metal interconnection layer 9 may be a metal layer, and the first conductive via 101 and the second conductive via 102 may be through silicon vias (through silicon via, TSV) formed in dielectric layers, respectively.
In the process structure diagram shown in fig. 8, each layer structure (including each control gate, gate dielectric layer, and charge storage layer) of the memory cell 400 is fabricated on the substrate 1 by a previous process; and the metal interconnection layer 9, the first conductive via 101 and the second conductive via 102 are manufactured by a subsequent process.
When the metal interconnection layer 9, the first conductive via 101 and the second conductive via 102 shown in fig. 8 are fabricated by using the subsequent process, more accommodating spaces can be reserved for the memory cells fabricated by using the previous process, so as to improve the storage density of the memory cells.
In order to further increase the memory density of the memory cell 400, as shown in fig. 9, fig. 9 shows a process structure including the memory cell 401 and the memory cell 402, specifically, the memory cell 401 and the memory cell 402 may be adjacently arranged along a direction parallel to the substrate 1, and the second doped region 12 of the memory cell 401 may be adjacent to the second doped region 12 of the memory cell 402 and may share the same doped region, so as to form a shared second doped region, that is, it is understood that the memory cell 401 and the memory cell 402 share the source terminal.
It is also possible to understand the structure shown in fig. 9 that the gate tube 63 of the memory unit 401 is disposed close to the gate tube 63 of the memory unit 402, so that the second doped region of the memory unit 401 is shared with the second doped region of the memory unit 402, so as to reduce the integration area of a plurality of memory units, for example, the area occupied in the X direction as shown in fig. 9 can be reduced, and the integration number of memory units per unit area can be increased.
In order to avoid the gate tube 63 of the memory cell 401 being electrically connected to the gate tube 63 of the memory cell 402, as shown in fig. 9, the third control gate 33 of the memory cell 401 located in the common second doping region and the third control gate 33 of the memory cell 402 located in the common second doping region are insulated.
In the flash structure according to the present application described above, the charge storage layer 2 may be a charge trapping layer, for example, a charge trapping layer made of silicon nitride, and thus, since a charge trapping layer made of an insulating material is used as the charge storage layer, electrons are hard to escape once they are trapped therein.
In other embodiments, the charge storage layer 2 may be a floating gate layer, such as a floating gate layer made of polysilicon.
Compared with the flash structure prepared by the floating gate layer, the flash structure prepared by the charge trapping layer has a larger working temperature-saving range, for example, the working temperature-saving range of the flash structure prepared by the charge trapping layer can be-40 ℃ to +150 ℃, and the working temperature-saving range of the flash structure prepared by the floating gate layer can be-40 ℃ to +125 ℃.
In the above-described flash structure with different structures, the first control gate 31, the second control gate 32, and the third control gate 33 may be made of poly-Si (p-Si, polysilicon).
The material of the insulating layer and the gate dielectric layer can be SiO 2 (silica), al 2 O 3 (aluminum oxide), hfO 2 (hafnium dioxide), zrO 2 (zirconia) TiO 2 (titanium dioxide), Y 2 O 3 (yttrium oxide) and Si 3 N 4 (silicon nitride) and the like.
In the flash memory according to the present application, control signal lines such as Source Lines (SL), bit Lines (BL), word Lines (WL), and gate control lines (control gate line, CL) are further included. As shown in fig. 10, fig. 10 shows the connection relationship of the corresponding structures of the respective control signal lines, specifically, the bit line BL is electrically connected to the first doped region 11, the source line SL is electrically connected to the second doped region 12, the gate control line CL is electrically connected to the first control gate 31, and the word line WL is electrically connected to the second control gate 32 and the third control gate 33.
Fig. 11 shows a partial structure of a memory array 310 of a flash structure, the memory array 310 including a plurality of memory cells, a plurality of word lines WL, a plurality of bit lines BL and a plurality of source lines SL, and a plurality of gate control lines CL. The memory cell may adopt any of the split gate structures of the memory cells according to the embodiments of the present application described above.
The plurality of bit lines BL and the plurality of source lines SL are arranged along a first direction X, the plurality of word lines WL and the plurality of gate control lines CL are arranged along a second direction Y, the first direction X is perpendicular to the second direction Y, the plurality of memory cells arranged along the second direction Y share one word line WL and one gate control line CL, and the plurality of memory cells arranged along the first direction X share one bit line BL and one source line SL. Fig. 11 shows only an exemplary structure of the layout of a plurality of signal lines and a plurality of memory cells, and the present application is not limited to the layout shown in fig. 11, but may be other layouts.
In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (11)

1. A memory, comprising:
a substrate; and
at least one memory cell formed on the substrate, any of the memory cells comprising:
a storage section comprising:
the channel region is positioned between the first doped region and the second doped region, the first doped region and the second doped region are formed in the substrate, and the doping types of the first doped region and the second doped region are the same;
a charge storage layer disposed on and insulated from the substrate;
a first control gate disposed on a side of the charge storage layer remote from the substrate and insulated from the charge storage layer;
A tunneling field effect transistor comprising:
the first doped region;
the channel region;
a second control gate disposed on and insulated from the first doped region;
the gate tube includes:
the second doped region;
the channel region;
a third control gate disposed on and insulated from the second doped region;
wherein the first control gate is insulated from the second control gate, and the first control gate is insulated from the third control gate.
2. The memory of claim 1, wherein the second control gate and the third control gate are electrically connected.
3. The memory of claim 2, wherein the memory further comprises:
a metal interconnection layer formed on a side of the first control gate away from the charge storage layer, the metal interconnection layer being insulated from the first control gate;
and the second control gate, the metal interconnection layer and the third control gate are connected such that the second control gate is electrically connected to the third control gate through the metal interconnection layer.
4. The memory of claim 3 wherein the second control gate, the metal interconnect layer and the third control gate are an integrally formed layer structure.
5. The memory of claim 2, wherein the memory further comprises:
a metal interconnection layer formed on a side of the first, second, and third control gates away from the substrate;
a first conductive via through which the second control gate is electrically connected to the metal interconnect layer;
and the third control gate is electrically connected with the metal interconnection layer through the second conductive channel, so that the second control gate is electrically connected with the third control gate through the first conductive channel, the second conductive channel and the metal interconnection layer.
6. The memory of claim 5, wherein the memory cell is fabricated using a prior process and the metal interconnect layer, the first conductive via, and the second conductive via are all fabricated using a subsequent process.
7. The memory according to any one of claims 1-6, further comprising:
a source line electrically connected to the second doped region;
a bit line electrically connected to the first doped region;
A word line electrically connected to both the second control gate and the third control gate;
and the grid control line is electrically connected with the first control grid.
8. The memory of any of claims 1-7, wherein the substrate is a P-type substrate, and the first doped region and the second doped region are both N-type doped regions;
during programming of the memory, the first control gate is used for receiving a first programming positive voltage, and the second control gate and the third control gate are both used for receiving a second programming positive voltage, wherein the first programming positive voltage is larger than the second programming positive voltage.
9. The memory of any of claims 1-8, wherein the substrate is a P-type substrate, and the first doped region and the second doped region are both N-type doped regions;
in the erasing process of the memory, the first control gate is used for receiving a first erasing negative voltage, and the second control gate and the third control gate are both used for receiving a second erasing negative voltage, wherein the absolute value of the first erasing negative voltage is larger than that of the second erasing negative voltage.
10. The memory according to any one of claims 1 to 9, wherein the at least one memory cell includes a first memory cell and a second memory cell, the first memory cell and the second memory cell being adjacently arranged in a direction parallel to the substrate;
The second doped region of the first memory cell and the second doped region of the second memory cell share the same doped region to form a shared second doped region;
and the third control gate of the first memory cell in the common second doped region is insulated from the third control gate of the second memory cell in the common second doped region.
11. An electronic device, comprising:
a circuit board;
the memory of any one of claims 1-10;
the memory is arranged on the circuit board and is electrically connected with the circuit board.
CN202210204785.9A 2022-03-03 2022-03-03 Memory and electronic equipment Pending CN116761432A (en)

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