CN108417575A - Flash cell, flash array and its operating method - Google Patents
Flash cell, flash array and its operating method Download PDFInfo
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- CN108417575A CN108417575A CN201810210422.XA CN201810210422A CN108417575A CN 108417575 A CN108417575 A CN 108417575A CN 201810210422 A CN201810210422 A CN 201810210422A CN 108417575 A CN108417575 A CN 108417575A
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
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Abstract
The present invention provides a kind of flash cell, flash memory permutation and its operating method, the flash cell includes：It is formed with the first doped region and the second doped region in substrate, the conduction type of first doped region and second doped region is opposite；Storage position over the substrate, and the region between first doped region and second doped region are formed, the storage position includes a floating boom and a control gate.Flash cell provided by the invention, use tunneling field-effect transistor (TFET), the conducting of raceway groove and the programming of flash cell are realized using band-to-band-tunneling principle, to inhibiting the punchthrough effect of short channel, improving programming efficiency and reducing overall power；In addition, flash cell provided by the present invention is conducive to the reduction of size, there is impetus to the reduction of storage area and the promotion of memory capacity of flash memories from now on.
Description
Technical field
The present invention relates to a kind of field of semiconductor manufacture more particularly to flash cell, flash array and its operating methods.
Background technology
Flash memory (flash memory) is a kind of non-volatile memory, and having will not disconnected electric stored data
Lose and can long-term preservation the characteristics of.Therefore the development of flash memory is very rapid in recent years, and with high integration, high storage speed
Degree and the flash memories of high reliability are widely used in including in the electronic products such as computer, mobile phone, server and equipment.
The performance to flash memory be improved with optimize when, first against be exactly each flash memory for constituting flash memories
The structure or operating principle of unit.In the prior art, the programming operation of flash cell is to utilize raceway groove or conventional source mostly
End thermoelectron injection is programmed, but ever-reduced instantly in characteristic size, is limited by physical size, flash memories
The problems such as how inhibiting the punchthrough effect of short channel, how improving programming efficiency and how to reduce power consumption be faced with.
Invention content
In order to which how inhibiting the punchthrough effect of short channel, how improving programming efficiency and such as above-mentioned flash cell solved
What reduces the problem of power consumption.The present invention provides a kind of flash cell, flash array and its operating methods.
The present invention provides a kind of flash cells, including：
Substrate is formed with the first doped region of N-type and the second doped region of p-type in the substrate；
Position is stored, is formed over the substrate, and the area between first doped region and second doped region
Domain, the storage position include a floating boom and a control gate, and the floating boom is formed over the substrate, and the control gate is located at described
The top of floating boom；
Wherein, described to store position and be provided commonly for positioned at first doped region for storing position both sides and the second doped region
The storage organization of flash cell is constituted, first doped region is used to constitute the drain region of the storage organization, second doping
Area is used to constitute the source region of the storage organization.
Preferably, there are two the storage positions for the flash cell tool；Wherein, there are two described for setting in the substrate
One doped region and second doped region, two first doped regions are arranged in the two of second doped region
Side；And two storage positions are respectively formed at the second doped region both sides, and it is located at second doped region and described
Between first doped region.
Preferably, further include an erasing grid, be formed in the top of second doped region, and be located at two storage positions
Between；The storage position respectively further comprises the wordline grid of a formation over the substrate, and the wordline grid are located at the control gate
With side of the floating boom far from the erasing grid；The floating boom and the control gate on the side wall close to the wordline grid with
And the bottom of wordline grid is formed with wordline gate dielectric layer.
Preferably, the control gate is formed with erasing grid side wall on the side wall close to the erasing grid, to prevent from wiping
When control gate and erasing grid between puncture.
Preferably, first doped region is located in substrate of the wordline grid far from the floating boom side, and described
First doped region does not diffuse to the lower section of the floating boom, so that first doped region and the floating boom do not have overlapping region.
Preferably, the substrate is the substrate of p-type.
The present invention also provides a kind of flash array, the flash array includes multiple flash cells.
Preferably, in the flash array, the source electrode with all flash cells in a line is connected with each other, same row
In the drain electrodes of all flash cells be connected on same bit line.
Preferably, there are two the storage organizations for the flash cell tool；And the flash cell further includes an erasing
Grid, the erasing grid are located between two storage organizations, also, with the erasing grid of all flash cells in a line
It is connected with each other.
Preferably, the flash cell tool there are two the storage organization, along column direction arrange by two storage organizations
Cloth, and in multiple flash cells in a line, multiple storage organizations are arranged in two rows；Wherein, with the institute in a line
There are the wordline grid of the storage organization to be connected with each other, the control gate with all storage organizations in a line is connected with each other.
The present invention also provides a kind of programmed methods of the flash array, including：
Selection needs the storage organization programmed, applies the first program voltage in corresponding drain electrode, in corresponding wordline grid
The second program voltage of upper application applies third program voltage, corresponding source electrode and corresponding erasing grid on corresponding control gate
Ground connection；Wherein,
First program voltage is less than second program voltage；
Second program voltage is less than the third program voltage.
Preferably, ranging from 2V~6V of first program voltage.
Preferably, ranging from 3V~7V of second program voltage.
Preferably, ranging from 10V~14V of the third program voltage.
The present invention also provides a kind of method for deleting of the flash array, including：
Apply the first erasing voltage on the erasing grid of each flash cell, the control gate of each storage organization
The second erasing voltage of upper application, source electrode, drain electrode and the wordline grid of each storage organization are grounded；Wherein,
First erasing voltage is positive voltage, and second erasing voltage is negative voltage.
Preferably, ranging from 6V~10V of first erasing voltage.
Preferably, ranging from -9.5V~-5.5V of second erasing voltage.
The present invention also provides a kind of read methods of the flash array, including：
Selection needs the storage organization read, applies first in corresponding drain electrode and reads voltage, in corresponding wordline grid
It is upper to apply the second reading voltage, apply third reading voltage, corresponding source electrode and corresponding erasing grid on corresponding control gate
Ground connection；Wherein,
Described first, which reads voltage, is less than the second reading voltage；
Described second, which reads voltage, is less than third reading voltage.
Preferably, ranging from 0.6V~1V of the first reading voltage.
Preferably, ranging from 2V~3V of the second reading voltage.
Preferably, the third reads ranging from 5V~7V of voltage.
A kind of flash cell, flash memory permutation and its operating method provided by the present invention, tunnel through field-effect transistor
(TFET) it is applied in flash memories, the conducting of raceway groove and the programming of flash cell is realized using band-to-band-tunneling principle, to
Further decreasing to the inhibition of the punchthrough effect of short channel, the raising of programming efficiency and overall power is realized, and
And flash cell provided by the present invention is easier to realize the diminution of size, the reduction to the memory space of flash memories from now on
And the promotion of memory capacity has impetus.
Description of the drawings
Fig. 1 is a kind of schematic diagram of flash cell in one embodiment of the invention；
Fig. 2 is the schematic diagram of another flash cell in one embodiment of the invention；
Fig. 3 is the band structure schematic diagram of the n-TFET in one embodiment of the invention programming process；
Fig. 4 is the schematic top plan view of flash array in one embodiment of the invention.
Specific implementation mode
The programming operation of existing flash memories as stated in the background art is to utilize raceway groove or conventional source heat mostly
Electron injection is programmed, and is faced with and how to be inhibited the punchthrough effect of short channel, how to improve programming efficiency and how to reduce
The problems such as power consumption.
Present invention proposition tunnels through field-effect transistor (Tunneling Field-Effect Transistor, TFET)
Applied in flash memories, to solve the above problems.
Below in conjunction with the drawings and specific embodiments to a kind of flash cell proposed by the present invention, flash array and operating method
It is described in further detail.According to following explanation, advantages and features of the invention will become apparent from.It should be noted that attached drawing is adopted
Use with very simplified form and non-accurate ratio, only to it is convenient, lucidly aid in illustrating the embodiment of the present invention
Purpose.
Fig. 1 is a kind of schematic diagram of flash cell in one embodiment of the invention, refering to what is shown in Fig. 1, the flash cell packet
It includes：Substrate 100 is formed with the first doped region 101 of N-type and the second doped region 102 of p-type in the substrate 100；
Position 200 is stored, is formed on the substrate 100, and is located at first doped region 101 and second doped region
Region between 102, the storage position 200 include that a floating boom 201 and a control gate 202, the floating boom 201 are formed in the lining
On bottom 100, the control gate 202 is located at the top of the floating boom 201；
Wherein, the storage position 200 and the first doped region 101 and second doping positioned at storage 200 both sides of position
Area 102 is provided commonly for constituting the storage organization of flash cell, and first doped region 101 is used to constitute the leakage of the storage organization
Area, second doped region 102 are used to constitute the source region of the storage organization.
Specifically, the substrate for example can be silicon substrate, the floating boom 201 and control gate 202 for example may be used more
Crystal silicon material, those skilled in the art can voluntarily select as needed, and this is not restricted by the present invention.
It should be noted that tunneling effect transistor is different from traditional MOSFET, conventional MOS FET is to utilize additional grid
Pressure is so that the channel region of device is transformed into anti-type state by spent condition, and then the charge inducing by accumulating forms conducting source and drain
Conducting channel.And TFET is so that the channel region band structure of device is bent using additional grid voltage, and then the electric carrier of source region
Enter raceway groove in a manner of band-to-band-tunneling (Band to Band tunneling), to realize the conducting of source and drain.
Therefore, the source region of TFET and the doping way in drain region are also different from MOSFET, and the source region of TFET and drain region requirement are
Two different doping types, such as the source region of N-type TFET is P-doped zone, drain region is N-doped zone, and the ditch of TFET
The conduction type in road is the carrier type for depending on occurring tunneling effect, rather than depending on the anti-type state of channel region, therefore right
There is no directly requirements for the doping type of its substrate, but in order to enable the additional grid voltage of grid can effectively change channel region
The band structure of substrate, therefore such as intrinsic silicon, the N-type silicon being lightly doped or the P-type silicon being lightly doped usually can be used and (adulterate dense
Doping concentration of the degree much smaller than source region and drain region) etc., wherein be lightly doped refer to semiconductor fermi level close to intrinsic Fermi's energy
The semiconductor of grade.
As a preferred option, the substrate is the substrate of p-type.In the present embodiment, in first doped region 101 for example
Then it is p-type in corresponding second doped region 102 for N-type, in turn, the substrate 100 is preferably the P-type silicon lining being lightly doped
Bottom, due to the drain region of first doped region 101 composition TFET, the source region of the composition of the second doped region 102 TFET, therefore source region
Electron tunneling to channel region and reach drain region, therefore TFET used by the present embodiment flash cell shown in FIG. 1 is substantially N
Type TFET (n-TFET).In addition, being directed to flash cell shown in FIG. 1, also may be selected to form N traps in the substrate, and described
First doped region and second doped region are formed in the scheme in the N traps.Specifically, the N traps are the N-type silicon being lightly doped
(doping concentration is much smaller than the doping concentration of source region and drain region).The N traps leading as raceway groove with aforementioned p-type substrate as raceway groove
Logical principle is identical, and so it will not be repeated.That is, the channel region of TFET is not limited to the p-type or N being lightly doped in the present embodiment
The intrinsic material of type semi-conducting material or such as intrinsic silicon, those skilled in the art is can be according to different need
Select suitable doping type.
As a preferred option, Fig. 2 is the schematic diagram of another flash cell in one embodiment of the invention, with reference to 1 institute of figure
Show, there are two the symmetrical storage positions 31/32 for the flash cell tool；Wherein, there are two described for setting in the substrate
One doped region 21/22 and second doped region 23, two first doped regions 21/22 are arranged in described second
The both sides of doped region 23；And two storage positions 31/32 are respectively formed at 23 both sides of the second doped region, and be located at
Between second doped region 23 and first doped region 21/22.
Specifically, refering to what is shown in Fig. 2, in Fig. 2 the substrate of flash cell, the first doped region and the second doped region doping class
Type can be referred to directly and using the above-mentioned flash cell for including a storage position, i.e., in the present embodiment, sudden strain of a muscle shown in Fig. 2
The substrate 1 of memory cell for example may be the P-type silicon substrate being lightly doped, and the first doped region 21/22 is, for example, N-type, then accordingly
Second doped region 23 is p-type.
In the present embodiment, between the first doped region 21 and the second doped region 23, the storage position 31 is wrapped for storage position 31
Floating boom 311 and control gate 312 are included；Position 32 is stored between the first doped region 22 and the second doped region 23, the storage position
32 include floating boom 321 and control gate 322.It can be seen that two storage positions 31/32 respectively using the first doped region 21/22 as drain region,
And shared the second doped region 21 and be used as source region, two storage organizations of certain lap are formd, and then formed in this way
Flash cell space can be saved, compared to the flash cell of a storage organization is only included to play raising storage density
And the effect of memory capacity.
As a preferred option, the flash cell further includes an erasing grid 4, is formed in the upper of second doped region 23
Side, and between two storage positions 31/32；The storage position 31/32 respectively further comprises a formation over the substrate
Wordline grid 313/323, the wordline grid 313/323 are located at the floating boom 311/321 and the control gate 312/322 far from institute
State the side of erasing grid 4；The floating boom 311/321 and the control gate 312/322 are close to the side of the wordline grid 313/323
On the wall and bottom of wordline grid 313/323 is formed with wordline gate dielectric layer 301.
Specifically, with continued reference to shown in Fig. 2, in the present embodiment, the erasing grid 4 are formed in second doped region 23
Top, and between two storage positions 31/32.The erasing grid 4 are for realizing the erasing to two storage positions 31/32
Operation, details will be described in detail later, it can be seen that two storage positions 31/32 of flash cell in the present embodiment
The same erasing grid 4 have also been shared, and then can also play section space-efficient effect.Apply respectively in the wordline grid 313/323
Voltage is to realize that the state of conducting with the cut-off of the raceway groove of the TFET to two storage positions controls, the floating boom 311/321 and institute
Control gate 312/322 is stated on the side wall close to the wordline grid 313/323 and the bottom of wordline grid 313/323 is formed with word
Wiregrating dielectric layer 301 is to play the role of isolation word line grid and substrate and control gate floating boom.
As a preferred option, the control gate 312/322 is formed with erasing grid on the side wall close to the erasing grid 4
Side wall 304.
Specifically, the control gate 312/322 is formed with erasing grid side wall 304 on the side wall close to the erasing grid 4,
To realize being dielectrically separated between control gate 312/322 and erasing grid 4, control gate 312/322 and erasing grid 4 when preventing erasing
Between puncture.The erasing grid side wall 304 is, for example, silicon oxide layer, further, the floating boom 311/321 and the wiping
Except an erasing gate oxide 305 is also formed between grid 4, the erasing gate oxide 305 is extended to form in the erasing grid side
Between wall 304 and the erasing grid 4.The erasing gate oxide 305 is in subsequent erase process, as tunnel oxide,
Electronics on floating boom 311/321 will be travelling through the erasing gate oxide 305 to reach on erasing grid 4, to realize storage organization
Erase process and the control gate 312/322 on be also formed with top layer dielectric layer 306.It is understood that the erasing
Grid side wall 304, erasing gate oxide 305 and top layer dielectric layer 306 can be, for example, silicon oxide layer, and the present embodiment and Fig. 2
In only for the purposes of distinguish carried out schematical division, during being actually formed, those skilled in the art can be as needed
Voluntarily determine specific forming method and formation sequence etc..
As a preferred option, first doped region 21/22 is located at the wordline grid 313/323 far from the floating boom
In the substrate of 311/321 side, and first doped region does not diffuse to the lower section of the floating boom, so that first doping
Area 21/22 and the floating boom 311/321 do not have overlapping region.
Specifically, with continued reference to shown in Fig. 2, in the present embodiment, such as the first doped region 21 is located at wordline grid 313 far from institute
In the substrate for stating 311 side of floating boom, and first doped region 21 does not diffuse to the lower section of the floating boom 311, so that described
First doped region 21 and the floating boom 311 do not have overlapping region.It is using the reason of this structure, FGS floating gate structure is being wiped
Afterwards, potential accordingly increases, and then generates induction field in channel region-source region (can be considered pn-junction in the present embodiment) so that
The electric current of drain-source changes, that is, leads to the exception of leakage current, and then can cause to judge the storage state of flash cell
The problem of Shi Fasheng is misread.Using the structure provided in the present embodiment, drain region and raceway groove are distinguished, to be effectively prevented from
The erasing floating gate of influence due to to(for) leakage current, so as to ensure accuracy that storage state judges.
In addition, understandable be, a bit line 211/221 can be connected separately on first doped region 21/22, with
Convenient for subsequently realizing the interconnection and control of the first doped region.Between the floating boom 311/321 and substrate 1, the erasing grid 4 with lining
A dielectric layer 302 is each formed between bottom 1, the dielectric layer 302 extends from 311/312 lower section of floating boom is connected to the erasing grid
4 lower section, and then an interface potential barrier area is formed between floating boom 311/321 and substrate 1, so that the electronics of channel region only has
It can just be passed through in programming and inject floating boom 311/321.And also there is a folder between floating boom 311/321 and control gate 312/322
Layer dielectric layer 303, the interlayer dielectric layer 303, such as can be the silicon oxide layer, silicon nitride layer and silicon oxide layer stacked gradually
Multilayered structure, as ONO structure.
In order to become apparent from, more specifically the embodiment present invention is using advantage possessed by TFET, below for tunneling field-effect
The structure and working principle of transistor is explained in detail.
Fig. 3 is the band structure schematic diagram of the n-TFET in one embodiment of the invention programming process, with reference to figure 1 and Fig. 3 institutes
Show, the raceway groove conducting principle of TFET is different from MOSFET, and the n-TFET in figure is being turned off using the P-type channel being lightly doped
Under state, i.e., in the case of not applying grid voltage, the valence-band electrons positioned at n-TFET source regions can not pass through forbidden band；And program shape
Under state, i.e., in the case where grid (corresponding control gate in flash cell) applies grid voltage, the band structure of channel region by
Energy band integrally bending to the influence of grid voltage, channel region pulls down, and then in channel region and source region intersection, channel region is led
It is less than the top of valence band of source region the bottom of with, and the width of potential barrier is reduced, after reaching a certain level, band-to-band-tunneling (Band to Band
Tunneling generation) just becomes possibility so that in the valence-band electrons tunnelling to the conduction band of channel region of source region.And outside
After adding source-drain voltage, the knee of energy band will produce prodigious voltage drop, and then will produce very strong transverse electric field so that into
The electronics for entering channel region accelerates and generates thermoelectron thermoelectron and enter under the action of control gate electric field in floating boom, is dodged to realize
The programming of memory cell.
In view of the background that the size of device now constantly reduces, MOSFET is easy to source caused by short-channel effect occurs
Break-through is leaked, and then generates prodigious source-drain current, influences the normal use of the function of MOSFET element.In contrast, TFET devices
When part is off state, barrier width is larger at tunnel junctions, and tunnelling is difficult to happen, and, it only exists between source and drain and reversely lets out
Reveal electric current, and Leakage Current very little, is, for example, less than 1015A/μm.In turn, be based on TFET has preferable suppression to Punchthrough effect
Effect processed, reducing the flash cell size based on TEFT devices also becomes to be more easy to realize.
In addition, to based on TFET flash memories program when, along the maximum lateral electric field of channel direction be located at source region with
Raceway groove intersection, electronics will be accelerated in source region and raceway groove intersection after source electrode is injected into raceway groove and generate thermoelectron
To obtain the energy being enough across dielectric layer 302, therefore electron injection floating boom is more efficient, realizes source thermoelectron volume
Journey, programming efficiency is promoted, and shortens programming time, to reduce overall power.
Based on above-mentioned flash cell, a kind of flash array is additionally provided in the present embodiment, the flash array includes more
A above-mentioned flash cell.Fig. 4 is the schematic top plan view of flash array in one embodiment of the invention, in order to it is apparent fully
Show the arrangement mode of flash array, the flash array that 3 rows 8 arrange is shown schematically in Fig. 4, and (3 rows have referred to that 3 rows are wiped
Grid), i.e., in the present embodiment, the flash array includes that 3 rows and 8 row amount to 24 flash cells, wherein in a line
The source electrode of all flash cells is connected with each other, and the drain electrode of all flash cells in same row is connected to same position
On line.
As a preferred option, the flash cell employed in the flash array all has two storage organizations,
Two storage organizations are arranged along column direction, and in multiple flash cells in a line, multiple storage organizations
It arranges in two rows；Wherein, it is connected with each other with the wordline grid of all storage organizations in a line, with all described in a line
The control gate of storage organization is connected with each other.The flash cell further includes an erasing grid, the erasing grid be located at two described in deposit
Between storage structure, also, it is connected with each other with the erasing grid of all flash cells in a line.
Specifically, refering to what is shown in Fig. 4, for the ease of understand and it is corresponding with the structure of flash cell, to the first row in Fig. 4
Shown in each structure of flash cell marked.It should be noted that combining the structure of flash cell it is found that the first doping
Area and the second doped region are located in substrate, wherein the first doped region is intended to the first doping with the flash cell of same row
Area is connected with each other, it is necessary to the second doped region is crossed over, therefore in the present embodiment, the first doped region is connected into a bit line 211/221, is led to
It crosses the bit line 211/221 and connecting line is raised to position at the top of higher than flash cell, to realize the interconnection in drain region；Phase
Than under, the second doped region only needs to be connected with the second doped region of other flash cells of same a line, therefore can be adulterated to second
Area carries out extending the interconnection for connecting and can realizing source region on substrate, also, is mixed in view of erasing grid can cover described second
Miscellaneous area, therefore right side shown in Fig. 4, extend a distance so that being partially exposed at for the second doped region is outer, and then passes through this
Realize that electrode is drawn in region；In addition, the control gate, wordline grid and erasing grid in the present embodiment have also been all made of and the second doped region
Identical connection type, the i.e. extension by control gate, wordline grid and erasing grid on same line direction, are directly realized by same a line
Flash cell interconnection.
And the operating method of the flash array is additionally provided in the present embodiment, specifically, the behaviour of the flash array
Include programmed method, method for deleting and read method as method.It will be appreciated by persons skilled in the art that institute in the present embodiment
There are two storage positions for the flash cell of offer, therefore when carrying out such as programming and read operation, being can be with each storage
What position carried out, and not two storage positions of each flash cell can only be operated simultaneously.Below in conjunction with specific embodiment
It elaborates to the operating method of flash array provided by the present invention.
First, a kind of method programmed to the flash array is provided in the present embodiment, including：Selection needs program
Storage organization applies the first program voltage in corresponding drain electrode, applies the second program voltage on corresponding wordline grid, right
Apply third program voltage, corresponding source electrode and corresponding erasing grid ground connection on the control gate answered；Wherein, the first programming electricity
Pressure is less than second program voltage；Second program voltage is less than the third program voltage.
As a preferred option, with reference to flash array shown in Fig. 4, wherein the storage knot marked out by dashed circle frame
Structure A is the selected storage organization for needing to program, and applies the first program voltage, first programming in its corresponding drain electrode
The range of voltage is, for example, 4V between 6V, in the present embodiment in 2V；Apply the second program voltage on its corresponding wordline grid,
The range of second program voltage is, for example, 5V between 7V, in the present embodiment in 3V；Apply in its corresponding control gate grid
Third program voltage, the range of the third program voltage is in 10V to being, for example, 12V between 14V, in the present embodiment；And it will
The source electrode of all storage organizations and erasing grid ground connection, drain electrode, wordline grid and the control gate of every other storage organization are grounded.
It should be noted that in the present embodiment, since the erasing grid with the storage organization of a line in flash array are connected to
, source electrode is connected to, wordline grid are connected to and control gate is connected to, therefore given tacit consent to and existed with selected storage organization
With the voltage applied on the erasing grid of other storage organizations in a line, source electrode, wordline grid and control gate and selected storage
Structure is consistent；Likewise, be connected to due to the drain electrode of the storage organization of same row in flash array, thus with it is selected
Other storage organizations of the storage organization in same row, the voltage applied in drain electrode and selected storage organization are consistent
's.
In turn, pass through above operating method so that only band-to-band-tunneling occurs for TFET structures in selected storage organization
And be connected, and electronics is injected to floating boom by way of thermoelectron injection, and then reach what flash array selectively programmed
Purpose.At the same time, in the not selected storage organization of other in flash array no applied voltage wordline grid, control gate and source
Drain electrode is grounded, and the purpose is to make other unchecked storage organization shutdowns.
Secondly, a kind of method wiped the flash array is provided in the present embodiment, including：In each flash memory
Apply the first erasing voltage on the erasing grid of unit, applies the second erasing voltage on the control gate of each storage organization, often
Source electrode, drain electrode and the wordline grid of a storage organization are grounded；Wherein, first erasing voltage is positive voltage, described the
Two erasing voltages are negative voltage.
As a preferred option, with reference to flash array shown in Fig. 4, wherein the storage knot marked out by dashed circle frame
A line where structure A is the flash cell of selected a line for needing to wipe, and is applied on the erasing grid of the flash cell
First erasing voltage, first erasing voltage are positive voltage, are, for example, 8V in the present embodiment in the range of 6V to 10V；At it
Apply the second erasing voltage on the corresponding control gate of flash cell at place, second erasing voltage is negative voltage, range
Be -9.5V to -5.5V, in the present embodiment it is, for example, -7.5V；And source electrode, wordline grid and the bit line grid of remaining no applied voltage
It is grounded.In the present embodiment, the erasing principle of flash cell is to be based on Fowler-Nordheim tunnellings (referred to as FN tunnellings),
By applying positive voltage on erasing grid, apply negative voltage on the control gate so that the barrier width between floating boom and erasing grid
Narrowing to the electronics accumulated in floating boom can be entered across the potential barrier in erasing grid in the way of FN tunnellings, and then be completed
The erasing of a line flash cell.
Finally, a kind of method read to the flash array is additionally provided in the present embodiment, including：Selection needs to read
Storage organization, in corresponding drain electrode apply first read voltage, on corresponding wordline grid apply second read voltage,
Apply third on corresponding control gate and reads voltage, corresponding source electrode and corresponding erasing grid ground connection；Wherein, it described first reads
Voltage is less than described second and reads voltage；Described second, which reads voltage, is less than third reading voltage.
As a preferred option, with reference to flash array shown in Fig. 4, wherein the storage knot marked out by dashed circle frame
Structure A is the selected storage organization for needing to read, wherein the storage organization marked out by dotted line frame is selected needs
The storage organization of reading applies first in the drain electrode for the storage organization for needing to read and reads voltage, and described first reads voltage
Range between 0.6V~1V, in the present embodiment be, for example, 0.8V；Apply on the wordline grid for needing the storage organization read
Second reads voltage, and described second reads the range of voltage between 2V~3V, is, for example, 2.5V in the present embodiment；It to read
Storage organization control gate on apply third and read voltage, the third reads the range of voltage between 5V~7V, this reality
Apply in example is, for example, 6V；And source electrode and the erasing grid ground connection of the selected storage organization for needing to read, and its in flash array
The erasing grid, source electrode, wordline grid and control gate of its not selected storage organization are grounded, other in flash array not to be selected
The drain electrode of storage organization be grounded.In the present embodiment, the reading principle of flash cell is, applies in control gate smaller just
After bias (the bias size will not cause to carry out accidentally programming to flash memory structure), the electronics that is stored on floating boom number can influence coupling
Close the potential on floating boom, for example, when there are voltages when electronics, applied on the control gate on floating boom will be by the electricity on floating boom
Son absorbs, and then the influence to raceway groove is smaller, has also just influenced the electric current of drain terminal reading, therefore big according to the electric current that drain terminal is read
It is small, it will be able to reflect on floating boom store electronics number, and realize by judgement the differentiation of two kinds of storage states, and then can be real
The read functions of existing storage structure.
In conclusion a kind of flash cell provided by the present invention, flash memory permutation and its operating method, tunnel through field-effect
Transistor (TFET) is applied in flash memories, and the conducting of raceway groove and the volume of flash cell are realized using band-to-band-tunneling principle
Journey, to realize to the further of the inhibition of the punchthrough effect of short channel, the raising of programming efficiency and overall power
It reduces, and flash cell provided by the present invention is easier to realize the diminution of size, it is empty to the storage of flash memories from now on
Between reduction and memory capacity promotion have impetus.
Obviously, those skilled in the art can carry out invention spirit of the various modification and variations without departing from the present invention
And range.If in this way, these modification and variations of the present invention belong to the claims in the present invention and its equivalent technologies range it
Interior, then the present invention is also intended to including these changes and changing.
Claims (21)
1. a kind of flash cell, which is characterized in that including：
Substrate is formed with the first doped region of N-type and the second doped region of p-type in the substrate；
Position is stored, is formed over the substrate, and the region between first doped region and second doped region, institute
It includes a floating boom and a control gate to state storage position, and the floating boom is formed over the substrate, and the control gate is located at the floating boom
Top；
Wherein, described to store position and be provided commonly for constituting positioned at first doped region for storing position both sides and the second doped region
The storage organization of flash cell, first doped region are used to constitute the drain region of the storage organization, and second doped region is used
In the source region for constituting the storage organization.
2. flash cell as described in claim 1, which is characterized in that there are two the storage positions for the flash cell tool；Its
In, there are two first doped region and second doped region, two first doped regions for setting in the substrate
It is arranged in the both sides of second doped region；And two storage positions are respectively formed at the second doped region both sides, and
It is located between second doped region and first doped region.
3. flash cell as claimed in claim 2, which is characterized in that further include an erasing grid, be formed in second doping
The top in area, and between two storage positions；The storage position respectively further comprises the word of a formation over the substrate
Wiregrating, the wordline grid are located at the side of the control gate and the floating boom far from the erasing grid；The floating boom and the control
Grid processed are on the side wall close to the wordline grid and the bottom of wordline grid is formed with wordline gate dielectric layer.
4. flash cell as described in claim 1, which is characterized in that the control gate is on the side wall close to the erasing grid
It is formed with erasing grid side wall.
5. flash cell as described in claim 1, which is characterized in that first doped region is located at the wordline grid far from institute
In the substrate for stating floating boom side, and first doped region does not diffuse to the lower section of the floating boom, so that first doping
Area and the floating boom do not have overlapping region.
6. flash cell as described in claim 1, which is characterized in that the substrate is the substrate of p-type.
7. a kind of flash array, which is characterized in that the flash array includes multiple as described in any one of claim 1-6
Flash cell.
8. flash array as claimed in claim 7, which is characterized in that in the flash array, with all described in a line
The source electrode of flash cell is connected with each other, and the drain electrode of all flash cells in same row is connected on same bit line.
9. flash array as claimed in claim 7, which is characterized in that there are two the storage organizations for the flash cell tool；
And the flash cell further includes an erasing grid, the erasing grid are located between two storage organizations, also, same
The erasing grid of all flash cells in row are connected with each other.
10. flash array as claimed in claim 7, which is characterized in that the flash cell has there are two the storage organization,
Two storage organizations are arranged along column direction, and in multiple flash cells in a line, multiple storage organizations
It arranges in two rows；Wherein, it is connected with each other with the wordline grid of all storage organizations in a line, with all described in a line
The control gate of storage organization is connected with each other.
11. a kind of programmed method of flash array as described in any one of claim 7-10, which is characterized in that including：
Selection needs the storage organization programmed, applies the first program voltage in corresponding drain electrode, is applied on corresponding wordline grid
Add the second program voltage, applies third program voltage, corresponding source electrode and corresponding erasing grid ground connection on corresponding control gate；
Wherein,
First program voltage is less than second program voltage；
Second program voltage is less than the third program voltage.
12. the programmed method of flash array according to claim 11, which is characterized in that the model of first program voltage
It encloses for 2V~6V.
13. the programmed method of flash array according to claim 11, which is characterized in that the model of second program voltage
It encloses for 3V~7V.
14. the programmed method of flash array according to claim 11, which is characterized in that the model of the third program voltage
It encloses for 10V~14V.
15. a kind of method for deleting of flash array as described in any one of claim 7-10, which is characterized in that including：
Apply the first erasing voltage on the erasing grid of each flash cell, is applied on the control gate of each storage organization
Add the second erasing voltage, source electrode, drain electrode and the wordline grid of each storage organization are grounded；Wherein,
First erasing voltage is positive voltage, and second erasing voltage is negative voltage.
16. the method for deleting of flash array according to claim 15, which is characterized in that the model of first erasing voltage
It encloses for 6V~10V.
17. the method for deleting of flash array according to claim 15, which is characterized in that the model of second erasing voltage
It encloses for -9.5V~-5.5V.
18. a kind of read method of flash array as described in any one of claim 7-10, which is characterized in that including：
Selection needs the storage organization read, applies first in corresponding drain electrode and reads voltage, is applied on corresponding wordline grid
Add the second reading voltage, applies third on corresponding control gate and read voltage, corresponding source electrode and corresponding erasing grid ground connection；
Wherein,
Described first, which reads voltage, is less than the second reading voltage；
Described second, which reads voltage, is less than third reading voltage.
19. the read method of flash array according to claim 18, which is characterized in that described first reads the model of voltage
It encloses for 0.6V~1V.
20. the read method of flash array according to claim 18, which is characterized in that described second reads the model of voltage
It encloses for 2V~3V.
21. the read method of flash array according to claim 18, which is characterized in that the third reads the model of voltage
It encloses for 5V~7V.
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| CN109712981A (en) * | 2019-01-02 | 2019-05-03 | 上海华虹宏力半导体制造有限公司 | Memory and forming method thereof |
| WO2023165283A1 (en) * | 2022-03-03 | 2023-09-07 | 华为技术有限公司 | Memory and electronic device |
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Application publication date: 20180817 |