CN116759500A - Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode - Google Patents
Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode Download PDFInfo
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910021389 graphene Inorganic materials 0.000 claims abstract description 42
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- 238000005240 physical vapour deposition Methods 0.000 claims description 14
- 235000012431 wafers Nutrition 0.000 description 47
- 229910002601 GaN Inorganic materials 0.000 description 22
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- 238000012360 testing method Methods 0.000 description 9
- 229910002704 AlGaN Inorganic materials 0.000 description 8
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
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Abstract
The invention relates to a light-emitting diode epitaxial wafer and a preparation method thereof, and a light-emitting diode, wherein the epitaxial wafer comprises an epitaxial wafer, a substrate and an epitaxial wafer laminated on the substrate, the epitaxial wafer comprises an electron blocking layer and a P-type layer which are laminated in turn along the epitaxial direction, and an insertion layer is arranged between the electron blocking layer and the P-type layer; the insertion layer comprises a first hole acceleration layer, an intermediate buffer layer and a second hole acceleration layer which are sequentially laminated along the epitaxial direction; the first hole acceleration layer is a superlattice structure formed by periodically and alternately growing a first MgN sub-layer and an AlInGaN sub-layer, the middle buffer layer is a graphene layer, and the second hole acceleration layer is a superlattice structure formed by periodically and alternately growing a second MgN sub-layer and an InGaN sub-layer. The invention can effectively improve the luminous efficiency of the light-emitting diode, increase the surface evenness of the epitaxial wafer and improve the antistatic capability.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode.
Background
In the prior art, the structure of the gallium nitride-based light-emitting diode epitaxial wafer is generally that a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multiple quantum well layer, an electron blocking layer and a P-type semiconductor layer are sequentially laminated on a substrate, on one hand, the activation rate of Mg in the existing P-type semiconductor layer is very low, the mobility of holes is low, and certain blocking is caused to the holes due to the fact that the holes in the multiple quantum well layer are insufficient due to the fact that the barrier height of the electron blocking layer is higher; on the other hand, the accumulated defects from the bottom layer extend to the P-type semiconductor layer, so that part of holes can be captured, the holes are consumed, the hole concentration is affected, the luminous efficiency is also affected, the surface flatness of the epitaxy is also affected, and the defects also become leakage channels, so that the antistatic capability of the light-emitting diode is reduced.
Disclosure of Invention
The invention aims at providing a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode aiming at the existing technical situation, and the invention can greatly increase the hole concentration entering a multi-quantum well layer, reduce the blocking effect of an electron blocking layer on holes in the traditional structure, promote the growth quality of a P-type layer, reduce the consumption of defects on the holes, thereby effectively improving the light-emitting efficiency of the light-emitting diode, and improving the surface flatness of the epitaxial wafer and the antistatic capability through the arrangement of an insertion layer.
In order to achieve the above purpose, the invention adopts the following technical scheme:
in one aspect, the invention provides a light-emitting diode epitaxial wafer, which comprises a substrate and an epitaxial wafer laminated on the substrate, wherein the epitaxial wafer comprises an electron blocking layer and a P-type layer which are laminated in turn along an epitaxial direction, and an insertion layer is arranged between the electron blocking layer and the P-type layer;
the insertion layer comprises a first hole acceleration layer, an intermediate buffer layer and a second hole acceleration layer which are sequentially laminated along the epitaxial direction;
the first hole acceleration layer is a superlattice structure formed by periodically and alternately growing a first MgN sub-layer and an AlInGaN sub-layer, the middle buffer layer is a graphene layer, and the second hole acceleration layer is a superlattice structure formed by periodically and alternately growing a second MgN sub-layer and an InGaN sub-layer.
In some embodiments, the Al content In the AlInGaN sub-layer decreases with increasing number of periods of the first hole acceleration layer, and the In content increases with increasing number of periods of the first hole acceleration layer.
In some embodiments, the Al content in the AlInGaN sub-layer decreases from a to b as the number of periods of the first hole acceleration layer increases, where 0.1. Ltoreq.a.ltoreq.0.4, and 0.01. Ltoreq.b.ltoreq.0.05.
In some embodiments, in content In the AlInGaN sub-layer increases from c to d with increasing number of periods of the first hole acceleration layer, where 0 < c < 0.05,0.05.ltoreq.d.ltoreq.0.1.
In some embodiments, the In content In the InGaN sublayer is 0.05-0.1.
In some embodiments, in the first hole acceleration layer, a thickness of a single first MgN sub-layer is 0.1nm to 5nm, and a thickness of a single AlInGaN sub-layer is 0.1nm to 5nm; in the second hole acceleration layer, the thickness of a single second MgN sub-layer is 0.1 nm-5 nm, and the thickness of a single InGaN sub-layer is 0.1 nm-5 nm.
In some embodiments, the first hole acceleration layer has a cycle number of 1 to 5 and a growth temperature of 800 ℃ to 1000 ℃; the number of cycles of the second hole acceleration layer is 1-5, and the growth temperature is 800-1000 ℃.
In some embodiments, the thickness of the graphene layer is 1 nm-10 nm, and the graphene layer is prepared by physical vapor deposition.
In another aspect, the present invention provides a method for preparing an epitaxial wafer of a light emitting diode, including:
providing a substrate;
depositing an epitaxial layer on the substrate;
the epitaxial wafer comprises an electron blocking layer and a P-type layer which are sequentially laminated along the epitaxial direction, and an inserting layer is arranged between the electron blocking layer and the P-type layer;
the insertion layer comprises a first hole acceleration layer, an intermediate buffer layer and a second hole acceleration layer which are sequentially laminated along the epitaxial direction;
the first hole acceleration layer is a superlattice structure formed by periodically and alternately growing a first MgN sub-layer and an AlInGaN sub-layer, the middle buffer layer is a graphene layer, and the second hole acceleration layer is a superlattice structure formed by periodically and alternately growing a second MgN sub-layer and an InGaN sub-layer.
Furthermore, the invention provides a light-emitting diode, comprising the light-emitting diode epitaxial wafer.
The invention has the beneficial effects that:
in the invention, an insertion layer is arranged between an electron blocking layer and a P-type layer, wherein the insertion layer is provided with a second hole accelerating layer at one side close to the P-type layer, the second hole accelerating layer is in a superlattice structure formed by periodically and alternately growing a second MgN sub-layer and an InGaN sub-layer, and the heterogeneous superlattice structure of the second MgN sub-layer and the InGaN sub-layer can generate a great polarized electric field so as to generate two-dimensional hole gas and contribute to the mobility improvement of carriers, so that holes generated by the P-type layer are improved in mobility and expansion capacity under the action of the second hole accelerating layer; meanwhile, holes are generated In the second MgN sub-layer, and In the InGaN sub-layer can reduce the activation energy of Mg and further increase the hole concentration.
Secondly, the interposed layer adopts the graphene layer as an intermediate buffer layer between the second hole acceleration layer and the first hole acceleration layer, on one hand, the graphene layer can enable materials to be combined according to van der Waals force, so that the lattice quality is greatly improved, defects which are prolonged from a bottom layer are prevented from extending upwards further, the antistatic capability of the light-emitting diode is improved, and the defects are prevented from accumulating to a P-type layer to capture holes to cause consumption of the holes, so that holes which effectively enter a multi-quantum well layer are increased, and the luminous efficiency is improved; on the other hand, the graphene layer can increase the matching degree between the P-type layer and the electron blocking layer, so that the blocking effect on holes caused by the high potential barrier height of the electron blocking layer is avoided, the mobility of carriers in the graphene layer is higher, and the concentration of holes entering the multi-quantum well layer through the electron blocking layer is also increased.
In addition, the first hole acceleration layer is arranged on one side of the insertion layer close to the electron blocking layer, and is in a superlattice structure formed by periodically and alternately growing the first MgN sub-layer and the AlInGaN sub-layer, so that on one hand, the heterogeneous superlattice structure formed by the first MgN sub-layer and the AlInGaN sub-layer can generate a great polarized electric field, the idle mobility is further improved, and meanwhile, the hole concentration can be further increased through the first MgN sub-layer and the AlInGaN sub-layer; on the other hand, inGaN < AlInGaN < AlGaN in the forbidden band width can increase the potential barrier and lattice matching degree with the electron blocking layer, so that more holes can enter the multiple quantum well layer through the electron blocking layer.
In summary, by arranging the insertion layer, the hole concentration entering the multi-quantum well layer can be greatly increased, the blocking effect of the electron blocking layer on the holes in the traditional structure is reduced, the growth quality of the P-type layer is improved, the consumption of defects on the holes is reduced, the luminous efficiency of the light-emitting diode is effectively improved, the surface flatness of the epitaxial wafer is improved, and the antistatic capability is improved.
Drawings
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to the present invention.
Fig. 2 is a schematic structural view of an interposer of the present invention.
Fig. 3 is a flowchart of a method for manufacturing a light emitting diode epitaxial wafer according to the present invention.
Detailed Description
The present invention will be described in further detail below in order to make the objects, technical solutions and advantages of the present invention more apparent.
On the one hand, referring to fig. 1 to 2, the invention discloses a light-emitting diode epitaxial wafer, which comprises a substrate 1 and an epitaxial wafer laminated on the substrate 1, wherein the epitaxial wafer comprises an electron blocking layer 6 and a P-type layer 8 which are laminated in turn along the epitaxial direction, and an insertion layer 7 is arranged between the electron blocking layer 6 and the P-type layer 8;
the interposer 7 includes a first hole acceleration layer 71, an intermediate buffer layer 72, and a second hole acceleration layer 73 stacked in this order in the epitaxial direction;
the first hole acceleration layer 71 has a superlattice structure in which a first MgN sublayer 711 and an AlInGaN sublayer 712 are periodically grown alternately, the intermediate buffer layer 72 is a graphene layer, and the second hole acceleration layer 73 has a superlattice structure in which a second MgN sublayer 731 and an InGaN sublayer 732 are periodically grown alternately.
In the invention, an insertion layer 7 is arranged between an electron blocking layer 6 and a P-type layer 8, wherein the insertion layer 7 is provided with a second hole acceleration layer 73 at one side close to the P-type layer 8, the second hole acceleration layer 73 is a superlattice structure formed by periodically alternately growing a second MgN sub-layer 731 and an InGaN sub-layer 732, a heterogeneous superlattice structure formed by the second MgN sub-layer 731 and the InGaN sub-layer 732 can generate a very large polarized electric field, so that two-dimensional hole gas is generated, mobility of carriers is promoted, and therefore, holes generated by the P-type layer 8 are promoted under the action of the second hole acceleration layer 73; meanwhile, the second MgN sub-layer 731 may generate holes, and In the InGaN sub-layer 732 may decrease activation energy of Mg, further increasing hole concentration.
Secondly, the interposed layer 7 adopts a graphene layer as the middle buffer layer 72 between the second hole acceleration layer 73 and the first hole acceleration layer 71, on one hand, the graphene layer can enable materials to be combined according to van der Waals force, so that the lattice quality is greatly improved, defects rising from a bottom layer are prevented from further extending upwards, the antistatic capability of the light-emitting diode is improved, defects are prevented from accumulating until the P-type layer 8 captures holes to cause consumption of the holes, holes effectively entering the multi-quantum well layer 5 are increased, and the light-emitting efficiency is improved; on the other hand, the graphene layer can increase the matching degree between the P-type layer 8 and the electron blocking layer 6, so that the blocking effect on holes caused by the high barrier height of the electron blocking layer 6 is avoided, the mobility of carriers in the graphene layer is higher, and the concentration of holes entering the multi-quantum well layer 5 through the electron blocking layer 6 is also increased.
Furthermore, the first hole acceleration layer 71 is disposed on the side of the insertion layer 7 near the electron blocking layer 6, and the first hole acceleration layer 71 is a superlattice structure formed by periodically and alternately growing a first MgN sublayer 711 and an AlInGaN sublayer 712, on one hand, a hetero superlattice structure formed by the first MgN sublayer 711 and the AlInGaN sublayer 712 can generate a very large polarized electric field, so as to further improve the idle mobility, and meanwhile, the hole concentration can be further increased through the first MgN sublayer 711 and the AlInGaN sublayer 712; on the other hand, since InGaN < AlInGaN < AlGaN in the forbidden band width, the potential barrier and lattice matching degree with the electron blocking layer 6 can be increased, so that more holes can enter into the multiple quantum well layer 5 through the electron blocking layer 6.
In summary, by arranging the insertion layer 7, the concentration of holes entering the multi-quantum well layer 5 can be greatly increased, the blocking effect of the electron blocking layer 6 on the holes in the traditional structure is reduced, the growth quality of the P-type layer 8 is improved, the consumption of defects on the holes is reduced, and therefore the luminous efficiency of the light-emitting diode is effectively improved, the surface flatness of the epitaxial wafer is improved, and the antistatic capability is improved.
In the AlInGaN sub-layer 712, the Al content decreases with the number of cycles of the first hole acceleration layer 71, and the In content increases with the number of cycles of the first hole acceleration layer 71.
That is, in the i-th period, the Al content In AlInGaN sub-layer 712 is k, the In content is m, and In the i+1-th period, the Al content In AlInGaN sub-layer 712 is j, the In content is n, k > j, and n > m.
Since InGaN < AlInGaN < AlGaN In the forbidden bandwidth, by the gradual change of Al content and In content of AlInGaN sub-layer 712, the potential barrier of AlInGaN sub-layer 712 gradually changes from low to high In the first hole acceleration layer 71 from P-type layer 8 to the direction of electron blocking layer 6, and the closer AlInGaN sub-layer 712 of electron blocking layer 6 is to the higher the matching degree of the potential barrier and lattice of electron blocking layer 6, the higher the potential barrier of electron blocking layer 6 is to the blocking of holes In the conventional structure is effectively reduced, so that more holes can enter into multiple quantum well layer 5 through electron blocking layer 6.
Wherein the Al content in AlInGaN sub-layer 712 decreases from a to b with increasing number of periods of the first hole acceleration layer 71, wherein 0.1 a 0.4,0.01 b 0.05, and a is exemplified by, but not limited to, 0.1, 0.2, 0.25, 0.3, 0.35, or 0.4, and b is exemplified by, but not limited to, 0.01, 0.02, 0.03, 0.04, or 0.05, and too high Al content tends to cause too high barrier and affect the crystal quality, and too low Al content tends to decrease the degree of matching with the barrier and lattice of the electron blocking layer 6.
Illustratively, the number of periods of the first hole acceleration layer 71 is 2, and in the first period, the Al content of the AlInGaN sub-layer 712 is 0.1, and in the second period, the Al content of the AlInGaN sub-layer 712 is 0.05, but is not limited thereto.
Illustratively, the number of periods of the first hole acceleration layer 71 is 4, and in the first period, the Al content of the AlInGaN sub-layer 712 is 0.4, in the second period, the Al content of the AlInGaN sub-layer 712 is 0.1, in the third period, the Al content of the AlInGaN sub-layer 712 is 0.08, and in the fourth period, the Al content of the AlInGaN sub-layer 712 is 0.01, but is not limited thereto.
Wherein In content In AlInGaN sub-layer 712 increases with the number of cycles of the first hole acceleration layer 71 from c to d, wherein 0 < c < 0.05,0.05 d.ltoreq.0.1, and c is, for example, 0.01, 0.02, 0.028, 0.03, 0.035, 0.04, or 0.049, but not limited thereto, and d is 0.05, 0.06, 0.07, 0.075, 0.08, 0.09, or 0.1, but not limited thereto, too high In content may cause significant degradation of lattice quality, and too low In content may be detrimental to lowering activation energy of Mg.
Illustratively, the number of periods of the first hole acceleration layer 71 is 2, and In content of the AlInGaN sub-layer 712 is 0.049 In the first period, and In content of the AlInGaN sub-layer 712 is 0.1 In the second period, but is not limited thereto.
Illustratively, the number of periods of the first hole acceleration layer 71 is 4, and In content of the AlInGaN sub-layer 712 is 0.01 In the first period, 0.03 In the second period, 0.05 In the third period, and 0.08 In the fourth period, but is not limited thereto.
In the InGaN sublayer 732, the In content is 0.05 to 0.1, and exemplary In contents are 0.05, 0.06, 0.07, 0.08, 0.09, or 0.1, but not limited thereto, too high In content may cause significant degradation of the lattice quality, and too low In content is unfavorable for reducing the activation energy of Mg.
In the first hole acceleration layer 71, the thickness of the single first MgN sub-layer 711 is 0.1nm to 5nm, and the thickness of the single AlInGaN sub-layer 712 is 0.1nm to 5nm; in the second hole acceleration layer 73, the thickness of the single second MgN sub-layer 731 is 0.1nm to 5nm, the thickness of the single InGaN sub-layer 732 is 0.1nm to 5nm, and exemplary, the thickness of the single first MgN sub-layer 711 is 0.1nm, 0.5nm, 2nm, 2.5nm, 3.5nm, 4.5nm, or 5nm, and the thickness of the single AlInGaN sub-layer 712 is 0.1nm, 0.5nm, 0.8nm, 1.2nm, 2.5nm, 3.5nm, 4.8nm, or 5nm, but is not limited thereto; illustratively, the thickness of the single second MgN sub-layer 731 is 0.1nm, 0.5nm, 1nm, 2.8nm, 3nm, 4.8nm, or 5nm, and the thickness of the single InGaN sub-layer 732 is 0.1nm, 0.5nm, 0.8nm, 1.2nm, 2.5nm, 3.5nm, 4.8nm, or 5nm, but is not limited thereto.
The number of cycles of the first hole acceleration layer 71 is 1 to 5, and the growth temperature is 800-1000 ℃; the number of cycles of the second hole acceleration layer 73 is 1 to 5, the growth temperature is 800 ℃ to 1000 ℃, and too high a temperature is unfavorable for In incorporation and too low a temperature is likely to cause a decrease In lattice quality.
More preferably, the number of cycles of the first hole acceleration layer 71 is 2 to 5, and the number of cycles of the second hole acceleration layer 73 is 2 to 5.
The thickness of the graphene layer is 1 nm-10 nm, and the graphene layer is prepared by Physical Vapor Deposition (PVD), and the thickness of the graphene layer is 1nm, 2nm, 5nm, 7nm, 9nm or 10nm, which is exemplary, but not limited thereto, and the thickness of the graphene layer is too small to reduce lattice defects extending upwards from the underlayer.
The preparation steps of the graphene layer are as follows:
firstly, growing 300nm Ni film with electron beam deposited on a substrate by PVD method, wherein the carbon source is CH 4 The growth temperature is 1000 ℃, and the carrier gas is H 2 And Ar, and then transferred onto the first hole acceleration layer 71.
The epitaxial wafer further comprises a nucleation layer 2, an intrinsic GaN layer 3, an N-type layer 4 and a multiple quantum well layer 5 which are sequentially deposited on the substrate 1, and an electron blocking layer 6 is deposited on the multiple quantum well layer 5.
The multiple quantum well layers 5 are of a periodic structure formed by alternately stacking InGaN quantum well layers and GaN quantum barrier layers, and the number of the periods of the multiple quantum well layers 5 is 3-15.
Wherein the electron blocking layer 6 is made of Al y Ga 1-y N material layer and In z Ga 1-z And the periodic structure of the alternate growth of the N material layers is that y is more than or equal to 0.05 and less than or equal to 0.2,0.1 and z is more than or equal to 0.5.
On the other hand, referring to fig. 1 to 3, the invention discloses a preparation method of a light emitting diode epitaxial wafer, which comprises the following steps:
s100, providing a substrate 1;
s200, depositing an epitaxial layer on the substrate 1;
the epitaxial wafer comprises an electron blocking layer 6 and a P-type layer 8 which are sequentially laminated along the epitaxial direction, and an insertion layer 7 is arranged between the electron blocking layer 6 and the P-type layer 8;
the interposer 7 includes a first hole acceleration layer 71, an intermediate buffer layer 72, and a second hole acceleration layer 73 stacked in this order in the epitaxial direction;
the first hole acceleration layer 71 has a superlattice structure in which a first MgN sublayer 711 and an AlInGaN sublayer 712 are periodically grown alternately, the intermediate buffer layer 72 is a graphene layer, and the second hole acceleration layer 73 has a superlattice structure in which a second MgN sublayer 731 and an InGaN sublayer 732 are periodically grown alternately.
Among them, the substrate 1 may be a sapphire substrate, a Si substrate, a SiC substrate, or the like, but is not limited thereto.
The specific steps of depositing the epitaxial layer on the substrate 1 in step S200 are as follows:
s210, depositing a nucleation layer 2 on a substrate 1:
the nucleation layer 2 may be an AlGaN material layer or an AlN material layer, and is exemplified by an AlGaN material layer by MOCVD (metal organic chemical vapor deposition) method, wherein the temperature of the reaction chamber is controlled to be 500-700 ℃, the pressure of the reaction chamber is controlled to be 200-400 torr, and NH is controlled 3 As N source, N 2 And H 2 TMGa is used as a Ga source and TMAL is used as an Al source as a carrier gas.
S220, depositing an intrinsic GaN layer 3 on the nucleation layer 2:
the MOCVD method is adopted, the temperature of the reaction chamber is controlled to be 1100-1150 ℃, the pressure of the reaction chamber is 100-500 torr, and NH is controlled 3 As N source, N 2 And H 2 As carrier gas, TMGa was used as Ga source.
S230, depositing an N-type layer 4 on the intrinsic GaN layer 3:
the MOCVD method is adopted, the temperature of the reaction chamber is controlled to be 1100-1150 ℃, the pressure of the reaction chamber is 100-500 torr, and NH is controlled 3 As N source, N 2 And H 2 TMGa as a Carrier gas, siH as a Ga source 4 As the N-type dopant, an Si-doped N-type GaN layer is grown.
S240, depositing a multi-quantum well layer 5 on the N-type layer 4:
the multi-quantum well layer 5 is a periodic structure formed by alternately stacking InGaN quantum well layers and GaN quantum barrier layers, the number of cycles of the multi-quantum well layer 5 is 3-15, wherein in the growth process of the InGaN quantum well layer, an MOCVD method is adopted, the temperature of a reaction chamber is controlled to be 700-800 ℃, the pressure of the reaction chamber is 100-500 torr, and NH is carried out 3 As N source, N 2 And H 2 The carrier gas is TMGa as Ga source, TMIn as In source, the temperature of the reaction chamber is controlled to be 800-900 ℃ and the pressure of the reaction chamber is controlled to be 100-500 torr In the growth process of the GaN quantum barrier layer, and the In source and N are closed 2 And H 2 As carrier gas, TEGa as Ga source, NH 3 As an N source.
S250, depositing an electron blocking layer 6 on the multiple quantum well layer 5:
the electron blocking layer 6 is made of Al y Ga 1-y N material layer and In z Ga 1-z The periodic structure of alternately growing N material layers, wherein y is more than or equal to 0.05 and less than or equal to 0.2,0.1 and z is more than or equal to 0.5, the MOCVD method is adopted, the temperature of a reaction chamber is controlled to be 900-1000 ℃, the pressure of the reaction chamber is 100-300 torr, and NH is adopted 3 As N source, N 2 And H 2 TMGa as a Ga source, TMAL as an Al source, and TMIn as an In source are used as carrier gases.
S260. depositing an insertion layer 7 on the electron blocking layer 6:
s261 depositing a first hole acceleration layer 71 on the electron blocking layer 6:
specifically, the first MgN sub-layer 711 and AlInGaN sub-layer 712 are alternately grown, the number of periods is 1-5, the first hole acceleration layer 71 can be grown by MOCVD, PVD or Molecular Beam Epitaxy (MBE), for example, the MOCVD method is used, the temperature of the reaction chamber is controlled to 800-1000 ℃, the pressure is 100-500 torr, and the n 2 And H 2 NH as carrier gas 3 CP as N source 2 Mg is used as a Mg source, and a first MgN sub-layer 711 is grown, wherein the thickness of the first MgN sub-layer is 0.1-5 nm; then maintaining the growth temperature and pressure unchanged, continuing to introduce NH 3 /N 2 /H 2 Closing CP 2 Mg, TEGa as Ga source, TMIn as In source, TMAL as Al source, alInGaN sub-layer 712 is grown with a thickness of 0.1nm to 5nm.
S262. depositing an intermediate buffer layer 72 on the first hole acceleration layer 71:
specifically, the intermediate buffer layer 72 is a graphene layer, the graphene layer can be grown by PVD, the growth substrate is a 300nm Ni film deposited by electron beam, and the carbon source is CH 4 The growth temperature is 1000 ℃, and the carrier gas is H 2 And Ar, growing a graphene layer with the thickness of 1-10 nm, and transferring the graphene layer onto the first hole acceleration layer 71.
S263. depositing a second hole acceleration layer 73 on the intermediate buffer layer 72:
specifically, the second MgN sub-layer 731 and the InGaN sub-layer 732 are alternately grown, the number of periods is 1-5, the second hole acceleration layer 73 can be grown by MOCVD, PVD or Molecular Beam Epitaxy (MBE), for example, the temperature of the reaction chamber is controlled to 800-1000 ℃, the pressure is 100-500 torr, and the pressure is n 2 And H 2 As a means ofCarrier gas, NH 3 CP as N source 2 Mg is used as a Mg source, and a second MgN sub-layer 731 is grown, wherein the thickness is 0.1 nm-5 nm; then maintaining the growth temperature and pressure unchanged, continuing to introduce NH 3 /N 2 /H 2 Closing CP 2 Mg, TEGa as Ga source, TMIn as In source, and InGaN sub-layer 732 is grown with a thickness of 0.1nm to 5nm.
In step S261, during the growth of AlInGaN sub-layer 712, the Al and In amounts are adjusted between the periods so that the Al content decreases with the increase of the number of periods of first hole acceleration layer 71 and the In content increases with the increase of the number of periods of first hole acceleration layer 71.
S270. depositing a P-type layer 8 on the interposer 7:
the MOCVD method is adopted, the temperature of the reaction chamber is controlled to be 800-1000 ℃, the pressure of the reaction chamber is 100-300 torr, and NH is controlled 3 As N source, N 2 And H 2 TMGa as carrier gas, CP 2 Mg as P-type dopant with a doping concentration of 5×10 17 cm -3 ~1×10 20 cm -3 A P-type layer 8 is grown, the P-type layer 8 being a Mg doped P-type GaN layer.
Furthermore, the invention discloses a light-emitting diode, which comprises the light-emitting diode epitaxial wafer.
The invention is further illustrated by the following examples in conjunction with the accompanying drawings:
example 1
The invention discloses a light-emitting diode epitaxial wafer, which comprises a substrate and an epitaxial wafer laminated on the substrate, wherein the epitaxial wafer comprises an electron blocking layer and a P-type layer which are laminated in turn along the epitaxial direction, and an inserting layer is arranged between the electron blocking layer and the P-type layer;
the insertion layer comprises a first hole acceleration layer, an intermediate buffer layer and a second hole acceleration layer which are sequentially laminated along the epitaxial direction;
the first hole acceleration layer is a superlattice structure formed by periodically and alternately growing a first MgN sub-layer and an AlInGaN sub-layer, the middle buffer layer is a graphene layer, and the second hole acceleration layer is a superlattice structure formed by periodically and alternately growing a second MgN sub-layer and an InGaN sub-layer.
Wherein, in the AlInGaN sub-layer, the Al content decreases with the increase of the cycle number of the first hole acceleration layer, and the In content increases with the increase of the cycle number of the first hole acceleration layer.
Wherein, the Al content in the AlInGaN sub-layer decreases from 0.2 to 0.03 along with the increase of the cycle number of the first hole acceleration layer.
In the AlInGaN sub-layer, the In content increases from 0.001 to 0.08 with the increase of the cycle number of the first hole acceleration layer.
In the InGaN sub-layer, the In content is 0.08.
In the first hole acceleration layer, the thickness of a single MgN sub-layer is 2nm, and the thickness of a single AlInGaN sub-layer is 3nm; in the second hole acceleration layer, the thickness of a single second MgN sub-layer is 3nm, and the thickness of a single InGaN sub-layer is 4nm.
The number of cycles of the first hole acceleration layer is 4, and the growth temperature is 850 ℃; the number of cycles of the second hole acceleration layer was 4, and the growth temperature was 850 ℃.
The thickness of the graphene layer is 6nm, and the graphene layer is prepared by adopting a Physical Vapor Deposition (PVD) method.
The epitaxial wafer further comprises a nucleation layer, an intrinsic GaN layer, an N-type layer and a multiple quantum well layer which are sequentially deposited on the substrate, and an electron blocking layer is deposited on the multiple quantum well layer.
Wherein the electron blocking layer is made of Al y Ga 1-y N material layer and In z Ga 1-z The periodic structure of the alternate growth of the N material layers, wherein y is 0.2 and z is 0.1.
The invention discloses a preparation method of a light-emitting diode epitaxial wafer, which comprises the following steps:
s100, providing a substrate;
s200, depositing an epitaxial layer on a substrate;
the epitaxial wafer comprises an electron blocking layer and a P-type layer which are sequentially laminated along the epitaxial direction, and an inserting layer is arranged between the electron blocking layer and the P-type layer;
the insertion layer comprises a first hole acceleration layer, an intermediate buffer layer and a second hole acceleration layer which are sequentially laminated along the epitaxial direction;
the first hole acceleration layer is a superlattice structure formed by periodically and alternately growing a first MgN sub-layer and an AlInGaN sub-layer, the middle buffer layer is a graphene layer, and the second hole acceleration layer is a superlattice structure formed by periodically and alternately growing a second MgN sub-layer and an InGaN sub-layer.
The specific steps of depositing the epitaxial layer on the substrate in step S200 are as follows:
s210, depositing a nucleation layer on a substrate: the nucleation layer is an AlGaN material layer;
s220, depositing an intrinsic GaN layer on the nucleation layer;
s230, depositing an N-type layer on the intrinsic GaN layer;
s240, depositing a multi-quantum well layer on the N-type layer: the multi-quantum well layer is a periodic structure formed by alternately stacking InGaN quantum well layers and GaN quantum barrier layers;
s250, depositing an electron blocking layer on the multiple quantum well layer;
s260, depositing an insertion layer on the electron blocking layer:
s261, depositing a first hole acceleration layer on the electron blocking layer:
specifically, alternately growing a first MgN sub-layer and an AlInGaN sub-layer;
s262, depositing an intermediate buffer layer on the first hole acceleration layer:
specifically, the intermediate buffer layer is a graphene layer;
s263. depositing a second hole acceleration layer on the intermediate buffer layer:
specifically, the second MgN sub-layer and the InGaN sub-layer are alternately grown.
And S270, depositing a P-type layer on the insertion layer.
Furthermore, the invention discloses a light-emitting diode, which comprises the light-emitting diode epitaxial wafer.
Example 2
The invention discloses a light-emitting diode epitaxial wafer, which comprises a substrate and an epitaxial wafer laminated on the substrate, wherein the epitaxial wafer comprises an electron blocking layer and a P-type layer which are laminated in turn along the epitaxial direction, and an inserting layer is arranged between the electron blocking layer and the P-type layer;
the insertion layer comprises a first hole acceleration layer, an intermediate buffer layer and a second hole acceleration layer which are sequentially laminated along the epitaxial direction;
the first hole acceleration layer is a superlattice structure formed by periodically and alternately growing a first MgN sub-layer and an AlInGaN sub-layer, the middle buffer layer is a graphene layer, and the second hole acceleration layer is a superlattice structure formed by periodically and alternately growing a second MgN sub-layer and an InGaN sub-layer.
Wherein, in the AlInGaN sub-layer, the Al content decreases with the increase of the cycle number of the first hole acceleration layer, and the In content increases with the increase of the cycle number of the first hole acceleration layer.
Wherein, the Al content in the AlInGaN sub-layer decreases from 0.4 to 0.01 along with the increase of the cycle number of the first hole acceleration layer.
In the AlInGaN sub-layer, the In content increases from 0.01 to 0.1 along with the increase of the cycle number of the first hole acceleration layer.
Wherein, in content In InGaN sub-layer is 0.05.
In the first hole acceleration layer, the thickness of a single MgN sub-layer is 2nm, and the thickness of a single AlInGaN sub-layer is 3nm; in the second hole acceleration layer, the thickness of a single second MgN sub-layer is 3nm, and the thickness of a single InGaN sub-layer is 4nm.
The number of cycles of the first hole acceleration layer is 4, and the growth temperature is 850 ℃; the number of cycles of the second hole acceleration layer was 4, and the growth temperature was 850 ℃.
The thickness of the graphene layer is 6nm, and the graphene layer is prepared by adopting a Physical Vapor Deposition (PVD) method.
The epitaxial wafer further comprises a nucleation layer, an intrinsic GaN layer, an N-type layer and a multiple quantum well layer which are sequentially deposited on the substrate, and an electron blocking layer is deposited on the multiple quantum well layer.
Wherein the electron blocking layer is made of Al y Ga 1-y N material layer and In z Ga 1-z The periodic structure of the alternate growth of the N material layers, wherein y is 0.2 and z is 0.1.
The invention discloses a preparation method of a light-emitting diode epitaxial wafer, which comprises the following steps:
s100, providing a substrate;
s200, depositing an epitaxial layer on a substrate;
the epitaxial wafer comprises an electron blocking layer and a P-type layer which are sequentially laminated along the epitaxial direction, and an inserting layer is arranged between the electron blocking layer and the P-type layer;
the insertion layer comprises a first hole acceleration layer, an intermediate buffer layer and a second hole acceleration layer which are sequentially laminated along the epitaxial direction;
the first hole acceleration layer is a superlattice structure formed by periodically and alternately growing a first MgN sub-layer and an AlInGaN sub-layer, the middle buffer layer is a graphene layer, and the second hole acceleration layer is a superlattice structure formed by periodically and alternately growing a second MgN sub-layer and an InGaN sub-layer.
The specific steps of depositing the epitaxial layer on the substrate in step S200 are as follows:
s210, depositing a nucleation layer on a substrate: the nucleation layer is an AlGaN material layer;
s220, depositing an intrinsic GaN layer on the nucleation layer;
s230, depositing an N-type layer on the intrinsic GaN layer;
s240, depositing a multi-quantum well layer on the N-type layer: the multi-quantum well layer is a periodic structure formed by alternately stacking InGaN quantum well layers and GaN quantum barrier layers;
s250, depositing an electron blocking layer on the multiple quantum well layer;
s260, depositing an insertion layer on the electron blocking layer:
s261, depositing a first hole acceleration layer on the electron blocking layer:
specifically, alternately growing a first MgN sub-layer and an AlInGaN sub-layer;
s262, depositing an intermediate buffer layer on the first hole acceleration layer:
specifically, the intermediate buffer layer is a graphene layer;
s263. depositing a second hole acceleration layer on the intermediate buffer layer:
specifically, the second MgN sub-layer and the InGaN sub-layer are alternately grown.
And S270, depositing a P-type layer on the insertion layer.
Furthermore, the invention discloses a light-emitting diode, which comprises the light-emitting diode epitaxial wafer.
Example 3
The invention discloses a light-emitting diode epitaxial wafer, which comprises a substrate and an epitaxial wafer laminated on the substrate, wherein the epitaxial wafer comprises an electron blocking layer and a P-type layer which are laminated in turn along the epitaxial direction, and an inserting layer is arranged between the electron blocking layer and the P-type layer;
the insertion layer comprises a first hole acceleration layer, an intermediate buffer layer and a second hole acceleration layer which are sequentially laminated along the epitaxial direction;
the first hole acceleration layer is a superlattice structure formed by periodically and alternately growing a first MgN sub-layer and an AlInGaN sub-layer, the middle buffer layer is a graphene layer, and the second hole acceleration layer is a superlattice structure formed by periodically and alternately growing a second MgN sub-layer and an InGaN sub-layer.
Wherein, in the AlInGaN sub-layer, the Al content is kept constant, and the Al content is 0.2.
In the AlInGaN sub-layer, the In content is kept constant, and the In content is 0.001.
In the InGaN sub-layer, the In content is 0.08.
In the first hole acceleration layer, the thickness of a single MgN sub-layer is 2nm, and the thickness of a single AlInGaN sub-layer is 3nm; in the second hole acceleration layer, the thickness of a single second MgN sub-layer is 3nm, and the thickness of a single InGaN sub-layer is 4nm.
The number of cycles of the first hole acceleration layer is 4, and the growth temperature is 850 ℃; the number of cycles of the second hole acceleration layer was 4, and the growth temperature was 850 ℃.
The thickness of the graphene layer is 6nm, and the graphene layer is prepared by adopting a Physical Vapor Deposition (PVD) method.
The epitaxial wafer further comprises a nucleation layer, an intrinsic GaN layer, an N-type layer and a multiple quantum well layer which are sequentially deposited on the substrate, and an electron blocking layer is deposited on the multiple quantum well layer.
Wherein the electron blocking layer is made of Al y Ga 1-y N material layer and In z Ga 1-z The periodic structure of the alternate growth of the N material layers, wherein y is 0.2 and z is 0.1.
The invention discloses a preparation method of a light-emitting diode epitaxial wafer, which comprises the following steps:
s100, providing a substrate;
s200, depositing an epitaxial layer on a substrate;
the epitaxial wafer comprises an electron blocking layer and a P-type layer which are sequentially laminated along the epitaxial direction, and an inserting layer is arranged between the electron blocking layer and the P-type layer;
the insertion layer comprises a first hole acceleration layer, an intermediate buffer layer and a second hole acceleration layer which are sequentially laminated along the epitaxial direction;
the first hole acceleration layer is a superlattice structure formed by periodically and alternately growing a first MgN sub-layer and an AlInGaN sub-layer, the middle buffer layer is a graphene layer, and the second hole acceleration layer is a superlattice structure formed by periodically and alternately growing a second MgN sub-layer and an InGaN sub-layer.
The specific steps of depositing the epitaxial layer on the substrate in step S200 are as follows:
s210, depositing a nucleation layer on a substrate: the nucleation layer is an AlGaN material layer;
s220, depositing an intrinsic GaN layer on the nucleation layer;
s230, depositing an N-type layer on the intrinsic GaN layer;
s240, depositing a multi-quantum well layer on the N-type layer: the multi-quantum well layer is a periodic structure formed by alternately stacking InGaN quantum well layers and GaN quantum barrier layers;
s250, depositing an electron blocking layer on the multiple quantum well layer;
s260, depositing an insertion layer on the electron blocking layer:
s261, depositing a first hole acceleration layer on the electron blocking layer:
specifically, alternately growing a first MgN sub-layer and an AlInGaN sub-layer;
s262, depositing an intermediate buffer layer on the first hole acceleration layer:
specifically, the intermediate buffer layer is a graphene layer;
s263. depositing a second hole acceleration layer on the intermediate buffer layer:
specifically, the second MgN sub-layer and the InGaN sub-layer are alternately grown.
And S270, depositing a P-type layer on the insertion layer.
Furthermore, the invention discloses a light-emitting diode, which comprises the light-emitting diode epitaxial wafer.
Comparative example 1
The present comparative example is different from example 1 in that the insertion layer of the present comparative example does not contain an intermediate buffer layer, and the epitaxial wafer is prepared correspondingly without a growth step of the intermediate buffer layer.
Comparative example 2
The present comparative example is different from example 1 in that the first hole acceleration layer of the insertion layer of the present comparative example adopts the same structure as the second hole acceleration layer, specifically:
the first hole acceleration layer is in a superlattice structure formed by periodically and alternately growing the second MgN sub-layers and the InGaN sub-layers, the number of periods is 4, the thickness of a single second MgN sub-layer in the first hole acceleration layer is 3nm, and the thickness of a single InGaN sub-layer is 4nm.
Comparative example 3
The present comparative example is different from example 1 in that the insertion layer of the present comparative example does not contain the second hole acceleration layer, and the production method of the epitaxial wafer does not provide a growth step of the second hole acceleration layer accordingly.
Comparative example 4
This comparative example is different from example 1 in that the present comparative example is not provided with an interposed layer.
Performance test:
test sample: examples 1 to 3, comparative examples 1 to 4
The testing method comprises the following steps:
(1) Surface roughness test:
testing the surface roughness (rms) of the epitaxial wafer of each experimental group by adopting AFM equipment;
(2) Brightness and antistatic performance test:
processing epitaxial wafers of each experimental group into 10×24mil LED chips with vertical structures, and testing the antistatic capability and the luminous brightness of the LED chips;
1) Brightness test: when 120mA of current is introduced, testing the luminous intensity of the obtained chip;
2) Antistatic performance test: the antistatic performance of the base chip is tested by using an electrostatic instrument under an HBM (human body discharge model) model, and the test chip can bear the passing proportion of reverse 8000V static electricity.
The test results are shown in the following table:
the foregoing description is only illustrative of the preferred embodiment of the present invention, and is not to be construed as limiting the invention, but is to be construed as limiting the invention to any and all simple modifications, equivalent variations and adaptations of the embodiments described above, which are within the scope of the invention, may be made by those skilled in the art without departing from the scope of the invention.
Claims (10)
1. The epitaxial wafer of the light-emitting diode comprises a substrate and an epitaxial wafer which is laminated on the substrate, and is characterized in that the epitaxial wafer comprises an electron blocking layer and a P-type layer which are laminated in sequence along the epitaxial direction, and an inserting layer is arranged between the electron blocking layer and the P-type layer;
the insertion layer comprises a first hole acceleration layer, an intermediate buffer layer and a second hole acceleration layer which are sequentially laminated along the epitaxial direction;
the first hole acceleration layer is a superlattice structure formed by periodically and alternately growing a first MgN sub-layer and an AlInGaN sub-layer, the middle buffer layer is a graphene layer, and the second hole acceleration layer is a superlattice structure formed by periodically and alternately growing a second MgN sub-layer and an InGaN sub-layer.
2. The light-emitting diode epitaxial wafer of claim 1, wherein the Al content In the AlInGaN sub-layer decreases with increasing number of cycles of the first hole acceleration layer, and the In content increases with increasing number of cycles of the first hole acceleration layer.
3. The light-emitting diode epitaxial wafer of claim 2, wherein the Al content in the AlInGaN sub-layer decreases from a to b with increasing number of periods of the first hole acceleration layer, wherein 0.1 ∈a ∈0.4 and 0.01 ∈b ∈0.05.
4. The light-emitting diode epitaxial wafer of claim 2, wherein the In content In the AlInGaN sub-layer increases from c to d with increasing number of periods of the first hole acceleration layer, wherein 0 < c < 0.05,0.05 ∈d ∈0.1.
5. The light-emitting diode epitaxial wafer of claim 1, wherein In content In the InGaN sublayer is 0.05-0.1.
6. The light emitting diode epitaxial wafer of claim 1, wherein in the first hole acceleration layer, the thickness of a single first MgN sub-layer is 0.1nm to 5nm, and the thickness of a single AlInGaN sub-layer is 0.1nm to 5nm; in the second hole acceleration layer, the thickness of a single second MgN sub-layer is 0.1 nm-5 nm, and the thickness of a single InGaN sub-layer is 0.1 nm-5 nm.
7. The light-emitting diode epitaxial wafer according to claim 1, wherein the number of cycles of the first hole acceleration layer is 1 to 5, and the growth temperature is 800 ℃ to 1000 ℃; the number of cycles of the second hole acceleration layer is 1-5, and the growth temperature is 800-1000 ℃.
8. The light-emitting diode epitaxial wafer of claim 1, wherein the graphene layer has a thickness of 1 nm-10 nm and is prepared by a physical vapor deposition method.
9. The preparation method of the light-emitting diode epitaxial wafer is characterized by comprising the following steps of:
providing a substrate;
depositing an epitaxial layer on the substrate;
the epitaxial wafer comprises an electron blocking layer and a P-type layer which are sequentially laminated along the epitaxial direction, and an inserting layer is arranged between the electron blocking layer and the P-type layer;
the insertion layer comprises a first hole acceleration layer, an intermediate buffer layer and a second hole acceleration layer which are sequentially laminated along the epitaxial direction;
the first hole acceleration layer is a superlattice structure formed by periodically and alternately growing a first MgN sub-layer and an AlInGaN sub-layer, the middle buffer layer is a graphene layer, and the second hole acceleration layer is a superlattice structure formed by periodically and alternately growing a second MgN sub-layer and an InGaN sub-layer.
10. A light emitting diode comprising the light emitting diode epitaxial wafer according to any one of claims 1 to 8.
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