CN116130572A - Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode - Google Patents

Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode Download PDF

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CN116130572A
CN116130572A CN202310409318.4A CN202310409318A CN116130572A CN 116130572 A CN116130572 A CN 116130572A CN 202310409318 A CN202310409318 A CN 202310409318A CN 116130572 A CN116130572 A CN 116130572A
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layer
moo
emitting diode
light
epitaxial wafer
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郑文杰
曹斌斌
程龙
高虹
刘春杨
胡加辉
金从龙
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Jiangxi Zhao Chi Semiconductor Co Ltd
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Jiangxi Zhao Chi Semiconductor Co Ltd
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Priority to CN202310865027.6A priority patent/CN116914048A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • H01L33/18—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The invention discloses a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode, and relates to the field of semiconductor photoelectric devices. The light-emitting diode epitaxial wafer comprises a substrate, a buffer layer, an undoped AlGaN layer, an N-type AlGaN layer, a multiple quantum well layer, an electron blocking layer, a P-type AlGaN layer and a P-type contact layer which are sequentially laminated on the substrate, wherein the P-type contact layer comprises a P-AlInN layer and a first MoO which are sequentially laminated on the P-type AlGaN layer 3 Layers, P-AlInGaN layers, and P-GaN layers. By implementing the invention, the luminous efficiency of the LED epitaxial wafer can be improved.

Description

Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
Technical Field
The invention relates to the field of semiconductor photoelectric devices, in particular to a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode.
Background
In the AlGaN-based light emitting diode, due to the introduction of Al, the activation energy of the doping element Mg in the P-type layer is increased, so that the activation efficiency is lower. After the electrode of the light-emitting diode is prepared subsequently, the ohmic contact between the electrode and the P-type layer is poor, and the light-emitting efficiency of the light-emitting diode is reduced.
The current common method is to form a heavily doped P-type AlGaN layer on the P-type layer, but the doping concentration is still low, so that it is difficult to effectively improve the ohmic contact, and therefore, the thickness of the heavily doped P-type AlGaN layer needs to be increased, but the light absorption is increased by increasing the thickness, and the light emitting efficiency is reduced.
Disclosure of Invention
The invention aims to solve the technical problem of providing a light-emitting diode epitaxial wafer and a preparation method thereof, which can improve the luminous efficiency of a light-emitting diode.
The invention also solves the technical problem of providing a light-emitting diode with high luminous efficiency.
In order to solve the problems, the invention discloses a light-emitting diode epitaxial wafer, which comprises a substrate, a buffer layer, an undoped AlGaN layer, an N-type AlGaN layer, a multiple quantum well layer, an electron blocking layer, a P-type AlGaN layer and a P-type contact layer which are sequentially laminated on the substrate, wherein the P-type contact layer comprises a P-AlInN layer and a first MoO which are sequentially laminated on the P-type AlGaN layer 3 Layers, P-AlInGaN layers, and P-GaN layers.
As an improvement of the technical scheme, the proportion of the Al component in the P-AlInN layer is 0.02-0.15, and the proportion of the in component is 0.3-0.45; the P-type doping element of the P-AlInN layer is Mg, and the doping concentration is 1 multiplied by 10 19 cm -3 ~5×10 19 cm -3 ；
The saidThe proportion of an In component In the P-AlInGaN layer is 0.1-0.2, and the proportion of an Al component In the P-AlInGaN layer is 0.05-0.15; the P-type doping element of the P-AlInGaN layer is Mg, and the doping concentration is 8 multiplied by 10 19 cm -3 ~3×10 20 cm -3 ；
The P-type doping element of the P-GaN layer is Mg, and the doping concentration is 5 multiplied by 10 20 cm -3 ~2×10 21 cm -3 。
As an improvement of the technical scheme, the thickness of the P-AlInN layer is 1 nm-5 nm, and the first MoO 3 The thickness of the layer is 0.5-3 nm, the thickness of the P-AlInGaN layer is 20-50 nm, and the thickness of the P-GaN layer is 50-200 nm.
As an improvement of the above technical solution, the first MoO 3 And (3) carrying out annealing treatment in a selenium source after the layer growth is finished, wherein the annealing treatment temperature is 600-700 ℃, and the annealing treatment time is 300-600 s.
As an improvement of the above technical solution, the P-type contact layer further includes a second MoO laminated on the P-GaN layer 3 A layer of the second MoO 3 Annealing treatment is carried out in a selenium source after the layer growth is completed, wherein the annealing treatment temperature is 650-700 ℃, and the annealing treatment time is 600-1000 s;
the second MoO 3 The thickness of the layer is 0.5 nm-5 nm.
As an improvement of the above technical solution, the P-type contact layer further includes a second MoO layer laminated on the second MoO layer 3 A graphene layer on the layer; the thickness of the graphene layer is 0.1 nm-2 nm.
Correspondingly, the invention also discloses a preparation method of the light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer and comprises the following steps:
providing a substrate, sequentially forming a buffer layer, an undoped AlGaN layer, an N-type AlGaN layer, a multiple quantum well layer, an electron blocking layer, a P-type AlGaN layer and a P-type contact layer on the substrate, wherein the P-type contact layer comprises a P-AlInN layer and a first MoO which are sequentially laminated on the P-type AlGaN layer 3 Layers, P-AlInGaN layers, and P-GaN layers.
As an improvement of the technical scheme, the P-AlInN layer grows by an MOCVD method, the growth temperature is 900-1000 ℃, and the growth pressure is 200-400 torr;
the first MoO 3 The layer is grown by ALD method, and Mo source adopted during growth is Mo (CO) 6 The adopted O source is O 3 The carrier gas is Ar, and the growth temperature is 150-200 ℃;
the P-AlInGaN layer grows through an MOCVD method, the growth temperature is 900-1000 ℃, and the growth pressure is 100-300 torr;
the P-GaN layer grows through an MOCVD method, the growth temperature is 950-1050 ℃, and the growth pressure is 100-300 torr.
As an improvement of the above technical solution, the P-type contact layer further includes a second MoO laminated on the P-GaN layer 3 A layer and a graphene layer;
the second MoO 3 The layer is grown by ALD method, and Mo source adopted during growth is Mo (CO) 6 The adopted O source is O 3 The carrier gas is Ar, and the growth temperature is 150-200 ℃;
the graphene layer is obtained by transferring a graphene layer on a copper substrate.
Correspondingly, the invention also discloses a light-emitting diode, which comprises the light-emitting diode epitaxial wafer.
The implementation of the invention has the following beneficial effects:
1. the invention relates to a light-emitting diode epitaxial wafer, wherein a P-type contact layer comprises a P-AlInN layer and a first MoO which are sequentially laminated on a P-type AlGaN layer 3 A layer, a P-AlInGaN layer, and a P-GaN layer; wherein, the first MoO 3 The band gap of the layer is wider, which is beneficial to improving the concentration of P-type doping in the adjacent layer P-AlInGaN. The P-AlInGaN layer can provide In, which can reduce the activation energy of P-type doping, improve the P-type doping concentration of the subsequent P-GaN layer, improve the hole concentration and improve the luminous efficiency. The P-AlInN layer can suppress the first MoO due to its higher dielectric constant 3 Long Cheng Kulun reflection in the layer effectively improves carrier migration efficiency and avoids the first MoO 3 The layer affects hole carrier transport; in addition, the lattice constant of the P-AlInN layer is between that of the P-type AlGaN layer and the first MoO 3 Between layers, can well relieve lattice mismatch and avoid generation of strongPiezoelectric polarization reduces the luminous efficiency.
2. The light-emitting diode epitaxial wafer of the invention, the first MoO 3 Annealing treatment is also performed in the selenium source after the layer growth is completed. Based on the annealing treatment, the method can be used for preparing the first MoO 3 Surface formation of layer MoS 2 A layer for further lifting the first MoO 3 The carrier mobility of the whole layer improves the luminous efficiency.
3. The light-emitting diode epitaxial wafer of the invention, the P-type contact layer also comprises a second MoO laminated on the P-GaN layer 3 Layer, second MoO 3 The layer can further improve the concentration of P-type doping in the P-GaN layer and improve the luminous efficiency of the light emitting diode.
4. The LED epitaxial wafer of the invention, the P-type contact layer also comprises a second MoO layer 3 A graphene layer on the layer; the graphene layer has strong conductivity, can promote ohmic contact between an electrode and a P-type contact layer in a subsequent light-emitting diode structure, and is also beneficial to current diffusion.
Drawings
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an embodiment of a contact layer of Europe;
FIG. 3 is a schematic diagram of an ohmic contact layer according to another embodiment of the present invention;
FIG. 4 is a schematic diagram of a structure of an Europe contact layer according to another embodiment of the present invention;
fig. 5 is a flowchart of a method for manufacturing an led epitaxial wafer according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail below in order to make the objects, technical solutions and advantages of the present invention more apparent.
Referring to fig. 1 and 2, the invention discloses a light emitting diode epitaxial wafer, which comprises a substrate 1, a buffer layer 2, an undoped AlGaN layer 3, an N-type AlGaN layer 4, a multiple quantum well layer 5, an electron blocking layer 6, a P-type AlGaN layer 7 and a P-type contact layer 8 which are sequentially stacked on the substrate 1. Wherein the P-type contact layer 8 comprises a P-type AlGaN layer 7 laminated in sequenceAlInN layer 81, first MoO 3 Layer 82, P-AlInGaN layer 83, and P-GaN layer 84. Based on the P-type contact layer 8, the concentration of hole carriers can be effectively improved, and the luminous efficiency is improved.
Wherein the ratio of Al component in the P-AlInN layer 81 is 0.02-0.2, and when the ratio of Al component is less than 0.02, the first MoO 3 The lattice mismatch between the layer 82 and the P-type AlGaN layer 7 is large, the piezoelectric polarization effect is strong, and the luminous efficiency is reduced; when the Al component ratio is more than 0.2, the dielectric constant of the P-AlInN layer 81 is low, the first MoO 3 Layer 82 reduces carrier mobility and reduces light emission efficiency. Illustratively, the Al component of the P-AlInN layer 81 has a ratio of 0.04, 0.06, 0.1, 0.13, 0.15, or 0.17, but is not limited thereto. Preferably 0.02 to 0.15.
The In component of the P-AlInN layer 81 has a ratio of 0.25 to 0.5, and exemplary values are, but not limited to, 0.27, 0.3, 0.35, 0.4, 0.44, or 0.48. Preferably 0.3 to 0.45. The P-type doping element of the P-AlInN layer 81 is Mg, but is not limited thereto. The doping concentration of the P-AlInN layer 81 is 1×10 19 cm -3 ~1×10 20 cm -3 Exemplary is 2X 10 19 cm -3 、4×10 19 cm -3 、5×10 19 cm -3 、7×10 19 cm -3 Or 9X 10 19 cm -3 But is not limited thereto. Preferably, the doping concentration of the P-AlInN layer 81 is 1×10 19 cm -3 ~5×10 19 cm -3 。
The thickness of the P-AlInN layer 81 is 0.5nm to 10nm, and exemplary is 0.7nm, 1nm, 2nm, 3nm, 4nm or 8nm, but is not limited thereto. Preferably, the thickness of the P-AlInN layer 81 is 1nm to 5nm.
Wherein, the first MoO 3 The thickness of layer 82 is 0.5nm to 5nm, and exemplary is 0.7nm, 1.2nm, 1.8nm, 2nm, 3nm, 3.8nm, or 4.4nm, but is not limited thereto. Preferably, the first MoO 3 The thickness of layer 82 is 0.5nm to 3nm.
Preferably, in one embodiment of the present invention, the first MoO 3 After the growth of layer 82 is completed, an annealing treatment is performed in an atmosphere containing a selenium source, based on which a first MoO may be performed 3 Surface formation MoS of layer 82 2 A layer for further lifting the firstA MoO 3 The carrier mobility of the layer 82 as a whole improves the light emitting efficiency. The selenium source is DMSe, ar is used as carrier gas, the annealing treatment temperature is 600-700 ℃, and the annealing treatment time is 300-600 s. When the annealing treatment time is short or the temperature is low, it is difficult to obtain the first MoO 3 Formation of MoS on layer 82 2 A layer, when the annealing treatment time is longer or the annealing temperature is higher, formed MoS 2 The layer thickness is large, the carrier mobility is high, but the first MoO 3 The lattice mismatch between layer 82 and P-AlInGaN layer 83 increases.
Wherein the In component of the P-AlInGaN layer 83 has a duty ratio of 0.1-0.3, and when the duty ratio is less than 0.1, one has a lower activation effect on the P-type doping of the subsequent P-GaN layer 84, and the two have smaller lattice constants, so that it is difficult to buffer the first MoO effectively 3 Lattice mismatch between layer 82 and P-GaN layer 84. When the In composition ratio In the P-AlInGaN layer 83 is > 0.3, the lattice quality thereof is poor. Illustratively, the In composition of the P-AlInGaN layer 83 has a duty ratio of 0.12, 0.15, 0.18, 0.2, 0.23, or 0.27, but is not limited thereto. Preferably, the proportion of the In component In the P-AlInGaN layer 83 is 0.1 to 0.2.
The ratio of the Al component in the P-AlInGaN layer 83 is 0.05 to 0.15, and exemplary is 0.08, 0.1 or 0.12, but is not limited thereto. Preferably, the Al component of the P-AlInGaN layer 83 has a ratio of 0.05-0.15. The P-type doping element of the P-AlInGaN layer 83 is Mg, but is not limited thereto. The doping concentration of the P-AlInGaN layer 83 is 5×10 19 cm -3 ~5×10 20 cm -3 Exemplary is 7X 10 19 cm -3 、9×10 19 cm -3 、1.5×10 20 cm -3 、3×10 20 cm -3 But is not limited thereto. Preferably, the P-AlInGaN layer 83 has a doping concentration of 8×10 19 cm -3 ~3×10 20 cm -3 。
The thickness of the P-AlInGaN layer 83 is 10nm to 100nm, and is exemplified by, but not limited to, 15nm, 20nm, 30nm, 40nm, 60nm, 70nm, or 90 nm. Preferably, the thickness of the P-AlInGaN layer 83 is 20nm to 50nm.
The P-type doping element of the P-GaN layer 84 is Mg, but is not limited thereto. The doping concentration of the P-GaN layer 84 is 5×10 20 cm -3 ~5×10 21 cm -3 Exemplary is 6X 10 20 cm -3 、8×10 20 cm -3 、1×10 21 cm -3 、3×10 21 cm -3 Or 4X 10 21 cm -3 But is not limited thereto. Preferably 5X 10 20 cm -3 ~2×10 21 cm -3 。
The thickness of the P-GaN layer 84 is 30nm to 300nm, and is exemplified by 40nm, 100nm, 150nm, 220nm, or 280nm, but not limited thereto. Preferably 50nm to 200nm.
Preferably, in one embodiment of the present invention, the doping concentration of the P-GaN layer 84 > the doping concentration of the P-AlInGaN layer 83 > the doping concentration of the P-AlInN layer 81 > the doping concentration of the P-AlGaN layer 7 is controlled, and based on this arrangement, the mobility of hole carriers can be further increased, and the light emitting efficiency can be improved.
Preferably, referring to FIG. 3, in one embodiment of the present invention, the P-type contact layer 8 further comprises a second MoO laminated on the P-GaN layer 84 3 Layer 85, second MoO 3 And (3) after the growth of the layer 85 is finished, annealing in a selenium source, wherein the annealing temperature is 650-700 ℃, and the annealing time is 600-1000 s.
Wherein the second MoO 3 The thickness of the layer 85 is 0.5nm to 5nm, and exemplary is 0.8nm, 1.2nm, 2.5nm, 3nm, 3.8nm, or 4.5nm, but is not limited thereto.
Preferably, referring to fig. 4, in one embodiment of the present invention, the P-type contact layer 8 further comprises a second MoO laminated thereon 3 The graphene layer 86 on the layer 85 has a thickness of 0.1nm to 2nm, and is exemplified by, but not limited to, 0.3nm, 0.5nm, 0.8nm, 1.4nm, 1.7nm, or 1.9 nm.
Wherein the substrate 1 is a sapphire substrate, a silicon substrate, or Ga 2 O 3 A substrate, a SiC substrate, or a ZnO substrate, but is not limited thereto. A sapphire substrate is preferred.
The buffer layer 2 is an AlN layer, but is not limited thereto. The thickness of the buffer layer 2 is 30nm to 80nm, and exemplary is 35nm, 45nm, 50nm, 60nm or 75nm, but is not limited thereto.
The thickness of the undoped AlGaN layer 3 is 0.5 μm to 2 μm, and exemplary thickness is 0.6 μm, 0.8 μm, 1.1 μm, 1.3 μm or 1.5 μm, but is not limited thereto.
The N-type doping element in the N-type AlGaN layer 4 is Si, but is not limited thereto. The doping concentration of Si in the N-type AlGaN layer 4 is 5×10 18 cm -3 ~8×10 19 cm -3 Exemplary is 6X 10 18 cm -3 、8×10 18 cm -3 、1×10 19 cm -3 、3×10 19 cm -3 Or 5X 10 19 cm -3 But is not limited thereto. Specifically, the thickness of the N-type AlGaN layer 4 is 1 μm to 3 μm, and exemplary is 1.2 μm, 1.6 μm, 2.1 μm, 2.4 μm, or 2.6 μm, but is not limited thereto.
Wherein the multiple quantum well layer 5 is composed of multiple Al α Ga 1-α N-well layer (alpha=0.3-0.5) and Al β Ga 1-β The periodic structure formed by alternately stacking N barrier layers (beta=0.5-0.6) has a period number of 3-15. Wherein, single Al α Ga 1-α The thickness of the N well layer is 2 nm-5 nm, and single Al β Ga 1-β The thickness of the N barrier layer is 5 nm-15 nm.
Wherein the electron blocking layer 6 is Al γ Ga 1-γ N layers (γ=0.55 to 0.7), but is not limited thereto. Specifically, the thickness of the electron blocking layer 6 is 20nm to 100nm, and exemplary is 25nm, 35nm, 40nm, 55nm, 70nm, 85nm or 95nm, but not limited thereto.
The P-type doping element of the P-type AlGaN layer 7 is Mg, but is not limited thereto. The doping concentration of Mg in the P-type AlGaN layer 7 is 5×10 18 cm -3 ~5×10 20 cm -3 Exemplary is 6.5X10 18 cm -3 、8.5×10 18 cm -3 、3×10 19 cm -3 、5×10 19 cm -3 Or 2X 10 20 cm -3 But is not limited thereto. Specifically, the thickness of the P-type AlGaN layer 7 is 100nm to 200nm, and 130nm, 140nm, 180nm or 190nm is exemplified, but not limited thereto.
Correspondingly, referring to fig. 5, the invention also discloses a preparation method of the light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer and comprises the following steps:
s1: providing a substrate;
s2: sequentially growing a buffer layer, an undoped AlGaN layer, an N-type AlGaN layer, a multiple quantum well layer, an electron blocking layer, a P-type AlGaN layer and a P-type contact layer on a substrate;
specifically, step S2 includes:
s21: growing a buffer layer on a substrate;
specifically, S21 includes:
among them, the AlN layer may be grown by PVD method, or the AlN layer may be grown by MOCVD method, but is not limited thereto.
S22: growing an undoped AlGaN layer on the buffer layer;
in one embodiment of the invention, the undoped AlGaN layer is grown by MOCVD, the growth temperature is 1000-1100 ℃, and the growth pressure is 100-500 torr.
S23: growing an N-type AlGaN layer on the undoped AlGaN layer;
in one embodiment of the invention, the N-type AlGaN layer is grown by MOCVD, the growth temperature is 1000 ℃ to 1150 ℃, and the growth pressure is 100torr to 500torr.
S24: growing a multi-quantum well layer on the N-type AlGaN layer;
wherein, in one embodiment of the present invention, a plurality of Al are grown periodically by MOCVD method α Ga 1-α N-well layer and Al β Ga 1-β And (5) an N barrier layer to obtain the multi-quantum well layer. Wherein Al is α Ga 1-α The growth temperature of the N well layer is 900-1000 ℃ and the growth pressure is 100-300 torr. Al (Al) β Ga 1-β The growth temperature of the N barrier layer is 1050-1150 ℃ and the growth pressure is 50-300 torr.
S25: growing an electron blocking layer on the multiple quantum well layer;
in one embodiment of the invention, the electron blocking layer is grown by MOCVD, the growth temperature is 1000 ℃ to 1100 ℃, and the growth pressure is 100torr to 300torr.
S26: growing a P-type AlGaN layer on the electron blocking layer;
in one embodiment of the invention, the P-type AlGaN layer is grown by MOCVD, the growth temperature is 900-1100 ℃, and the growth pressure is 100-300 torr.
S27: growing a P-type contact layer on the P-type AlGaN layer;
wherein, in one embodiment of the present invention, step S27 includes:
s271: growing a P-AlInN layer on the P-AlGaN layer;
in one embodiment of the invention, the P-AlInN layer is grown by MOCVD, the growth temperature is 900-1000 ℃, and the growth pressure is 200-400 torr.
S272: growth of first MoO on P-AlInN layer 3 A layer;
wherein the first MoO can be grown by PVT method, ALD method, PECVD method 3 A layer, but is not limited thereto. Preferably, in one embodiment of the present invention, the first MoO 3 The layer is grown by ALD method, and Mo source adopted during growth is Mo (CO) 6 The adopted O source is O 3 The carrier gas is Ar, and the growth temperature is 150-200 ℃.
Preferably, in one embodiment of the present invention, step S27 further includes:
s273: first MoO 3 Annealing the layer;
in one embodiment of the invention, annealing is performed in an ALD reaction chamber, wherein a selenium source used in annealing is DMSe, ar is used as carrier gas, the annealing temperature is 600-700 ℃, and the annealing time is 300-600 s.
S274: at the first MoO 3 Growing a P-AlInGaN layer on the layer;
in one embodiment of the invention, the P-AlInGaN layer is grown by MOCVD at 900-1000 ℃ under 100-300 torr. By adopting lower growth pressure, in drops can be formed, and the activation energy of P-type doping is reduced.
S275: growing a P-GaN layer on the P-AlInGaN layer;
in one embodiment of the invention, the P-GaN layer is grown by MOCVD, the growth temperature is 950-1050 ℃, and the growth pressure is 100-300 torr.
Preferably, in one embodiment of the present invention, step S27 further includes:
s276: growth of second MoO on P-GaN layer 3 A layer;
wherein the second MoO can be grown by PVT method, ALD method, PECVD method 3 A layer, but is not limited thereto. Preferably, in one embodiment of the invention, the second MoO 3 The layer is grown by ALD method, and Mo source adopted during growth is Mo (CO) 6 The adopted O source is O 3 The carrier gas is Ar, and the growth temperature is 150-200 ℃.
S277: second MoO 3 Annealing the layer;
in one embodiment of the invention, annealing is performed in an ALD reaction chamber, wherein a selenium source used in annealing is DMSe, ar is used as carrier gas, the annealing temperature is 650-700 ℃, and the annealing time is 600-1000 s.
S278: in the second MoO 3 Growing a graphene layer on the layer;
wherein, in one embodiment of the invention, the graphene layer is transferred from the graphene layer on the copper substrate. The graphene layer on the copper substrate may be prepared by PVD methods well known in the art. Specifically, the transfer method of the graphene layer comprises the following steps: stripping the copper substrate provided with the PMMA-graphene layer by adopting ferric chloride solution, cleaning to obtain a PMMA-graphene film, adhering the PMMA-graphene film to the surface of the silicon substrate, heating and laminating at 100-150 ℃, cooling, soaking by adopting acetone solution, and removing PMMA to obtain the PMMA-graphene film.
The invention is further illustrated by the following examples:
example 1
Referring to fig. 1 and 2, the present embodiment provides a light emitting diode epitaxial wafer, which includes a substrate 1, a buffer layer 2, an undoped AlGaN layer 3, an N-type AlGaN layer 4, a multiple quantum well layer 5, an electron blocking layer 6, a P-type AlGaN layer 7, and a P-type contact layer 8.
Wherein the substrate 1 is a sapphire substrate. The buffer layer 2 is an AlN layer having a thickness of 55nm. The undoped AlGaN layer 3 has a thickness of 1.5 μm. The doping element of the N-type AlGaN layer 4 is Si, and the doping is concentratedDegree of 8×10 18 cm -3 The thickness thereof was 2.5. Mu.m.
Wherein the multiple quantum well layer 5 is composed of multiple Al α Ga 1-α N-well layer (α=0.4) and Al β Ga 1-β The periodic structure formed by alternately stacking N barrier layers (β=0.55) has a cycle number of 10. Wherein, single Al α Ga 1-α The thickness of the N well layer is 3nm, single Al β Ga 1-β The thickness of the N barrier layer was 9nm. The electron blocking layer 6 is Al γ Ga 1-γ N layers (γ=0.6) with a thickness of 80nm. The doping element of the P-type AlGaN layer 7 is Mg, and the doping concentration is 5 multiplied by 10 19 cm -3 The thickness thereof was 150nm.
Wherein the P-type contact layer 8 comprises a P-AlInN layer 81 and a first MoO sequentially laminated on the P-type AlGaN layer 7 3 Layer 82, P-AlInGaN layer 83, and P-GaN layer 84. Wherein the ratio of Al component in the P-AlInN layer 81 is 0.1 and the ratio of in component is 0.4. The P-type doping element of the P-AlInN layer 81 is Mg, and the doping concentration is 4×10 19 cm -3 The thickness thereof was 3nm. First MoO 3 Layer 82 has a thickness of 1.5nm. The P-AlInGaN layer 83 has an In component of 0.12 and an al component of 0.08. The P-type doping element of the P-AlInGaN layer 83 is Mg, and the doping concentration is 5×10 19 cm -3 The thickness thereof was 25nm. The P-type doping element of the P-GaN layer 84 is Mg, and the doping concentration is 6X10 20 cm -3 The thickness thereof was 55nm.
The preparation method of the light-emitting diode epitaxial wafer in the embodiment comprises the following steps:
(1) Providing a substrate;
(2) Growing a buffer layer on a substrate;
wherein the AlN layer is grown by PVD.
(3) Growing an undoped AlGaN layer on the buffer layer;
wherein, the undoped AlGaN layer is grown by MOCVD method, the growth temperature is 980 ℃, and the growth pressure is 300torr.
(4) Growing an N-type AlGaN layer on the undoped AlGaN layer;
wherein, the growth temperature of the N-type AlGaN layer is 1100 ℃ and the growth pressure is 200torr by the MOCVD method.
(5) Growing a multi-quantum well layer on the N-type AlGaN layer;
wherein a plurality of Al are periodically grown by MOCVD method α Ga 1-α N-well layer and Al β Ga 1-β And (5) an N barrier layer to obtain the multi-quantum well layer. Wherein Al is α Ga 1-α The growth temperature of the N well layer is 960 ℃, and the growth pressure is 200torr. Al (Al) β Ga 1-β The growth temperature of the N barrier layer is 1060 ℃, and the growth pressure is 200torr.
(6) Growing an electron blocking layer on the multiple quantum well layer;
wherein, the electron blocking layer is grown by MOCVD method, the growth temperature is 1050 ℃, and the growth pressure is 200torr.
(7) Growing a P-type AlGaN layer on the electron blocking layer;
wherein, the P-type AlGaN layer is grown by MOCVD method, the growth temperature is 1000 ℃, and the growth pressure is 200torr.
(8) Growing a P-AlInN layer on the P-AlGaN layer;
wherein, the P-AlInN layer is grown by MOCVD method, the growth temperature is 950 ℃, and the growth pressure is 350torr.
(9) Growth of first MoO on P-AlInN layer 3 A layer;
wherein, the first MoO 3 The layer is grown by ALD method, and Mo source adopted during growth is Mo (CO) 6 The adopted O source is O 3 The carrier gas used was Ar and the growth temperature was 160 ℃.
(10) At the first MoO 3 Growing a P-AlInGaN layer on the layer;
wherein, the P-AlInGaN layer is grown by MOCVD method, the growth temperature is 940 ℃, and the growth pressure is 150torr.
(11) Growing a P-GaN layer on the P-AlInGaN layer;
wherein, the P-GaN layer is grown by MOCVD method, the growth temperature is 1000 ℃, and the growth pressure is 200torr.
Example 2
The present embodiment provides a light emitting diode epitaxial wafer, which is different from embodiment 1 in that, in the first MoO 3 After the layer growth is completed, the ALD reaction is performedAnd annealing is carried out in the chamber, wherein a selenium source adopted by the annealing is DMSe, ar is used as carrier gas, the annealing treatment temperature is 630 ℃, and the annealing treatment time is 500s. Correspondingly, the annealing step is also added in the preparation method.
The remainder was the same as in example 1.
Example 3
The present embodiment provides a light emitting diode epitaxial wafer, which is different from embodiment 2 in that the doping concentration of the P-type AlGaN layer 7 is 2×10 19 cm -3 The doping concentration of the P-AlInN layer 81 is 4×10 19 cm -3 The doping concentration of the P-AlInGaN layer 83 is 1×10 20 cm -3 The doping concentration of the P-GaN layer 84 is 6×10 20 cm -3 。
Example 4
Referring to fig. 1 and 3, the present embodiment provides a light emitting diode epitaxial wafer, which is different from embodiment 3 in that the P-type contact layer 8 further comprises a second MoO laminated on the P-GaN layer 84 3 And annealing the layer 85 in an ALD reaction chamber after the growth of the layer is completed, wherein a selenium source adopted by the annealing is DMSe, ar is used as carrier gas, the annealing treatment temperature is 680 ℃, and the annealing treatment time is 800s. Second MoO 3 Layer 85 has a thickness of 2nm, a second MoO 3 Layer 85 was prepared as described for the first MoO of example 1 3 Layer 82 is prepared in the same manner.
The remainder was the same as in example 3.
Example 5
Referring to fig. 1 and 4, the difference between the present embodiment and embodiment 4 is that the P-type contact layer 8 further includes a second MoO laminated thereon 3 A graphene layer 86 on layer 85, the thickness of graphene layer 86 being 1.2nm.
Specifically, the graphene layer is transferred from a graphene layer on a copper substrate. The graphene layer on the copper substrate may be prepared by PVD methods well known in the art. Specifically, the transfer method of the graphene layer comprises the following steps: and (3) stripping a copper substrate (purchased from Shenzhen six-carbon technology Co., ltd.) provided with a PMMA-graphene layer by adopting ferric chloride solution, cleaning by deionized water to obtain a PMMA-graphene film, adhering the PMMA-graphene film to the surface of a silicon substrate, heating and attaching the PMMA-graphene film at 120 ℃, cooling, soaking the PMMA-graphene film by adopting acetone solution, removing PMMA, and cleaning by adopting deionized water for multiple times to obtain the PMMA-graphene film.
The remainder was the same as in example 4.
Comparative example 1
The present comparative example provides a light emitting diode epitaxial wafer, which is different from example 1 in that the P-type contact layer 8 is a heavily doped P-type AlGaN layer, the doping element is Mg, and the doping concentration is 2×10 20 cm -3 The thickness thereof was 50nm.
The P-type contact layer 8 was produced by the MOCVD method at a growth temperature of 1100 c and a growth pressure of 200torr.
Comparative example 2
This comparative example provides a light emitting diode epitaxial wafer which is different from example 1 in that the P-type contact layer 8 does not include the P-AlInN layer 81, and accordingly, the step of preparing the layer is not included in the preparation method.
Comparative example 3
This comparative example provides a light emitting diode epitaxial wafer which differs from that of example 1 in that the P-type contact layer 8 does not include the first MoO 3 Layer 82, accordingly, is prepared without the step of preparing the layer.
Comparative example 4
This comparative example provides a light emitting diode epitaxial wafer which is different from that of example 1 in that the P-type contact layer 8 does not include the P-AlInGaN layer 83, and accordingly, the step of preparing the layer is not included in the preparation method.
Comparative example 5
This comparative example provides a light emitting diode epitaxial wafer which is different from example 1 in that the P-type contact layer 8 does not include the P-GaN layer 84, and accordingly, the step of preparing the layer is not included in the preparation method.
Comparative example 6
This comparative example provides a light emitting diode epitaxial wafer which is different from example 1 in that the P-type contact layer 8 does not include the P-AlInN layer 81 and the first MoO 3 Layer 82; accordingly, the preparation process does not include a step of preparing the layer.
The light-emitting diode epitaxial wafers of examples 1 to 5 and comparative examples 1 to 6 were each 10, the light-emitting brightness was measured, and the light-emitting brightness improvement ratio was calculated based on the data of comparative example 1, and the specific results are shown in the following table.
The specific test results are shown in the following table:
Figure SMS_1
as can be seen from the table, when the conventional P-type contact layer (comparative example 1) was replaced with the P-type contact layer (example 1) of the present invention, the light emission luminance was improved.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.

Claims (10)

1. A light-emitting diode epitaxial wafer comprises a substrate, wherein a buffer layer, an undoped AlGaN layer, an N-type AlGaN layer, a multiple quantum well layer, an electron blocking layer, a P-type AlGaN layer and a P-type contact layer are sequentially laminated on the substrate, and the P-type contact layer comprises a P-AlInN layer and a first MoO which are sequentially laminated on the P-type AlGaN layer 3 Layers, P-AlInGaN layers, and P-GaN layers.
2. The light-emitting diode epitaxial wafer of claim 1, wherein the P-AlInN layer has an Al component of 0.02 to 0.15 and an in component of 0.3 to 0.45; the P-type doping element of the P-AlInN layer is Mg, and the doping concentration is 1 multiplied by 10 19 cm -3 ~5×10 19 cm -3 ；
The proportion of an In component In the P-AlInGaN layer is 0.1-0.2, and the proportion of an Al component is 0.05-0.15; the P-type doping element of the P-AlInGaN layer is Mg, and the doping concentration is 8 multiplied by 10 19 cm -3 ~3×10 20 cm -3 ；
The P-type doping element of the P-GaN layer is Mg, and the doping concentration is 5 multiplied by 10 20 cm -3 ~2×10 21 cm -3 。
3. The light-emitting diode epitaxial wafer of claim 1, wherein the P-AlInN layer has a thickness of 1nm to 5nm, the first MoO 3 The thickness of the layer is 0.5-3 nm, the thickness of the P-AlInGaN layer is 20-50 nm, and the thickness of the P-GaN layer is 50-200 nm.
4. The light-emitting diode epitaxial wafer according to any one of claims 1 to 3, wherein the first MoO 3 And (3) carrying out annealing treatment in a selenium source after the layer growth is finished, wherein the annealing treatment temperature is 600-700 ℃, and the annealing treatment time is 300-600 s.
5. The light-emitting diode epitaxial wafer of any one of claims 1-3, wherein the P-type contact layer further comprises a second MoO laminated on the P-GaN layer 3 A layer of the second MoO 3 Annealing treatment is carried out in a selenium source after the layer growth is completed, wherein the annealing treatment temperature is 650-700 ℃, and the annealing treatment time is 600-1000 s;
the second MoO 3 The thickness of the layer is 0.5 nm-5 nm.
6. The led epitaxial wafer of claim 5, wherein the P-type contact layer further comprises a layer laminated to the second MoO 3 A graphene layer on the layer; the thickness of the graphene layer is 0.1 nm-2 nm.
7. A method for preparing a light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer according to any one of claims 1 to 6, and is characterized by comprising the following steps:
providing a substrate, sequentially forming a buffer layer, an undoped AlGaN layer, an N-type AlGaN layer, a multiple quantum well layer, an electron blocking layer, a P-type AlGaN layer and a P-type contact layer on the substrate, wherein the P-type contact layer comprises a P-AlInN layer and a first MoO which are sequentially laminated on the P-type AlGaN layer 3 Layers, P-AlInGaN layers, and P-GaN layers.
8. The method for preparing a light-emitting diode epitaxial wafer according to claim 7, wherein the P-AlInN layer is grown by MOCVD at a growth temperature of 900-1000 ℃ and a growth pressure of 200-400 torr;
the first MoO 3 The layer is grown by ALD method, and Mo source adopted during growth is Mo (CO) 6 The adopted O source is O 3 The carrier gas is Ar, and the growth temperature is 150-200 ℃;
the P-AlInGaN layer grows through an MOCVD method, the growth temperature is 900-1000 ℃, and the growth pressure is 100-300 torr;
the P-GaN layer grows through an MOCVD method, the growth temperature is 950-1050 ℃, and the growth pressure is 100-300 torr.
9. The method of manufacturing a light emitting diode epitaxial wafer of claim 7, wherein the P-type contact layer further comprises a second MoO laminated on the P-GaN layer 3 A layer and a graphene layer;
the second MoO 3 The layer is grown by ALD method, and Mo source adopted during growth is Mo (CO) 6 The adopted O source is O 3 The carrier gas is Ar, and the growth temperature is 150-200 ℃;
the graphene layer is obtained by transferring a graphene layer on a copper substrate.
10. A light emitting diode comprising the light emitting diode epitaxial wafer according to any one of claims 1 to 6.
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