CN116724384A - Semiconductor device, power conversion device, and method for manufacturing semiconductor device - Google Patents
Semiconductor device, power conversion device, and method for manufacturing semiconductor device Download PDFInfo
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- CN116724384A CN116724384A CN202280010811.2A CN202280010811A CN116724384A CN 116724384 A CN116724384 A CN 116724384A CN 202280010811 A CN202280010811 A CN 202280010811A CN 116724384 A CN116724384 A CN 116724384A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 218
- 238000006243 chemical reaction Methods 0.000 title claims description 43
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 title claims description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 140
- 239000002184 metal Substances 0.000 claims abstract description 140
- 239000013078 crystal Substances 0.000 claims abstract description 105
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 69
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 52
- 239000000463 material Substances 0.000 claims description 38
- 229910052782 aluminium Inorganic materials 0.000 claims description 32
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 32
- 229910052759 nickel Inorganic materials 0.000 claims description 24
- 229910052742 iron Inorganic materials 0.000 claims description 20
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical group [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 20
- 239000010949 copper Substances 0.000 claims description 17
- 239000000654 additive Substances 0.000 claims description 16
- 230000000996 additive effect Effects 0.000 claims description 16
- 238000007747 plating Methods 0.000 claims description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 229910052698 phosphorus Inorganic materials 0.000 claims description 9
- 239000011574 phosphorus Substances 0.000 claims description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 7
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims description 5
- 238000009713 electroplating Methods 0.000 claims description 5
- 239000011593 sulfur Substances 0.000 claims description 5
- 229910052717 sulfur Inorganic materials 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims description 3
- 239000007791 liquid phase Substances 0.000 claims description 2
- QDWJUBJKEHXSMT-UHFFFAOYSA-N boranylidynenickel Chemical compound [Ni]#B QDWJUBJKEHXSMT-UHFFFAOYSA-N 0.000 claims 1
- OFNHPGDEEMZPFG-UHFFFAOYSA-N phosphanylidynenickel Chemical compound [P].[Ni] OFNHPGDEEMZPFG-UHFFFAOYSA-N 0.000 claims 1
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- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
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- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 2
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
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- 150000002500 ions Chemical class 0.000 description 2
- 229910052749 magnesium Inorganic materials 0.000 description 2
- 229910052748 manganese Inorganic materials 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
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- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 2
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- 238000003860 storage Methods 0.000 description 2
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 2
- 238000012935 Averaging Methods 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
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- 229910052787 antimony Inorganic materials 0.000 description 1
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- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
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- 238000010248 power generation Methods 0.000 description 1
- 238000005204 segregation Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
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Classifications
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05655—Nickel [Ni] as principal constituent
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/484—Connecting portions
- H01L2224/48455—Details of wedge bonds
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
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- H01L2224/732—Location after the connecting process
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A semiconductor device (100) is provided with a semiconductor element (1), a metal film (2), and a lead (3). The semiconductor element (1) includes an electrode (11). The metal film (2) covers the electrode (11) of the semiconductor element (1). The lead (3) is bonded to the metal film (2). The metal film (2) has a higher hardness than the lead (3). In the entire lead (3), the average crystal grain diameter of the lead (3) in a circular cross section is 5 μm or less.
Description
Technical Field
The present disclosure relates to a semiconductor device, a power conversion device, and a method of manufacturing the semiconductor device.
Background
Conventionally, a semiconductor module having a semiconductor element such as a power semiconductor element mounted thereon is known. The power semiconductor device is a power semiconductor device. An electrode is disposed on the semiconductor element. The electrodes are made of, for example, aluminum (Al). Wiring members such as leads are bonded to the electrodes. The wiring member electrically connects the plurality of semiconductor elements to each other. Further, the wiring member electrically connects the semiconductor element and the circuit pattern. For example, a semiconductor device described in japanese patent No. 6132014 (patent document 1) includes a semiconductor element, a metal film, and a lead. The metal film covers the electrode of the semiconductor element. The metal film has a higher hardness than the lead. The wire is bonded to the metal film. The bonding interface of the wire includes only a crystal grain size of 15 μm or less. The portion of the wire away from the bonding interface contains crystals having a particle size of greater than 15 μm.
Prior art literature
Patent literature
Patent document 1: japanese patent No. 6132014
Disclosure of Invention
Problems to be solved by the invention
With miniaturization and higher density of semiconductor devices such as semiconductor modules, the current density of the current flowing through the leads increases. Therefore, there is a problem that the life of the semiconductor element and the wire after bonding is limited as compared with the conventional one. The lifetime of the bonded portion between the semiconductor element and the wire after bonding is evaluated by, for example, a power cycle test.
The present disclosure has been made in view of the above problems, and an object thereof is to provide a semiconductor device, a power conversion device, and a method for manufacturing the semiconductor device, each having a longer reliability lifetime than the conventional one.
Means for solving the problems
The semiconductor device of the present disclosure includes a semiconductor element, a metal film, and a lead. The semiconductor element includes an electrode. The metal film covers the electrode of the semiconductor element. The wire is bonded to the metal film. The metal film has a higher hardness than the lead. The average crystal grain diameter of the lead in the round section of the lead is 5 μm or less.
Effects of the invention
According to the semiconductor device of the present disclosure, the average crystal grain size in the circular cross section of the wire is 5 μm or less in the entire wire. Therefore, the power cycle tolerance of the semiconductor device can be improved, and the effect of having a longer reliability lifetime than before can be obtained.
Drawings
Fig. 1 is a cross-sectional view schematically showing the structure of a semiconductor device according to embodiment 1.
Fig. 2 is a cross-sectional view schematically showing the structure of the semiconductor device according to modification 1 of embodiment 1.
Fig. 3 is a cross-sectional view schematically showing the structure of a semiconductor device according to modification 2 of embodiment 1.
Fig. 4 is an enlarged view of the IV area of fig. 1.
Fig. 5 is an enlarged view schematically showing crystallization of a lead of the semiconductor device of embodiment 1 and corresponding to the IV region in fig. 1.
Fig. 6 is a flowchart schematically showing a method for manufacturing the semiconductor device according to embodiment 1.
Fig. 7 is a cross-sectional view schematically showing a crack generated in the semiconductor device according to embodiment 1 and corresponding to fig. 4.
Fig. 8 is a cross-sectional view schematically showing a crack generated in the semiconductor device according to embodiment 1 and corresponding to fig. 5.
Fig. 9 is a cross-sectional view schematically showing the semiconductor device and crack of comparative example 1.
Fig. 10 is a graph showing the relationship between the average crystal grain size and the power cycle life.
Fig. 11 is a cross-sectional view schematically showing the semiconductor device and crack of comparative example 2.
Fig. 12 is a cross-sectional view schematically showing the semiconductor device and crack of comparative example 3.
Fig. 13 is a cross-sectional view schematically showing the semiconductor device and crack of comparative example 4.
Fig. 14 is a cross-sectional view schematically showing crystallization of a lead of the semiconductor device of embodiment 2.
Fig. 15 is a crystal orientation diagram schematically showing the crystal of the lead of the 1 st structure of the semiconductor device according to the embodiment before the power cycle test.
Fig. 16 is a crystal orientation diagram schematically showing the crystallization of the lead wire of the 2 nd structure of the semiconductor device according to the embodiment before the power cycle test.
Fig. 17 is a crystal orientation diagram schematically showing the crystal of the lead of the semiconductor device of comparative example 1 before the power cycle test.
Fig. 18 is a crystal orientation diagram schematically showing the crystal of the lead of the 1 st structure of the semiconductor device according to the embodiment after the power cycle test.
Fig. 19 is a 1 st cross-sectional view schematically showing crystallization and cracking of a lead of the 1 st structure of the semiconductor device according to the embodiment after the power cycle test.
Fig. 20 is a 2 nd cross-sectional view schematically showing crystallization and cracking of a lead of the 1 st structure of the semiconductor device according to the embodiment after the power cycle test.
Fig. 21 is a 3 rd cross-sectional view schematically showing crystallization and cracking of a lead wire of the 1 st structure of the semiconductor device according to the embodiment after a power cycle test.
Fig. 22 is a crystal orientation diagram schematically showing the crystal of the lead of the 2 nd structure of the semiconductor device according to the embodiment after the power cycle test.
Fig. 23 is a crystal orientation diagram schematically showing the crystal of the lead of the semiconductor device of comparative example 1 after the power cycle test.
Fig. 24 is a cross-sectional view schematically showing crystallization and cracking of a lead of the semiconductor device of comparative example 1 after a power cycle test.
Fig. 25 is an enlarged view of the XXV region of fig. 24.
Fig. 26 is a block diagram schematically showing the configuration of the power conversion device according to embodiment 3.
Detailed Description
Hereinafter, embodiments will be described with reference to the drawings. In the following, the same or corresponding parts are denoted by the same reference numerals, and overlapping description thereof is omitted.
Embodiment 1.
The structure of the semiconductor device 100 according to embodiment 1 will be described with reference to fig. 1 and 2.
As shown in fig. 1, a semiconductor device 100 includes a semiconductor element 1, a metal film 2, and a lead 3. The semiconductor device 100 may further include a circuit pattern 41, a metal pattern 42, an insulating member 43, a heat dissipating member 5, a 1 st bonding material 61, a 2 nd bonding material 62, a case 7, a terminal 8, and a sealing material 9.
In the present embodiment, the semiconductor element 1 is a power semiconductor element. The power semiconductor element is sometimes referred to as a power semiconductor element. The semiconductor element 1 is, for example, a metal oxide semiconductor field effect transistor (MOSFET: metal Oxide Semiconductor Field Effect Transistor), an insulated gate bipolar transistor (IGBT: insulated Gate Bipolar Transistor), or the like.
The semiconductor element 1 comprises an electrode 11. The electrode 11 is, for example, an aluminum (Al) -silicon (Si) electrode. In the present embodiment, the electrode 11 has a lower hardness than the lead 3 and the metal film 2. In the present embodiment, the hardness may be, for example, vickers hardness specified in JIS B7725 or rockwell hardness specified in JIS G0202. The semiconductor element 1 of the present embodiment further includes a back electrode 12 and a substrate portion 13. The back electrode 12 and the electrode 11 sandwich the substrate portion 13. The substrate portion 13 is, for example, a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or the like.
In the present embodiment, the semiconductor element 1 includes a 1 st element portion 1a and a 2 nd element portion 1b. The 1 st element portion 1a and the 2 nd element portion 1b are arranged with a gap therebetween. In the present embodiment, the direction in which the 1 st element portion 1a and the 2 nd element portion 1b are arranged is the 1 st direction DR1. The direction in which the electrode 11 overlaps the substrate 13 is the 2 nd direction DR2. The 1 st direction DR1 intersects the 2 nd direction DR2. In the embodiment, the 1 st direction DR1 is perpendicular to the 2 nd direction DR2.
The metal film 2 covers the electrode 11 of the semiconductor element 1. The metal film 2 is disposed on the opposite side of the electrode 11 from the substrate 13. The metal film 2 has a higher hardness than the lead 3. The detailed structure of the material and the like of the metal film 2 will be described later.
In the present embodiment, the metal film 2 includes a 1 st metal film portion 2a and a 2 nd metal film portion 2b. The 1 st metal film portion 2a covers the electrode 11 of the 1 st element portion 1 a. The 2 nd metal film portion 2b covers the electrode 11 of the 2 nd element portion 1 b.
The lead 3 is, for example, a lead made of aluminum (Al). The lead 3 is bonded to the metal film 2. The lead 3 is bonded to the terminal 8 and the circuit pattern 41. The lead 3 is provided with a 1 st end E1, a 2 nd end E2, and a bent portion B. The 1 st end E1 of the lead 3 is bonded to the metal film 2. The 2 nd end E2 of the lead 3 is joined to the terminal 8. The bent portion B is provided between the 1 st end E1 and the 2 nd end E2. The bending portion B is bent. The bent portion B is bonded to any one of the metal film 2 and the circuit pattern 41.
In the present embodiment, the lead 3 includes a 1 st lead portion 3a and a 2 nd lead portion 3b. The 1 st end E1, the 2 nd end E2, the 1 st bent portion B1, and the 2 nd bent portion B2 of the 1 st lead portion 3a are bonded to the terminal 8, the 2 nd metal film portion 2B, the circuit pattern 41, and the 1 st metal film portion 2a, respectively. The 1 st end E1, 2 nd end E2, and bent portion B3 of the 2 nd lead portion 3B are bonded to the 2 nd metal film portion 2B, the terminal 8, and the circuit pattern 41, respectively.
The wire diameter of the lead 3 is, for example, 100 μm or more and 500 μm or less. When a current flows through the lead 3, the larger the wire diameter of the lead 3 is, the lower the heat generation of the lead 3 can be. Therefore, the wire diameter of the lead 3 is preferably, for example, 400 μm or more and 500 μm or less. In addition, when the wire diameter of the lead wire 3 is large, heat generation of the lead wire 3 can be reduced, and thus, high integration of the lead wire 3 can be achieved. In addition, when the wire diameter of the lead 3 is large, the number of the leads 3 can be reduced, and thus the time required for wiring the lead 3 can be shortened.
The average crystal grain size of the entire lead 3 in the circular cross section of the lead 3 is 5 μm or less. In the present embodiment, the crystal grain size of the lead 3 was evaluated by an electron back scattering diffraction method (EBSD: electron BackScatter Diffraction). The grain size of the lead 3 was evaluated based on the grain boundaries of adjacent crystals. The grain boundaries of adjacent crystals are defined by boundaries at which the crystal orientations of adjacent crystals deviate by 5 ° or more. The average crystal grain size of the entire lead 3 was evaluated based on a crystal orientation chart on a circular cross section of the lead 3 having a diameter equal to the wire diameter of the lead. The strict average crystal grain size is calculated by averaging the crystal grain sizes of a plurality of crystals measured by an analysis method capable of observing crystal grains, such as observation by a cross-sectional SIM (Scanning Ion Microscope: scanning ion microscope). The detailed structure of the crystals of the lead 3 will be described later.
The following hall-peclet relationship is known: the smaller the grain size, the greater the yield strength of the metal. Therefore, the smaller the average crystal grain size of the lead 3, the greater the strength and hardness of the lead 3. Here, if a crack is generated in the lead 3 when the hardness of the lead 3 is greater than that of the metal film 2, there is a problem that the crack progresses into the metal film 2 to shorten the life, and thus peeling (lift-off) to be described later is caused. Cracks that have progressed into the metal film 2 further progress into the electrode 11, and the lifetime may be unexpectedly shortened. In contrast, in the present disclosure, since the hardness of the lead 3 is made smaller than that of the metal film 2, there is an effect that: if a crack is generated in the lead 3, the crack progresses only in the lead 3. As described above, the crystal grain size of the lead 3 is reduced, and the effects of suppressing the crack growth rate and improving the power cycle life are obtained. This operation will be described in detail in paragraphs 0094 to 0097.
The semiconductor element 1 is bonded to the circuit pattern 41. Specifically, the back electrode 12 of the semiconductor element 1 is bonded to the circuit pattern 41 by the 1 st bonding material 61. The 1 st bonding material 61 is, for example, solder, silver (Ag), or the like. The circuit pattern 41 and the metal pattern 42 sandwich the insulating member 43. The circuit pattern 41 and the metal pattern 42 are provided on the insulating member 43, respectively. The metal pattern 42 is bonded to the heat sink member 5 by the 2 nd bonding material 62. The insulating member 43 is constituted as an insulating substrate.
The case 7 encloses the semiconductor element 1, the metal film 2, the lead 3, the circuit pattern 41, the metal pattern 42, the insulating member 43, the 1 st bonding material 61, the 2 nd bonding material 62, and the sealing material 9. An inner space is provided in the housing 7. The semiconductor element 1, the metal film 2, the lead 3, the circuit pattern 41, the metal pattern 42, the insulating member 43, the 1 st bonding material 61, the 2 nd bonding material 62, and the sealing material 9 are accommodated in the internal space. The housing 7 is engaged with the side surfaces and the upper surface of the heat radiating member 5. The lower surface of the heat radiating member 5 is exposed from the housing 7. Although not shown, the case 7 has a ring shape surrounding the heat radiating member 5 when seen from the bottom.
Terminals 8 are arranged in the case 7. The 1 st end of the terminal 8 is disposed in the inner space of the housing 7. The 1 st end of the terminal 8 is exposed from the housing 7 in the inner space of the housing 7. The 2 nd end of the terminal 8 is disposed in an area outside the housing 7. The 2 nd end of the terminal 8 protrudes from the housing 7.
Terminal 8 includes 1 st terminal 81 and 2 nd terminal 82. The 1 st terminal 81 is connected to the 1 st lead portion 3 a. The 2 nd terminal 82 is connected to the 2 nd lead portion 3 b. The 1 st terminal 81 and the 2 nd terminal 82 may be configured as main terminals or power supply terminals.
The inner space of the case 7 is filled with a sealing material 9. The sealing material 9 seals the semiconductor element 1, the metal film 2, the lead 3, the circuit pattern 41, the metal pattern 42, the insulating member 43, the 1 st bonding material 61, and the 2 nd bonding material 62 in the internal space. The sealing material 9 may be a gel-like sealing resin or a molding resin.
As shown in fig. 2, the semiconductor device 100 may further include a lead frame LF. In the case where the semiconductor device 100 includes the lead frame LF, the semiconductor device 100 may not include the case 7. The lead frame LF is bonded to the insulating member 43. In fig. 2, the lead frame LF is in contact with the insulating member 43, but a metal plate, not shown, may be disposed between the lead frame LF and the insulating member 43.
The lead frame LF is partially encapsulated by the encapsulant 9. The end of the lead frame LF protrudes outside the sealing material 9. The end of the lead frame LF is configured as a terminal 8 for connection to equipment external to the semiconductor device 100.
The lead frame LF constitutes a circuit. The 1 st end E1 of the lead 3 is bonded to the semiconductor element 1. The 2 nd end E2 of the lead 3 is bonded to the lead frame LF. The semiconductor element 1 bonded to the lead 3 can be connected to equipment external to the semiconductor device 100 through the lead 3 and the lead frame LF.
In the case where the semiconductor device 100 includes the lead frame LF, the heat dissipation member 5 may be a metal layer, and the insulating member 43 may be an insulating sheet. The insulating sheet is laminated on the metal layer. The insulating sheet is fixed to the metal layer. The insulating sheet may also have an uncured insulating resin layer.
As shown in fig. 3, the metal film 2 disposed on the electrode 11 may be formed only at a portion where the lead 3 is connected to the metal film 2. That is, the metal film 2 may partially cover the electrode 11.
Next, the structure of the semiconductor element 1, the metal film 2, and the lead 3 of the semiconductor device 100 according to embodiment 1 will be described in detail with reference to fig. 4 and 5. Fig. 4 is an enlarged view of the IV area of fig. 1. For convenience of explanation, the sealing material 9 (see fig. 1) is not shown in the enlarged views of fig. 4 and 5. In fig. 7 to 9 and fig. 11 to 14, which will be described later, the sealing material (see fig. 1) is not shown in the drawings, as in fig. 4 and fig. 5.
As shown in fig. 4 and 5, the lead 3 is bonded to the metal film 2 by direct bonding. The lead 3 is bonded to the metal film 2 by ultrasonic bonding, for example. Therefore, the lead 3 is provided with a bonding portion 31 to be bonded to the metal film 2. In the present embodiment, the bonding portion 31 of the lead 3 is a range from the bonding interface BI at which the lead 3 is bonded to the metal film 2 to a position at which the amount of the average crystal grain size of the lead 3 advances toward the inside of the lead 3. The engaging portion 31 is provided along the 1 st direction DR 1. In the present embodiment, since the average crystal grain size is 5 μm or less, the bonding portion 31 of the lead 3 is a range from the bonding interface BI at which the lead 3 is bonded to the metal film 2 to a position that is advanced to 5 μm or less toward the inside of the lead 3. Further, for example, in the case where the average crystal grain diameter of the lead 3 is 10 μm, the bonding portion 31 of the lead 3 is a range from the bonding interface BI at which the lead 3 is bonded to the metal film 2 to a position where it advances to, for example, 10 μm inside the lead 3. Although not shown, the metal film 2 may include a plurality of film portions and a plurality of base films. The plurality of film portions and the plurality of base films are alternately laminated. Thereby, the close fitting property of the metal film 2 is improved. In this case, the film portion is bonded to the lead 3.
As shown in fig. 5, the lead 3 includes a plurality of crystals 30. In the present embodiment, the crystals 30 of the lead 3 are miniaturized.
The metal film 2 may be preferably any of a nickel (Ni) film and a copper (Cu) film. In the case where the metal film 2 is a nickel (Ni) plating film as a nickel (Ni) film, the thickness of the metal film 2 is preferably 3 μm or more and 5 μm or less. In the case where the thickness of the nickel (Ni) plating film is less than 3 μm, breakage of the nickel (Ni) plating film may occur when the lead 3 is bonded to the nickel (Ni) plating film. In the case where the thickness of the nickel (Ni) plating film is more than 5 μm, the formation of the nickel (Ni) plating film takes time, and is therefore economically disadvantageous.
The metal film 2 may be an electroless nickel (Ni) -phosphorus (P) plating film containing no sulfur (S). In this case, the content of phosphorus (P) in the metal film 2 is 8 mass% or less.
The metal film 2 may be an electroless nickel (Ni) -boron (B) plating film.
The metal film 2 may be preferably any of a nickel (Ni) film and a copper (Cu) film formed by electroplating.
The metal film 2 may be preferably any of a nickel (Ni) film, a copper (Cu) film, a titanium (Ti) film, and a tungsten (W) film formed by any of a vapor deposition method and a sputtering method.
As shown in fig. 1, in the case where the semiconductor element 1 has a plurality of element portions such as the 1 st element portion 1a and the 2 nd element portion 1b, a metal film portion is formed on each of the plurality of element portions. In this case, the metal film 2 is preferably formed by plating such as electroless plating or electroplating.
Next, a method for manufacturing the semiconductor device 100 according to embodiment 1 will be described with reference to fig. 1, 2, and 6.
As shown in fig. 6, the method for manufacturing the semiconductor device 100 includes a preparation step S101 and a bonding step S102.
As shown in fig. 1, in a preparation step S101 (see fig. 6), a semiconductor element 1, a metal film 2, and a lead 3 are prepared. In the present embodiment, a circuit pattern 41, a metal pattern 42, an insulating member 43, a heat radiating member 5, a bonding material (1 st bonding material 61), a 2 nd bonding material 62, a case 7, a terminal 8, and a sealing material 9 are also prepared.
The electrode 11 is covered with a metal film 2. The electrode 11 may be covered with the metal film 2 by plating with electroplating. The electrode 11 may be covered with the metal film 2 by plating using electroless plating.
Next, in a bonding step S102 (see fig. 6), the lead 3 is bonded to the metal film 2 covering the electrode 11. In the present embodiment, the lead 3 is bonded to the metal film 2 by ultrasonic bonding. The method of bonding the lead 3 to the metal film 2 can also be appropriately determined.
Further, the 1 st bonding material 61 is heated, whereby the semiconductor element 1 and the circuit pattern 41 are bonded with the 1 st bonding material 61. In the present embodiment, the semiconductor element 1 is bonded to the circuit pattern 41 by a bonding material (1 st bonding material 61) heated to 270 ℃. The metal pattern 42 is bonded to the heat sink member 5 by heating the 2 nd bonding material 62. The sealing material 9 seals the inner space formed by the upper surfaces of the case 7 and the heat sink 5 surrounding the semiconductor element 1, the metal film 2, the leads 3, and the like.
In addition, as shown in fig. 2, when the semiconductor device 100 includes the lead frame LF, in the bonding step S102 (see fig. 6), the insulating member 43 as an insulating sheet in an uncured state is disposed in a molding die not shown. Further, the lower surface of the metal pattern 42 configured as a metal layer is in surface contact with the cavity bottom surface of the molding die. Next, the lead frame LF is arranged in surface contact with the insulating sheet in an uncured state. Next, pressure is applied to the insulating sheet through the lead frame LF. In addition, the sealing material 9 as a molding resin is injected into the cavity of the molding die in a state where pressure is applied. Then, after the molding resin is filled into the entire cavity, the application of pressure is stopped. Next, the molding resin and the insulating sheet in an uncured state are cured.
Next, a power cycle test for evaluating the lifetime of the semiconductor device 100 of embodiment 1 will be described with reference to fig. 7 and 8. In the present embodiment, the lifetime of the semiconductor device 100 refers to a power cycle lifetime evaluated by a power cycle test.
In the power cycle test, switching between an on state in which current flows through the semiconductor element 1 and an off state in which current does not flow through the semiconductor element 1 is alternately repeated. Thereby, the semiconductor element 1 is alternately and repeatedly switched between a state of being heated by the electric current and a state of being naturally cooled. Therefore, stress corresponding to the difference in linear expansion coefficients between the members is repeatedly generated in the joint 31 between the members of the semiconductor device 100. That is, the power cycle test is a fatigue test in which small deformation due to stress is repeatedly applied to an evaluation object. As a result, as shown in fig. 7 and 8, a crack CR may occur in the semiconductor device 100 to be evaluated.
In the case where the sealing material 9 (see fig. 1) is a gel-like sealing resin, the crack CR generated by the power cycle test is developed along the joint 31 where the lead 3 and the metal film 2 are joined. That is, the crack CR mainly progresses along the 1 st direction DR 1. In addition, the lead 3 is separated (peeled) from the electrode 11 by the developed crack CR, and the semiconductor device 100 is broken down. The crack CR is liable to develop in a portion having a smaller strength and a smaller hardness. Further, the crack CR is liable to develop at the joint 31. Specifically, the crack CR tends to progress toward crystals having a larger particle diameter.
Next, the operational effects of the present embodiment will be described.
According to the semiconductor device 100 of embodiment 1, as shown in fig. 5, the average crystal grain size of the entire lead 3 in the circular cross section of the lead 3 is 5 μm or less. Thus, the life of the lead 3 is prolonged. Accordingly, the semiconductor device 100 has a long lifetime.
The operation and effect of the semiconductor device 100 of the present embodiment will be described in detail by comparing the semiconductor device 100 of the present embodiment with the semiconductor device 101 (see fig. 9) of comparative example 1.
As shown in fig. 5, the lead 3 of the semiconductor device 100 according to the present embodiment has an average crystal grain size of 5 μm or less. In contrast, as shown in fig. 9, the average crystal grain size of the lead 3 of the semiconductor device 101 of comparative example 1 is larger than 7 μm.
The life of the semiconductor device 100 according to the present embodiment and the semiconductor device 101 according to comparative example 1 were evaluated by a power cycle test. The test conditions for the power cycle test of this embodiment are as follows. The current value of the current and the time for which the current flows are determined such that the junction temperature (junction temperature) in the on state of the semiconductor element 1 is 100 ℃ higher than the junction temperature in the off state. When the voltage between the emitter and collector of the semiconductor element 1 is 5% greater than the value before the test, it is determined that the semiconductor device 100 has failed.
Fig. 8 shows a case where a crack CR generated by a power cycle test has developed inside the lead 3 of the semiconductor device 100 of the present embodiment. When the lead 3 is bonded to the semiconductor element 1 by ultrasonic bonding, the lead 3 is plastically deformed. This refines the crystals of the bonding portion 31 of the lead 3.
The crack CR progresses inside the lead 3. In the present embodiment, crystals of the joint 31 and crystals at positions apart from the joint 31 are miniaturized. Therefore, the crack CR is suppressed from developing from the crystal of the joint 31 toward the crystal at the position apart from the joint 31. Thereby, the crack CR develops along the joint 31 where the lead 3 and the metal film 2 are joined. Further, since crystals at a position apart from the joint 31 are miniaturized, even if the crack CR progresses toward crystals at a position apart from the joint 31, the progress rate of the crack CR is small. Thus, the power cycle life is extended. That is, the lifetime of the semiconductor device 100 is prolonged.
Fig. 9 shows a case where a crack CR generated by a power cycle test has developed inside the lead 3 of the semiconductor device 101 of the present embodiment. Crack CR develops in lead 3. The crystals at the positions apart from the joint 31 have lower strength and hardness than the finer crystals of the joint 31. Accordingly, the generated crack CR progresses from the crystal of the bonding portion 31 to the crystal at the position apart from the bonding portion 31 in the lead 3. Therefore, in comparative example 1, even if the crystals of the joint 31 are miniaturized, the power cycle life is not sufficiently improved. In addition, the deformation amount of the lead wire 3 subjected to plastic deformation in comparative example 1 is larger than that of the lead wire 3 subjected to plastic deformation in embodiment 1. This is because the lead 3 is bonded to the metal film 2 in a state where the crystal of the lead 3 of the present embodiment is miniaturized, whereas the lead 3 is bonded to the metal film 2 in a state where the crystal of the lead 3 of comparative example 1 is not miniaturized.
Fig. 10 is a graph showing the relationship between the average crystal grain size of the lead 3 and the power cycle life in the case where the power cycle test is performed on the semiconductor device 100 of the present embodiment and the semiconductor device 101 of the 1 st comparative example. The vertical axis shows the power cycle life. The horizontal axis shows the average crystal grain size of the lead 3.
When the average crystal grain size of the lead 3 of the semiconductor device 100 of the present embodiment is 2.7 μm, the power cycle life is 278400 times. When the average crystal grain size of the lead 3 of the semiconductor device 100 of the present embodiment is 5 μm, the power cycle life is 104900 times.
In the case where the average crystal grain size of the lead 3 of the semiconductor device 101 of comparative example 1 was 7.1 μm, the power cycle life was 40100 times. In the case where the average crystal grain size of the lead 3 of the semiconductor device 101 of comparative example 1 was 9.3 μm, the power cycle life was 60500 times. In the case where the average crystal grain size of the lead 3 of the semiconductor device 101 of comparative example 1 was 10.6 μm, the power cycle life was 59600 times. In the case where the average crystal grain size of the lead 3 of the semiconductor device 101 of comparative example 1 was 13.9 μm, the power cycle life was 77300 times. In the case where the average crystal grain size of the lead 3 of the semiconductor device 101 of comparative example 1 was 14.9 μm, the power cycle life was 77600 times. In the case where the average crystal grain size of the lead 3 of the semiconductor device 101 of comparative example 1 was 35.8 μm, the power cycle life was 33900 times.
That is, the power cycle life of the semiconductor device 100 of the present embodiment is about 8 times longer than that of the semiconductor device 101 of comparative example 1.
As described above, the semiconductor device 100 of the present embodiment having the lead 3 with the average crystal grain size of 5 μm or less tends to be significantly different from the semiconductor device 101 of comparative example 1 having the lead 3 with the average crystal grain size of more than 7 μm, and a significant improvement in the power cycle life was confirmed.
Further, although the experimental results were shown in the case where the condition setting was performed so that the junction temperature in the on state of the semiconductor element 1 was higher than the junction temperature in the off state, even in the case where the difference between the junction temperature in the on state and the junction temperature in the off state of the semiconductor element 1 was smaller than 100 ℃, for example, in the case where the condition setting was performed so that the junction temperature in the on state of the semiconductor element 1 was higher than the junction temperature in the off state by 80 ℃, it was also confirmed that the power cycle life was significantly improved in the region where the average crystal grain size was 5 μm or less.
Next, the operation and effect of the semiconductor device 100 of the present embodiment will be described in detail by comparing the semiconductor device 100 of the present embodiment with the semiconductor device 102 (see fig. 11) of the 2 nd comparative example and the semiconductor device 103 (see fig. 12) of the 3 rd comparative example.
As shown in fig. 5, the semiconductor device 100 of the present embodiment includes a metal film 2. In addition, the average crystal grain size of the lead 3 is 5 μm or less in the entire lead 3.
In contrast, as shown in fig. 11, the semiconductor device 102 of comparative example 2 does not include the metal film 2. Further, the average crystal grain size of the lead 3 of the semiconductor device 102 of comparative example 2 is larger than 7 μm. The lead 3 of comparative example 2 contains, for example, high purity aluminum (Al). The content of aluminum (Al) in the lead 3 of comparative example 2 is, for example, 99.99 mass% or more. The lead 3 of the semiconductor device 102 of comparative example 2 has a lower hardness than the electrode 11. Accordingly, crack CR generated in semiconductor device 102 of comparative example 2 progresses inside lead 3. Specifically, crack CR progresses along joint 31 inside lead 3. Further, since the average crystal grain size of the lead 3 is large, the crack CR progresses rapidly. Therefore, the power cycle life of the semiconductor device 102 of comparative example 2 is short.
Further, with respect to the semiconductor device 100 of the present embodiment, as shown in fig. 12, the semiconductor device 103 of comparative example 3 does not include the metal film 2. The average crystal grain size of the lead 3 of the semiconductor device 103 of comparative example 3 was 5 μm or less. The lead 3 of the semiconductor device 103 of comparative example 3 has higher hardness than the electrode 11. Accordingly, crack CR generated in semiconductor device 103 of comparative example 3 progresses inside electrode 11. When the crack CR develops in the electrode 11, the chip structure of the semiconductor element 1 may be broken by the crack CR. Therefore, the power cycle life of the semiconductor device 103 of comparative example 3 is short.
As described above, the semiconductor device 100 of the present embodiment including the metal film 2 and the lead 3 having an average crystal grain size of 5 μm or less has a longer power cycle life than the semiconductor devices 102 and 103 of comparative examples 2 and 3 including no metal film 2.
Next, effects of the metal film 2 will be described.
As shown in fig. 4 and 5, when the life of the bonding portion 31 where the lead 3 is bonded to the metal film 2 is long, it is preferable that the life of other components of the semiconductor device 100 is long. Specifically, as shown in fig. 1, the 1 st bonding material 61 preferably has a long life. By improving the heat resistance of the 1 st bonding material 61, the life of the 1 st bonding material 61 is improved. By improving the heat resistance of the 1 st bonding material 61, the heat resistance of the bonding portion 31 (see fig. 5) where the semiconductor element 1 and the circuit pattern 41 are bonded is improved. Specifically, the 1 st bonding material 61 is preferably a high temperature solder. The high temperature solder is, for example, lead (Pb) based solder, tin (Sn) -antimony (Sb) based solder, gold (Au) based solder, bismuth (Bi) based solder, copper (Cu) based solder, zinc (Zn) based solder. In the case where the high-temperature solder is melted, the liquid phase temperature of the high-temperature solder is high. The liquidus temperature of the high temperature solder is 270 deg.c, for example. Therefore, as in the semiconductor device 104 of comparative example 4 shown in fig. 13, when the metal film 2 is a nickel (Ni) film formed by electroless plating and contains an amorphous state, the volume of the metal film 2 is reduced due to crystallization of the metal film 2. As a result, the metal film 2 may be cracked. As shown in fig. 13, when the metal film 2 is cracked, cracks CR may develop into the electrode 11 along with the cracking of the metal film 2. For example, when the metal film 2 contains phosphorus (P), the metal film 2 contains an amorphous state. When the content of phosphorus (P) is large, the metal film 2 has an amorphous single phase. In addition, when the content of phosphorus (P) is small, the metal phase has a crystal structure containing crystallites.
According to the semiconductor device 100 of the present embodiment, the metal film 2 may be an electroless nickel (Ni) -phosphorus (P) plating film containing no sulfur (S). In this case, the content of phosphorus (P) in the metal film 2 is 5 mass% or less. When the content of phosphorus (P) is 5 mass% or less, the metal phase has a crystalline structure. Therefore, cracking of the metal due to the amorphous state can be suppressed. Further, since sulfur (S) is not contained, segregation of sulfur (S) at the grain boundary during heat treatment can be suppressed. This can suppress grain boundary embrittlement, and therefore, cracking of the metal film 2 during heat treatment can be suppressed. As described above, the heat resistance of the metal film 2 is improved. Therefore, for example, even in the case where 270 ℃ is exceeded at the time of manufacturing the semiconductor device 100, cracking of the metal film 2 can be suppressed.
The metal film 2 may be an electroless nickel (Ni) -boron (B) plating film. In this case, the metal film 2 has a crystalline structure. The purity of nickel (Ni) contained in the metal film 2 is high. Therefore, cracking of the metal film 2 at the time of heat treatment can be suppressed.
The metal film 2 may be any of a nickel (Ni) film and a copper (Cu) film formed by electroplating. In this case, the metal film 2 has a crystalline structure. The purity of nickel (Ni) contained in the metal film 2 is high. Therefore, cracking of the metal film 2 at the time of heat treatment can be suppressed.
The metal film 2 may be any of a nickel (Ni) film, a copper (Cu) film, and a tungsten (W) film formed by any of a vapor deposition method and a sputtering method. In this case, the metal film 2 has a crystalline structure. The purity of nickel (Ni) contained in the metal film 2 is high. Therefore, cracking of the metal film 2 at the time of heat treatment can be suppressed.
According to the method of manufacturing the semiconductor device of embodiment 1, as shown in fig. 5, in the bonding step S102 (see fig. 6), the lead 3 is bonded to the metal film 2. The average crystal grain size of the entire lead 3 in the circular cross section of the lead 3 is 5 μm or less. Accordingly, the lifetime of the semiconductor device 100 is prolonged.
The semiconductor element 1 is bonded to the circuit pattern 41 by a bonding material (1 st bonding material 61) heated to 270 ℃ or higher. Therefore, a bonding material (1 st bonding material 61) having higher heat resistance can be used as a bonding material for bonding the semiconductor element 1 and the circuit pattern 41. Specifically, the semiconductor element 1 and the circuit pattern 41 may be bonded with a bonding material (1 st bonding material 61) having a melting point of 270 ℃ or higher. For example, when the content of lead (Pb) in the 1 st bonding material 61 is large, the melting point of the 1 st bonding material 61 is 270 ℃. This improves the heat resistance of the semiconductor device 100. For example, in the semiconductor device 100 in which the operation temperature is high due to the high integration of the semiconductor element 1, high heat resistance is required.
Embodiment 2.
Next, a structure of the semiconductor device 100 according to embodiment 2 will be described with reference to fig. 14. Embodiment 2 has the same structure, manufacturing method, and operational effects as embodiment 1 described above, unless otherwise specified. Therefore, the same components as those of embodiment 1 are denoted by the same reference numerals, and description thereof will not be repeated.
As shown in fig. 14, the lead 3 of the present embodiment contains iron (Fe) and aluminum (Al). The iron content of the lead 3 is 0.2 mass% or more and 2.0 mass% or less. The content of aluminum in the remainder of the lead 3 excluding iron is 99.99 mass% or more.
The element other than aluminum (Al) contained in the lead 3 is present in any of a state of being solid-dissolved in aluminum (Al) and a state of being precipitated from aluminum (Al). Therefore, in the present embodiment, iron (Fe) exists in any one of a state of being solid-dissolved in aluminum (Al) and a state of being precipitated from aluminum (Al). In a state where an element other than aluminum (Al) is solid-dissolved in aluminum (Al), the conductivity of the lead wire 3 is greatly reduced. In a state where an element other than aluminum (Al) is precipitated from aluminum (Al), the decrease in conductivity of the lead wire 3 is suppressed. In addition, the maximum solid solubility limit for aluminum (Al) differs depending on the element. Further, the rate of decrease in the conductivity of the lead 3 according to the unit solid solution amount of the element varies depending on the element.
The maximum solid solubility limit of iron (Fe) to aluminum (Al) is, for example, 0.05 mass%. Therefore, even if the content of iron (Fe) in the lead 3 is 0.2 mass% or more and 2.0 mass% or less, a large amount of iron (Fe) is precipitated. Therefore, the conductivity of the lead 3 is suppressed from decreasing due to iron (Fe).
The lead 3 of the present embodiment preferably has a conductivity of 29×10 5 S/m (50% IACS) or more. More preferably, the conductivity of the lead 3 is 32×10 5 S/m (55% IACS) or more.
The lead 3 according to the modification example of embodiment 2 contains iron (Fe), an additive element, and aluminum. The content of iron and additive elements in the lead 3 is 0.2 mass% or more and 2.0 mass% or less. The content of aluminum in the lead 3 excluding iron and additive elements is 99.99 mass% or more.
Examples of the additive elements include magnesium (Mg), silicon (Si), copper (Cu), nickel (Ni), zinc (Zn), chromium (Cr), manganese (Mn), titanium (Ti), zirconium (Zr), and tungsten (W). The additive element is an element different from iron (Fe).
Next, the operational effects of the present embodiment will be described.
According to the semiconductor device 100 of embodiment 2, as shown in fig. 14, the lead 3 contains iron (Fe) and aluminum (Al). Therefore, the average crystal grain size of aluminum (Al) can be reduced by iron (Fe). That is, the average crystal grain size of the lead 3 can be reduced. In addition, the recrystallization temperature of the lead 3 can be increased. Specifically, the recrystallization temperature of the lead 3 is 175 ℃ or higher. Thus, even if a current flows through the lead wire 3 to generate heat in the lead wire 3 during the power cycle test, crystallization and recrystallization after miniaturization can be suppressed. This can suppress coarsening of crystals after refinement. Therefore, both the promotion of the refinement of crystals and the suppression of coarsening of crystals after the refinement can be achieved.
The iron content of the lead 3 is 0.2 mass% or more and 2.0 mass% or less. The content of aluminum in the remainder of the lead 3 excluding iron is 99.99 mass% or more. Therefore, the solid solution limit of iron (Fe) to aluminum (Al) is small. This can suppress a decrease in the conductivity of the lead 3. Therefore, even when a large current flows through the semiconductor device 100, the lead 3 of the present embodiment can be used.
Next, the effect of the semiconductor device 100 according to the present embodiment will be described in more detail with reference to fig. 15 to 25. Fig. 15 is a crystal orientation chart showing evaluation of the lead 3 obtained by electron back scattering diffraction analysis (EBSD: electron Backscatter Diffraction) before and after the power cycle test. The crystal orientation diagram in fig. 15 is a crystal orientation diagram of a part of the semiconductor device 100, but for convenience of explanation, the four directions are not illustrated by the omitted lines but by the straight lines.
The effects of the semiconductor device 100 of the present embodiment will be described by comparing the lead 3 of the 1 st structure of the semiconductor device 100 of the present embodiment (see fig. 15), the lead 3 of the 2 nd structure of the semiconductor device 100 of the present embodiment (see fig. 16), and the lead 3 of the 1 st comparative example (see fig. 17).
As shown in fig. 15, the average crystal grain size of the lead 3 of the 1 st structure of the semiconductor device 100 of the present embodiment is 2.7 μm. The content of the element other than aluminum (Al) in the lead 3 of the 1 st structure was 0.4 mass%. As shown in fig. 16, the average crystal grain size of the lead 3 of the 2 nd structure of the semiconductor device 100 of the present embodiment is 5 μm. The content of the element other than aluminum (Al) in the lead 3 of the 2 nd structure was 1.5 mass%. As shown in fig. 17, the semiconductor device 101 of comparative example 1 has an average crystal grain size of 35 μm.
The power cycle test was performed on the 1 st lead 3, the 2 nd lead 3, and the 1 st lead 3 of the comparative example of the semiconductor device 100 of the present embodiment.
The power cycle life of the lead 3 of the 1 st configuration of the semiconductor device 100 of the present embodiment is 277000 times. As shown in fig. 15, before the power cycle test, the difference between the crystal grain size at the bonding interface BI of the lead 3 of the 1 st structure of the semiconductor device 100 of the present embodiment and the crystal grain size at the bonding portion 31 on the inner side than the bonding interface BI is small. Specifically, before the power cycle test, the crystal grain size at the bonding interface BI of the lead 3 of the 1 st structure of the semiconductor device 100 of embodiment 2 and the crystal grain size at the bonding portion 31 on the inner side than the bonding interface BI were each about 1 μm. As shown in fig. 18, after the power cycle test, the crystal grain size at the bonding interface BI of the lead 3 of the 1 st structure of the semiconductor device 100 of the present embodiment and the crystal grain size at the bonding portion 31 on the inner side of the bonding interface BI were each 3 μm. As shown in fig. 19 to 21, the crack CR progresses inside the lead 3 so as to extend along the joint 31 where the lead 3 and the metal film 2 are joined.
The power cycle life of the 2 nd structure of the semiconductor device 100 of the present embodiment is 353000 times. As shown in fig. 16, before the power cycle test, the difference between the crystal grain size at the bonding interface BI of the lead 3 of the 2 nd structure of the semiconductor device 100 of the present embodiment and the crystal grain size at the bonding portion 31 on the inner side than the bonding interface BI is small. Specifically, before the power cycle test, the crystal grain size at the bonding interface BI of the lead 3 of the 2 nd structure of the semiconductor device 100 of embodiment 2 and the crystal grain size at the bonding portion 31 on the inner side than the bonding interface BI are each 1 μm to 2 μm. As shown in fig. 22, after the power cycle test, the crystal grain size at the bonding interface BI of the lead 3 of the 2 nd structure of the semiconductor device 100 of embodiment 2 and the crystal grain size at the bonding portion 31 on the inner side of the bonding interface BI were each 3 μm.
As shown in fig. 17, lead 3 of semiconductor device 101 of comparative example 1 includes: a joint 31 having an average crystal grain diameter of about 1 μm before the power cycle test; and an inner region which is a position inside the lead 3 than the bonding portion 31. The internal region has a crystal grain size of 2 μm or more and 5 μm or less. As shown in fig. 20, the area of the joint 31 after the power cycle test is smaller than the area of the joint 31 after the power cycle test. The bulk crystals in the interior region have a particle size of greater than 5 μm. Therefore, the lead 3 of the semiconductor device 101 of comparative example 1 is coarsened. As shown in fig. 23, cracks CR were generated. As shown in fig. 24 and 25, the crack CR develops inside the lead so as to leave the metal film 2.
As described above, in the present disclosure, since the wire 3 having the crystal grain size of 5 μm or less is bonded to the metal film 2 harder than the wire 3 by adding the alloy element, cracks selectively develop only in the wire 3 at the time of the power cycle test, and coarsening of the crystal grain size of the wire 3 is suppressed during the test, so that a characteristic long life is obtained.
The lead 3 contains iron (Fe). Therefore, the heat resistance of the lead 3 improves. This improves the heat resistance of the semiconductor device 100.
The lead 3 contains an additive element. The strength, recrystallization temperature, corrosion resistance, and the like of the lead 3 are improved by the added element. For example, when the additive element is magnesium (Mg) or silicon (Si), the tensile strength of the lead wire 3 is improved. In addition, when the additive element is zirconium (Zr), the recrystallization temperature of the lead 3 increases. In addition, when the additive element is manganese (Mn), the corrosion resistance of the lead 3 is improved. Therefore, the strength, recrystallization temperature, corrosion resistance, and the like of the semiconductor device 100 are improved.
In the above description, the case where the content of iron or iron and the additive element in the lead 3 is 0.2 mass% or more and 2.0 mass% or less, and the content of aluminum in the remainder of the lead 3 other than iron or iron and the additive element is 99.99 mass% or more has been described. However, the same effect is obtained even if the iron content of the lead 3, or the iron and the additive element content is 0.01 mass% or more and 2.0 mass% or less, and the aluminum content of the remainder of the lead 3 other than the iron, or the iron and the additive element content is 99 mass% or more.
Embodiment 3.
The present embodiment applies the semiconductor device 100 of the above-described embodiments 1 to 2 to a power conversion device. The present disclosure is not limited to a specific power conversion device, and a case where the present disclosure is applied to a three-phase inverter will be described below as embodiment 3.
Fig. 26 is a block diagram showing the configuration of a power conversion system to which the power conversion device of the present embodiment is applied.
The power conversion system shown in fig. 26 includes a power source PW, a power conversion device 200, and a load L. The power source PW is a dc power source, and supplies dc power to the power conversion device 200. The power source PW may be constituted by various power sources, for example, a direct current system, a solar battery, and a storage battery, or may be constituted by a rectifier circuit or an AC/DC converter connected to an alternating current system. The power supply PW may be configured by a DC/DC converter that converts direct-current power output from a direct-current system into predetermined power.
The power conversion device 200 is a three-phase inverter connected between the power source PW and the load L, and converts dc power supplied from the power source PW into ac power to supply the ac power to the load L. As shown in fig. 26, the power conversion device 200 includes: a main conversion circuit 201 that converts direct-current power into alternating-current power and outputs the same; and a control circuit 202 that outputs a control signal that controls the main conversion circuit 201 to the main conversion circuit 201.
The load L is a three-phase motor driven by ac power supplied from the power conversion device 200. The load L is not limited to a specific application, and is a motor mounted on various electric devices, and is used as a motor for a hybrid car, an electric car, a rail car, an elevator, or an air conditioner, for example.
The details of the power conversion device 200 will be described below. The main conversion circuit 201 includes a switching element and a flywheel diode (not shown), and the switching element switches to convert dc power supplied from the power source PW into ac power and supplies the ac power to the load L. The main converter circuit 201 of the present embodiment has various specific circuit configurations, but the main converter circuit 201 of the present embodiment is a two-level three-phase full-bridge circuit, and may be configured of 6 switching elements and 6 flywheel diodes connected in anti-parallel to the respective switching elements. At least one of the switching elements and the flywheel diodes of the main conversion circuit 201 is a switching element or flywheel diode included in the semiconductor device 100 corresponding to the semiconductor device 100 of any one of the above-described embodiments 1 and 2. The 6 switching elements are connected in series for every 2 switching elements to constitute upper and lower arms, and each of the upper and lower arms constitutes each phase (U-phase, V-phase, W-phase) of the full bridge circuit. The load L is connected to 3 output terminals of the main conversion circuit 201, which are output terminals of the upper and lower arms.
The main conversion circuit 201 includes a driving circuit (not shown) for driving each switching element, and the driving circuit may be incorporated in the semiconductor device 100 or may be provided separately from the semiconductor device 100. The driving circuit generates a driving signal for driving the switching element of the main conversion circuit 201, and supplies the driving signal to the control electrode of the switching element of the main conversion circuit 201. Specifically, in accordance with a control signal from the control circuit 202 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the electrode 11 of each switching element. The drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element when the switching element is maintained in the on state, and is a voltage signal (off signal) equal to or lower than the threshold voltage of the switching element when the switching element is maintained in the off state.
The control circuit 202 controls the switching elements of the main conversion circuit 201 to supply desired electric power to the load L. Specifically, the time (on time) for which each switching element of the main conversion circuit 201 should be in the on state is calculated from the electric power to be supplied to the load L. For example, the main conversion circuit 201 can be controlled by PWM control in which the on time of the switching element is modulated according to the voltage to be output. Then, a control command (control signal) is output to the driving circuit provided in the main conversion circuit 201, so that an on signal is output to the switching element to be turned on at each timing, and an off signal is output to the switching element to be turned off. The drive circuit outputs an on signal or an off signal as a drive signal to the electrode 11 of each switching element in accordance with the control signal.
In the power conversion device of the present embodiment, the semiconductor device 100 of embodiments 1 to 2 is applied as the semiconductor device 100 constituting the main conversion circuit 201, and therefore, the power conversion device 200 having a long lifetime can be realized.
In the present embodiment, an example in which the present disclosure is applied to a two-level three-phase inverter has been described, but the present disclosure is not limited to this, and can be applied to various power conversion devices. In the present embodiment, the power conversion device is provided with two levels, but the power conversion device may be provided with three or more levels, and the present disclosure may be applied to a single-phase inverter when power is supplied to a single-phase load. Further, in the case of supplying electric power to a direct current load or the like, the present disclosure may also be applied to a DC/DC converter or an AC/DC converter.
The power conversion device to which the present disclosure is applied is not limited to the case where the load is an electric motor, and may be used as a power source device of an electric discharge machine, a laser machine, an induction heating cooker, or a non-contact power supply system, and may be used as a power conditioner of a solar power generation system, a power storage system, or the like, for example.
The embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive. The scope of the present disclosure is indicated by the appended claims rather than by the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein.
Description of the reference numerals
1: a semiconductor element; 2: a metal film; 3: a lead wire; 100: a semiconductor device; 20: a power conversion device; 201: a main conversion circuit; 202: a control circuit; l: a load; PW (pseudo wire): and a power supply.
Claims (12)
1. A semiconductor device, wherein the semiconductor device comprises:
a semiconductor element including an electrode;
a metal film covering the electrode of the semiconductor element; and
a lead wire bonded to the metal film,
the metal film has a higher hardness than the lead wire,
in the whole of the lead, the average crystal grain diameter of the lead on the circular section is below 5 μm.
2. The semiconductor device according to claim 1, wherein,
the lead wire comprises iron and aluminum,
the iron content of the lead is 0.01 to 2.0 mass%,
the content of aluminum in the rest of the lead except the iron is 99 mass% or more.
3. The semiconductor device according to claim 1, wherein,
the lead wire contains iron, additive elements and aluminum,
the content of the iron and the additive element in the lead is 0.01 to 2.0 mass%,
The aluminum content of the lead wire excluding the iron and the additive element is 99 mass% or more.
4. The semiconductor device according to any one of claim 1 to 3, wherein,
the metal film is any one of a nickel film and a copper film.
5. The semiconductor device according to any one of claim 1 to 3, wherein,
the metal film is an electroless nickel-phosphorus plating film containing no sulfur,
the content of phosphorus in the metal film is 5 mass% or less.
6. The semiconductor device according to any one of claim 1 to 3, wherein,
the metal film is an electroless nickel-boron plating film.
7. The semiconductor device according to any one of claim 1 to 3, wherein,
the metal film is either a nickel film or a copper film formed by electroplating.
8. The semiconductor device according to any one of claim 1 to 3, wherein,
the metal film is any one of a nickel film, a copper film, a titanium film, and a tungsten film formed by any one of a vapor deposition method and a sputtering method.
9. The semiconductor device according to any one of claims 1 to 8, wherein the semiconductor device further comprises:
a circuit pattern; and
A bonding material disposed between the circuit pattern and the semiconductor element,
the liquid phase temperature of the bonding material is 270 ℃ or higher.
10. A power conversion device, wherein the power conversion device includes:
a main conversion circuit having the semiconductor device according to any one of claims 1 to 9, and converting and outputting the input electric power; and
and a control circuit that outputs a control signal for controlling the main conversion circuit to the main conversion circuit.
11. A method for manufacturing a semiconductor device includes the steps of:
preparing a semiconductor element having an electrode, a metal film covering the electrode, and a lead wire; and
bonding the leads to the metal film,
the metal film has a higher hardness than the lead wire,
after the wire is bonded to the metal film, the wire has an average crystal grain size of 5 μm or less in a circular cross section throughout the wire.
12. The method for manufacturing a semiconductor device according to claim 11, wherein,
a circuit pattern and a bonding material are also prepared,
the semiconductor element is bonded to the circuit pattern by a bonding material heated to 270 ℃ or higher.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
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| JP2021012040 | 2021-01-28 | ||
| JP2021-012040 | 2021-01-28 | ||
| PCT/JP2022/002882 WO2022163695A1 (en) | 2021-01-28 | 2022-01-26 | Semiconductor device, power conversion device, and method for manufacturing semiconductor device |
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| CN202280010811.2A Pending CN116724384A (en) | 2021-01-28 | 2022-01-26 | Semiconductor device, power conversion device, and method for manufacturing semiconductor device |
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| JP (1) | JPWO2022163695A1 (en) |
| CN (1) | CN116724384A (en) |
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| JPS6132014U (en) | 1984-07-31 | 1986-02-26 | 凸版印刷株式会社 | Inko-style box |
| JP2000286289A (en) * | 1999-03-31 | 2000-10-13 | Fujitsu Ten Ltd | Board laminated with metal, and semiconductor device |
| JP5598592B2 (en) * | 2012-12-25 | 2014-10-01 | 三菱マテリアル株式会社 | Power module |
| WO2014175343A1 (en) * | 2013-04-25 | 2014-10-30 | 富士電機株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| CN105027272A (en) * | 2013-05-10 | 2015-11-04 | 富士电机株式会社 | Semiconductor device |
| US11562979B2 (en) * | 2018-06-27 | 2023-01-24 | Mitsubishi Electric Corporation | Power module and method of manufacturing the same, and power conversion apparatus |
| JP7126322B2 (en) * | 2018-10-10 | 2022-08-26 | 日鉄マイクロメタル株式会社 | aluminum bonding wire |
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