CN116721975A - Three-dimensional packaging structure of quantum bare chip - Google Patents
Three-dimensional packaging structure of quantum bare chip Download PDFInfo
- Publication number
- CN116721975A CN116721975A CN202310640444.0A CN202310640444A CN116721975A CN 116721975 A CN116721975 A CN 116721975A CN 202310640444 A CN202310640444 A CN 202310640444A CN 116721975 A CN116721975 A CN 116721975A
- Authority
- CN
- China
- Prior art keywords
- quantum
- bare chip
- substrate
- plate
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 100
- 239000000523 sample Substances 0.000 claims description 47
- 238000007789 sealing Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 abstract description 21
- 238000012858 packaging process Methods 0.000 abstract description 14
- 230000008569 process Effects 0.000 abstract description 6
- -1 polytetrafluoroethylene Polymers 0.000 description 23
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 23
- 239000004810 polytetrafluoroethylene Substances 0.000 description 23
- 238000010586 diagram Methods 0.000 description 12
- 238000000605 extraction Methods 0.000 description 5
- 238000003754 machining Methods 0.000 description 5
- 230000009471 action Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- XOMKZKJEJBZBJJ-UHFFFAOYSA-N 1,2-dichloro-3-phenylbenzene Chemical compound ClC1=CC=CC(C=2C=CC=CC=2)=C1Cl XOMKZKJEJBZBJJ-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 101001001429 Homo sapiens Inositol monophosphatase 1 Proteins 0.000 description 1
- 102100035679 Inositol monophosphatase 1 Human genes 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000011999 immunoperoxidase monolayer assay Methods 0.000 description 1
- GHZKGHQGPXBWSN-UHFFFAOYSA-N methyl(propan-2-yloxy)phosphinic acid Chemical compound CC(C)OP(C)(O)=O GHZKGHQGPXBWSN-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67259—Position monitoring, e.g. misposition detection or presence detection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Measuring Leads Or Probes (AREA)
- Wire Bonding (AREA)
Abstract
The application discloses a quantum bare chip three-dimensional packaging structure, which comprises a substrate, an adjusting plate, a quantum bare chip, a fixing plate, a circuit board and at least two positioning pins, wherein the substrate is arranged on the adjusting plate; the substrate, the adjusting plate, the fixing plate and the circuit board are initially positioned through the positioning pin, the groove for accommodating the quantum bare chip is formed through the substrate and the adjusting plate, then the groove is fixed through the fixing plate, the position of the quantum bare chip can be adjusted through the adjusting plate in the fixing process, so that the position of the quantum bare chip can be monitored in real time in the quantum bare chip packaging process, the corresponding adjustment is carried out, the quantum bare chip and the fixing plate are finally packaged after being fixed in position, and the aligning packaging precision of the quantum bare chip is improved.
Description
The application discloses a quantum bare chip three-dimensional packaging structure and a packaging method thereof, which are applied for the application of 2018, 07 and 27 days, the application number of which is 201810845454.7, and the patent name of which is a divisional application.
Technical Field
The application relates to the technical field of chip packaging, in particular to a quantum bare chip three-dimensional packaging structure.
Background
The quantum bare chip comprises a quantum chip, an IMPA (parameter amplifier with impedance matching) and the like, and an extremely stable working environment is required during working, so that the quantum bare chip can avoid the influences of vibration, heat radiation, electric noise, signal crosstalk, magnetic field fluctuation and the like.
In order to reduce the influence of the external environment on the quantum bare chip, the quantum bare chip is generally packaged. In the prior art, two packaging modes are mainly adopted, one is to paste the quantum bare chip at the bottom of the packaging box for packaging, and the mode has great randomness, for example, the problem that the quantum bare chip falls off due to inclination generated in the pasting process or infirm pasting is solved. The other is to clamp the quantum bare chip by a multi-layer clamp with a groove, specifically, the quantum bare chip is placed on the fixed cavity and covered with a layer of PCB (Printed Circuit Board ) which is covered with the alignment cavity, and the fixed cavity and the alignment cavity are connected by a fastening device, so that the quantum bare chip is pressed between the fixed cavity and the alignment cavity.
However, in the prior art, the packaging mode of the quantum bare chip cannot monitor the position of the quantum bare chip and correct the relative position of the quantum bare chip in real time in the packaging process, so that the packaging alignment accuracy of the quantum bare chip is lower.
Disclosure of Invention
In view of this, the application provides a three-dimensional packaging structure of a quantum bare chip, which solves the problems that in the prior art, the position of the quantum bare chip cannot be monitored and the relative position of the quantum bare chip cannot be corrected in real time in the packaging process, so that the packaging alignment precision of the quantum bare chip is lower.
In order to achieve the above purpose, the present application provides the following technical solutions:
a quantum bare chip three-dimensional packaging structure, comprising: the device comprises a substrate, an adjusting plate, a quantum bare chip, a fixing plate, a circuit board and at least two positioning pins;
the substrate is used for bearing the quantum bare chip;
the adjusting plate is positioned on the surface of the substrate bearing the quantum bare chip, and a first through hole is formed in the adjusting plate;
the quantum bare chip is positioned in the first through hole, and a datum line is arranged on the surface of the quantum bare chip, which is away from the substrate;
the fixing plate is positioned on the surface of the adjusting plate, which is away from the substrate, and is provided with a second through hole, the outline of the second through hole is identical to the shape of the datum line on the quantum bare chip, and the fixing plate is used for fixing the adjusting plate and the quantum bare chip with the substrate after the datum line of the quantum bare chip adjusted by the adjusting plate is overlapped with the outline of the second through hole;
the circuit board is positioned on one side of the fixed plate, which is away from the substrate, and is electrically connected with the quantum bare chip;
the substrate is provided with at least two positioning holes, the adjusting plate, the fixing plate and the circuit board are provided with a plurality of positioning holes which are the same as the positioning holes on the substrate in number and positions, and the positioning pins are positioned in the positioning holes.
Preferably, the quantum bare chip three-dimensional packaging structure further comprises a top plate;
the top plate is arranged between the circuit board and the fixed plate;
the top plate is provided with a plurality of third through holes, the number of the third through holes is the same as that of the connecting points on the quantum bare chip, and the positions of the third through holes are in one-to-one correspondence with the positions of the connecting points on the quantum bare chip.
Preferably, the quantum bare chip three-dimensional packaging structure further comprises: and the probes are positioned in the third through holes and are electrically connected with the quantum bare chip and the circuit board.
Preferably, one end of the probe is a telescopic top end;
the telescopic top end is contacted with the connection point of the quantum bare chip, and the other end of the probe is contacted with the bonding pad point on the circuit board.
Preferably, the probe further comprises a plurality of sealing sleeves, the number of the sealing sleeves is the same as that of the third through holes, the sealing sleeves are arranged in the third through holes of the top plate in a one-to-one correspondence mode, and one sealing sleeve surrounds one probe.
Preferably, the sealing sleeve is a polytetrafluoroethylene sleeve.
Preferably, the substrate, the adjusting plate and the fixing plate are fixedly connected through screws.
Preferably, the quantum bare chip is a quantum chip or a parametric amplifier with impedance matching.
Preferably, the circuit board is a PCB board.
The application also provides a quantum bare chip packaging method for forming the quantum bare chip three-dimensional packaging structure, which comprises the following steps:
providing a substrate, a quantum bare chip, an adjusting plate, a fixing plate, a circuit board and at least two positioning pins, wherein the adjusting plate is provided with a first through hole, the fixing plate is provided with a second through hole, and the substrate, the adjusting plate, the fixing plate and the circuit board are provided with positioning holes;
placing the adjustment plate on the substrate;
placing the quantum bare chip in a first through hole of the adjusting plate;
placing the fixing plate on the adjusting plate;
inserting the positioning pins into the positioning holes of the substrate, the adjusting plate and the fixing plate for positioning;
adjusting the adjusting plate so that a datum line on the surface of the quantum bare chip overlaps with the second through hole outline of the fixing plate;
and fixing the circuit board on one side of the fixing plate, which is away from the substrate, wherein the locating hole on the circuit board is matched with the locating pin, and the circuit board is electrically connected with the quantum bare chip.
Preferably, before the fixing the circuit board on the side of the fixing board facing away from the substrate, the method further comprises:
providing a top plate, wherein the top plate comprises a plurality of third through holes, the number of the third through holes is the same as that of the connecting points on the quantum bare chip, and the positions of the third through holes are in one-to-one correspondence with the positions of the connecting points on the quantum bare chip;
and arranging the top plate on the surface of the fixed plate, so that the third through holes are arranged in one-to-one correspondence with the connection points on the quantum bare chip.
Preferably, after the top plate is disposed on the surface of the fixing plate, the method further comprises:
providing a plurality of probes;
and inserting the probe into the third through hole, so that one end of the probe is in contact with a connection point of the quantum bare chip.
Preferably, the fixing the circuit board on the side of the fixing board away from the substrate specifically includes:
the circuit board is arranged on the surface of the top plate, which is away from the substrate;
the circuit board is initially positioned through the positioning pin;
secondly, the probes are contacted with bonding pads on the circuit board in a one-to-one correspondence manner, so that the circuit board is subjected to secondary positioning;
the circuit board is fixed on the fixing plate through screws.
According to the technical scheme, the quantum bare chip three-dimensional packaging structure comprises a substrate, an adjusting plate, a quantum bare chip, a fixing plate, a circuit board and at least two positioning pins; the substrate, the adjusting plate, the fixing plate and the circuit board are initially positioned through the positioning pin, the groove for accommodating the quantum bare chip is formed through the substrate and the adjusting plate, then the groove is fixed through the fixing plate, the position of the quantum bare chip can be adjusted through the adjusting plate in the fixing process, so that the position of the quantum bare chip can be monitored in real time in the quantum bare chip packaging process, the corresponding adjustment is carried out, the quantum bare chip and the fixing plate are finally packaged after being fixed in position, and the aligning packaging precision of the quantum bare chip is improved.
The application also provides a quantum bare chip packaging method, based on the quantum bare chip three-dimensional packaging structure, and the position of the quantum bare chip can be adjusted through the adjusting plate in the packaging process, so that the alignment packaging precision of the quantum bare chip can be improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a prior art structure for packaging a quantum bare chip using a fixed cavity and an alignment cavity;
fig. 2 is an exploded view of a three-dimensional package structure of a quantum bare chip according to an embodiment of the present application;
fig. 3 is an exploded view of a quantum bare chip three-dimensional package structure according to another embodiment of the present application;
fig. 4 is a schematic flow chart of a quantum bare chip packaging method according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a circuit board that is not electrically connected to a three-dimensional package structure for quantum chips according to an embodiment of the present application;
fig. 6 is a side view of a three-dimensional package structure for quantum chips according to an embodiment of the present application;
fig. 7 is a schematic diagram of a lead connection design of a three-dimensional package structure of a quantum chip according to an embodiment of the present application;
fig. 8 is an overall schematic diagram of a three-dimensional package structure of a quantum chip according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of a circuit board that is not electrically connected to a three-dimensional package structure of an I MPA chip according to an embodiment of the application;
fig. 10 is an alignment and fixing schematic diagram of an I MPA chip three-dimensional package structure according to an embodiment of the application.
Detailed Description
As described in the background art, in the packaging method of the quantum bare chip in the prior art, the position of the quantum bare chip cannot be monitored and the relative position of the quantum bare chip cannot be corrected in real time in the packaging process, so that the problem of low packaging alignment accuracy of the quantum bare chip exists.
The inventor finds that the reason why the above phenomenon occurs is that, as shown in fig. 1, a structure of packaging a quantum bare chip by adopting a fixing cavity and an alignment cavity in the prior art is adopted, wherein a groove 011 is arranged in the fixing cavity 01, the quantum bare chip 04 is positioned in the groove 011, the alignment cavity 02 is positioned above the fixing cavity 01, so that the quantum bare chip 04 is positioned between the fixing cavity 01 and the alignment cavity 02, the fixing cavity 01 and the alignment cavity 02 are tightly pressed by a positioning pin (not shown in the figure) so as to package the quantum bare chip, and then lead extraction of the quantum bare chip is realized by electrically connecting the circuit board 03. However, as the grooves in the fixing cavity are in a machining and forming fixed shape, and the positions of the fixing cavity, the alignment cavity and the positioning pin are determined, the positions of the quantum bare chips are also determined, and when the machining of the grooves in the fixing cavity deviates due to the process reasons or the dimensional matching of the positioning pin, the fixing cavity and the alignment cavity deviates, the relative positions of the components are displaced, so that the packaging alignment precision of the quantum bare chips is reduced.
Moreover, because the groove in the fixing cavity is a finished product formed by machining in the prior art, the quantum bare chip cannot be monitored and adjusted in position in real time in the packaging process, so that the packaging alignment precision of the final quantum bare chip cannot meet the working environment.
Based on this, the application provides a quantum bare chip three-dimensional packaging structure, comprising:
the device comprises a substrate, an adjusting plate, a quantum bare chip, a fixing plate, a circuit board and at least two positioning pins;
the substrate is used for bearing the quantum bare chip;
the adjusting plate is positioned on the surface of the substrate bearing the quantum bare chip, and a first through hole is formed in the adjusting plate;
the quantum bare chip is positioned in the first through hole, and a datum line is arranged on the surface of the quantum bare chip, which is away from the substrate;
the fixing plate is positioned on the surface of the adjusting plate, which is away from the substrate, and is provided with a second through hole, the outline of the second through hole is identical to the shape of the datum line on the quantum bare chip, and the fixing plate is used for fixing the adjusting plate and the quantum bare chip with the substrate after the datum line of the quantum bare chip adjusted by the adjusting plate is overlapped with the outline of the second through hole;
the circuit board is positioned on one side of the fixed plate, which is away from the substrate, and is electrically connected with the quantum bare chip;
the substrate is provided with at least two positioning holes, the adjusting plate, the fixing plate and the circuit board are provided with a plurality of positioning holes which are the same as the positioning holes on the substrate in number and positions, and the positioning pins are positioned in the positioning holes.
The application provides a quantum bare chip three-dimensional packaging structure which comprises a substrate, an adjusting plate, a quantum bare chip, a fixing plate, a circuit board and at least two positioning pins, wherein the adjusting plate is arranged on the substrate; the substrate, the adjusting plate, the fixing plate and the circuit board are initially positioned through the positioning pin, the groove for accommodating the quantum bare chip is formed through the substrate and the adjusting plate, then the groove is fixed through the fixing plate, the position of the quantum bare chip can be adjusted through the adjusting plate in the fixing process, so that the position of the quantum bare chip can be monitored in real time in the quantum bare chip packaging process, the corresponding adjustment is carried out, the quantum bare chip and the fixing plate are finally packaged after being fixed in position, and the aligning packaging precision of the quantum bare chip is improved.
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Referring to fig. 2, fig. 2 is an exploded view of a three-dimensional package structure of a quantum bare chip according to an embodiment of the present application, where the three-dimensional package structure of a quantum bare chip includes: a substrate 1, an adjusting plate 2, a quantum bare chip 3, a fixing plate 4, a circuit board 5 and at least two positioning pins 6.
Wherein the substrate 1 is used for bearing the quantum bare chip 3; the adjusting plate 2 is positioned on the surface of the substrate 1 bearing the quantum bare chip 3, and a first through hole 21 is arranged on the adjusting plate 2; the quantum bare chip 3 is positioned in the first through hole 3, and a datum line 31 is arranged on the surface of the quantum bare chip 3, which is away from the substrate 1; the fixing plate 4 is positioned on the surface of the adjusting plate 2, which is away from the substrate 1, a second through hole 41 is formed in the fixing plate 4, the outline of the second through hole 41 is identical to the shape of the datum line 31 on the quantum bare chip 3, and the fixing plate 4 is used for fixing the adjusting plate 2 and the quantum bare chip 3 with the substrate 1 after the datum line 31 of the quantum bare chip 3 adjusted by the adjusting plate 2 is overlapped with the outline of the second through hole 41; the circuit board 5 is positioned on one side of the fixed plate 44 away from the substrate 1, and the circuit board 5 is electrically connected with the quantum bare chip 3; the substrate 1 is provided with at least two positioning holes 11, and the adjusting plate 2, the fixing plate 4 and the circuit board 5 are provided with a plurality of positioning holes which are the same as the positioning holes on the substrate 1 in number and positions, and the positioning pins 6 are positioned in the positioning holes.
It should be noted that, the substrate 1 further includes other devices for fixedly connecting with other components, and optionally, in this embodiment, threads are used to fixedly connect the substrate with the adjusting plate, the fixing plate, the circuit board, etc., so that each plate includes a threaded hole in addition to the positioning hole for realizing fixation.
The number of positioning holes and the number of fixing holes such as threaded holes are not limited in the present embodiment, and are all within the scope of the present application as long as positioning and fixing of each component can be achieved. In this embodiment, the substrate is provided with 2 positioning holes 11 and 4 screw holes 12.
The adjusting plate 2 adopts a through hole structure, so that after the adjusting plate 2 is placed on the substrate 1, the first through hole 21 on the adjusting plate 2 and the surface of the substrate 1 form a groove, and the groove is used for accommodating the quantum bare chip 3.
It should be noted that, in this embodiment, the shape of the sidewall of the first via hole 21 is not limited, alternatively, the shape of the groove is consistent with the outline shape of the quantum bare chip 3, and the size of the groove is larger than the actual size of the quantum bare chip 3, so that after the quantum bare chip 3 is placed in the groove, the position of the quantum bare chip 3 can be moved and adjusted by moving the position of the adjusting plate 2.
It should be noted that, since the position of the adjusting plate 2 can be moved relative to the substrate 1, and the positioning pins 6 pass through the positioning holes of all the components to perform positioning, the positioning holes on the adjusting plate 2 should be configured such that the adjusting plate 2 can be moved even if the positioning pins are inserted, and the size of the 2 positioning holes 22 on the adjusting plate 2 is larger relative to the size of the two positioning holes 11 on the substrate 1 in this embodiment, so that the movement of the adjusting plate 2 is facilitated. Similarly, since the fixing plate 4 and the substrate 1 need to be fixed by screws through the adjusting plate 2, and the adjusting plate 2 is only used for adjusting the quantum bare chip 3, 4 through holes larger than the size of the threaded hole 12 on the substrate 1 are further formed in the adjusting plate 2.
In this embodiment, the fixing plate 4 also adopts a through hole structure, and the fixing plate 4 is firstly provided with a second through hole 41 for aligning with the quantum bare chip, and secondly, the fixing plate 4 also needs to be positioned by using a positioning pin and clamps and fixes the adjusting plate 2 with the substrate 1, so that the fixing plate 4 is also provided with a positioning hole 42 with the same position and size as those of the positioning hole on the substrate 1, and 4 threaded holes 43 with the same position and size as those of the threaded hole 12 on the substrate 1.
The packaging process of the quantum bare chip 3 may be: firstly, placing an adjusting plate 2 on a substrate 1; the quantum bare chip 3 is placed in a groove formed by the first through hole 21 of the adjusting plate 2 and the substrate 1; placing a fixing plate 4 on the surface of the adjustment plate 2 facing away from the substrate 1; the positioning holes of the fixing plate 4, the adjusting plate 2 and the substrate 1 are aligned by the positioning pins 6 to realize preliminary positioning.
And then, the position of the adjusting plate 2 is moved to drive the quantum bare chip 3 to move, the reference line 31 on the quantum bare chip 3 is aligned with the outline of the second through hole 41 on the fixing plate 4 through microscopic observation with scales, the alignment precision is observed in real time, and after the alignment precision is reached, the fixing plate 4 is fixedly connected with the substrate 1 through screws, so that the packaging of the quantum bare chip 3 is realized.
In practical application, after the quantum bare chip 3 is preliminarily packaged, electrical functions on the quantum bare chip 3 are led out to an external circuit, so that the quantum bare chip three-dimensional packaging structure provided in the embodiment further comprises a circuit board 5, wherein the circuit board 5 also comprises a positioning hole 51 and a threaded hole 52, the position and the size of the positioning hole 51 are consistent with those of the positioning hole 11 on the substrate 1, the circuit board 5 is positioned through the positioning pin 6 and the positioning hole 51, and then the quantum bare chip 3 is electrically connected with a bonding pad on the circuit board 5 through a gold wire or other electrical connection structures, so that the electrical leading-out of the quantum bare chip is realized.
That is, in the quantum bare chip packaging structure provided by the embodiment of the application, the accurate alignment of the datum line on the quantum bare chip and the second via hole contour line of the fixing plate can be realized by moving and accommodating the quantum bare chip adjusting plate under a microscope in the fixing packaging process, the alignment precision can be observed in real time, and after the required precision value is reached, the substrate, the adjusting plate and the fixing plate are connected and fixed, so that the position of the quantum bare chip is fixed, and the second via hole contour line of the fixing plate is aligned with the datum line on the quantum bare chip.
It should be noted that, in the embodiment of the application, the specific mode of line extraction of the quantum bare chip is not limited, and for the case that the quantum bare chip is a quantum chip, bonding wires can be used to connect bonding pads on the quantum bare chip to a circuit board through quantum wires and then to be extracted outside a packaging box, when the number of bonding wires used is increased along with the increase of quantum bits, but when the number of bonding wires is too large, the probability of mutual crosstalk between the bonding wires is increased, which leads to the performance deterioration of the quantum bare chip and even some functions can not be realized, so that the line extraction mode can not be applied to the quantum chip integrated on a large scale; for the I MPA, a binding wire process is generally used in the prior art to connect an amplifying circuit from a bonding pad of a quantum bare chip to a microstrip line of a circuit board and then led out of a packaging outer box, but an impedance strip line manufactured by the circuit board can bring more uncontrollable influence due to the floating index of an impedance transformation line caused by the processing precision of the circuit board.
Therefore, another embodiment of the present application provides a quantum bare chip three-dimensional package structure, including a substrate, an adjusting plate, a quantum bare chip, a fixing plate, a circuit board and at least two positioning pins, and in addition, unlike the above embodiment, the quantum bare chip three-dimensional package structure provided in the present embodiment further includes a top plate, please refer to fig. 3, fig. 3 is an exploded view of the quantum bare chip three-dimensional package structure provided in another embodiment of the present application; wherein, roof 7 sets up between circuit board 5 and fixed plate 4, is provided with a plurality of third through-holes 71 on the roof 7, and the number of third through-holes 71 is the same with the number of tie points on the quantum bare chip 3, and the position of third through-holes 71 and the position one-to-one setting of tie point on the quantum bare chip 3.
In the present embodiment, the number of third through holes 71 is not limited, and the number of third through holes is the same as the number of connection points on the quantum bare chip 3, that is, the number of connection points on the quantum bare chip determines the number of third through holes on the top plate.
In this embodiment, the electrical connection between the circuit board 5 and the quantum bare chip 3 is achieved through the third through hole 71 on the top plate 7 and the second through hole 41 on the fixing plate 4.
The circuit board 5 and the quantum bare chip 3 may be electrically connected through gold wires, or may be electrically connected through other connection structures, which is not limited in this embodiment. In order to align the quantum bare chip 3 and the circuit board 5, the present embodiment optionally further includes a plurality of probes 8, where the probes 8 are located in the third through holes 71 and electrically connect the quantum bare chip 3 and the circuit board 5.
The specific material and structure of the probe are not limited in this embodiment, and alternatively, the probe may be a high-frequency probe pogo-pin.
In this embodiment, one end of the probe is a retractable top, the retractable top of the probe 8 in this embodiment is in contact with the connection point of the quantum bare chip 3, and the other end of the probe 8 is in point contact with the bonding pad on the circuit board 5. The quantum bare chip 3 and the circuit board 5 are electrically connected together only by the two end points of the probe 8 contacting the quantum bare chip 3 and the circuit board 5. Finally, the circuit board 5 and the top plate 7 are fixedly connected together by screws. In this embodiment, the top plate 7 is also provided with positioning holes having the same size as the positioning holes of the substrate 1 for positioning with other components.
In this embodiment, in order to enable the probe 8 to be stably disposed in the third through hole 71, the quantum bare chip three-dimensional packaging structure may further include a plurality of sealing sleeves 9, the number of the sealing sleeves 9 is the same as that of the third through hole 71, and the sealing sleeves 9 are disposed in the third through hole 71 of the top plate 7 in a one-to-one correspondence manner, and one sealing sleeve 9 surrounds one probe 8.
In this embodiment, the specific material of the sealing sleeve is not limited, and optionally, the sealing sleeve 9 is a polytetrafluoroethylene sleeve. In this embodiment, the polytetrafluoroethylene sleeve 9 and the probe 8 form a coaxial structure.
In the prior art, the connection of the quantum bare chip and the circuit board is realized by a coaxial structure, the alignment of the quantum bare chip and the circuit board is realized by matching with a locating pin, and the wiring extraction scheme is realized, but the accuracy of locating is determined by the processing accuracy of the locating pin, and the locating accuracy of the coaxial structure cannot be checked after the packaging process and the packaging are finished, so that the wiring extraction stability cannot be ensured. In the embodiment of the application, the position of the quantum bare chip can be adjusted by adjusting the adjusting plate 2, so that the probe in the coaxial structure can be precisely aligned with the bonding pads on the quantum bare chip 3 and the circuit board 5, and the electrical connection is realized.
Specifically, in the packaging process of the quantum bare chip in this embodiment, reference may be made to part of the steps in the above embodiment, for example, placing the adjusting plate on the substrate, placing the quantum bare chip in a groove formed by the adjusting plate and the substrate, and then setting the fixing plate, adjusting the adjusting plate to fix the fixing plate and the quantum bare chip, and fixing the fixing plate and the substrate by using screws.
After the fixing plate and the substrate fix the adjusting plate and the quantum bare chip, a polytetrafluoroethylene sleeve with the diameter equivalent to that of a third through hole on the top plate is plugged into the third through hole on the top plate, one end of the polytetrafluoroethylene sleeve is connected with a connecting point on the quantum bare chip, the other end of the polytetrafluoroethylene sleeve props against the circuit board, then one telescopic end of the probe is inserted into the polytetrafluoroethylene sleeve, one end of the probe is contacted with the connecting point on the quantum bare chip, one non-telescopic end of the probe extends out of the polytetrafluoroethylene sleeve for a certain distance, then the circuit board is placed on the top plate, one non-telescopic end of the probe is contacted with the circuit board, and finally the probe is fixed by screws, so that the alignment connection between the quantum bare chip and the circuit board is realized. In this embodiment, specific materials and structures of the circuit board are not limited, and optionally, the circuit board is a PCB board.
It should be noted that, in this embodiment, the position of the probe is fixed by the top plate, so that the circuit board and the quantum bare chip are aligned, and due to the limitation of the top plate, the position of the probe is not dislocated or moved, so in this embodiment, the connection point between the probe and the quantum bare chip and the connection point between the probe and the bonding pad on the circuit board can be electrically connected only by contact, and no welding is required, so that the packaging operation is convenient and simple.
In the embodiment, the top plate, the polytetrafluoroethylene and the probe are additionally arranged, so that good alignment and electrical connection can be formed between the circuit board and the quantum bare chip. Through the movement of the adjusting plate, the connection point of the probe on the top plate and the quantum bare chip forms good alignment, in addition, the coaxial connection structure (the structure consisting of the polytetrafluoroethylene sleeve and the probe) can determine the relative position of the circuit board, and the connection point on the circuit board adopts a Pad (bonding Pad) form, so that the precise alignment connection can be realized with the connection point on the quantum bare chip, and the operation is more convenient and simpler.
Based on the quantum bare chip provided in the foregoing embodiment, the embodiment of the present application further provides a method for packaging a quantum bare chip, as shown in fig. 4, which is a schematic flow chart of the method for packaging a quantum bare chip provided in the embodiment of the present application, where the method for packaging a quantum bare chip includes:
s101: providing a substrate, a quantum bare chip, an adjusting plate, a fixing plate, a circuit board and at least two positioning pins, wherein the adjusting plate is provided with a first through hole, the fixing plate is provided with a second through hole, and the substrate, the adjusting plate, the fixing plate and the circuit board are provided with positioning holes;
s102: placing the adjustment plate on the substrate;
s103: placing the quantum bare chip in a first through hole of the adjusting plate;
s104: placing the fixing plate on the adjusting plate;
s105: inserting the positioning pins into the positioning holes of the substrate, the adjusting plate and the fixing plate for positioning;
s106: adjusting the adjusting plate so that a datum line on the surface of the quantum bare chip overlaps with the second through hole outline of the fixing plate;
s107: and fixing the circuit board on one side of the fixing plate, which is away from the substrate, wherein the locating hole on the circuit board is matched with the locating pin, and the circuit board is electrically connected with the quantum bare chip.
It should be noted that, if the top plate and the coaxial connection structure (including the structure of the sealing sleeve and the probe) are adopted to realize the electrical connection between the quantum bare chip and the circuit board, the embodiment further includes, before fixing the circuit board on the side of the fixing plate away from the substrate:
providing a top plate, wherein the top plate comprises a plurality of third through holes, the number of the third through holes is the same as that of the connecting points on the quantum bare chip, and the positions of the third through holes are in one-to-one correspondence with the positions of the connecting points on the quantum bare chip;
and arranging the top plate on the surface of the fixed plate, so that the third through holes are arranged in one-to-one correspondence with the connection points on the quantum bare chip.
After the top plate is arranged on the surface of the fixed plate, the method further comprises:
providing a plurality of probes;
and inserting the probe into the third through hole, so that one end of the probe is in contact with a connection point of the quantum bare chip.
Correspondingly, in this embodiment, the circuit board is fixed on a side of the fixing board facing away from the substrate, specifically:
the circuit board is arranged on the surface of the top plate, which is away from the substrate;
the circuit board is initially positioned through the positioning pin;
secondly, the probes are contacted with bonding pads on the circuit board in a one-to-one correspondence manner, so that the circuit board is subjected to secondary positioning;
the circuit board is fixed on the fixing plate through screws.
In order to clearly explain the packaging method of the quantum bare chip provided in the embodiment, a three-dimensional packaging structure of the quantum chip including a top plate, a polytetrafluoroethylene sleeve and a probe is taken as an example, and the detailed description is given with reference to the accompanying drawings.
Fig. 5 and fig. 6 show a schematic structural diagram of a quantum chip three-dimensional package structure without electrical connection to a circuit board according to an embodiment of the present application; FIG. 6 is a side view of a quantum chip three-dimensional package structure; the quantum chip packaging structure comprises: a substrate 1, an adjusting plate 2, a quantum bare chip (inside the package structure, not shown in the drawing), a fixing plate 4, a circuit board (not shown in the drawing), and at least two positioning pins 6.
As shown in fig. 7, the outline size of the groove formed after the substrate 1 and the adjusting plate 2 are tightly combined is larger than the size of the quantum bare chip 3, the adjusting plate 2 is placed on the substrate 1 through the positioning pin 6, the quantum bare chip 3 is placed in the groove formed by tightly combining the substrate 1 and the adjusting plate 2, then the fixing plate 4 is placed above the adjusting plate 2, the adjusting plate 2 is moved under a microscope until the position of the quantum bare chip 3 is determined, and then the quantum bare chip 3 is screwed and fixed by a screw.
Fig. 7 is a schematic diagram of a lead connection design of a three-dimensional package structure for a quantum chip according to an embodiment of the present application. The top plate 7 and the PCB board 5 are connected by a coaxial structure (dielectric/teflon sleeve 9, inner conductor/pogo-pin 8). After the quantum bare chip 3 is fixed, the polytetrafluoroethylene sleeve 9 is plugged into the through hole of the top plate 7, one end of the polytetrafluoroethylene sleeve 9 is propped against the quantum bare chip, and the other end is flush with the plane of the top plate 7. The retractable end of pogo-pin8 is then inserted into the polytetrafluoroethylene sleeve such that one end of pogo-pin7 is in contact with the quantum-bare chip (not shown), i.e., with the connection point on the quantum-bare chip. The other end extends out of the polytetrafluoroethylene sleeve 9 by a distance. The PCB board 5 is then placed on the top plate 7 such that one end of the pogo-pin8 contacts the pad on the PCB board 5, and then the PCB board 5 is fastened over the top plate 7, thus achieving an aligned connection of the quantum bare chip and the PCB.
Fig. 8 is an overall schematic diagram of a three-dimensional package structure of a quantum chip provided by the embodiment of the application, wherein the three-dimensional package structure of the quantum chip comprises a substrate 1, an adjusting plate 2, a fixing plate 4, a top plate 7, a PCB (printed circuit board) 5, a coaxial structure (polytetrafluoroethylene sleeve 9/pogo-pin 8), a quantum bare chip 3, a connection point 32 on the quantum bare chip, a through hole on the top plate 7 and a positioning pin 6.
In the quantum chip three-dimensional packaging structure provided by the embodiment of the application, in the design process, the outline dimension of the quantum bare chip is firstly determined, and then the frame-type dimensions of the slotted bottoms of the adjusting plate and the fixing plate are determined according to the outline dimension. And the machining precision of the frame-shaped bottom of the groove of the fixing plate is A, and then the position of the quantum bare chip in the groove is determined according to the reference pattern on the quantum bare chip. The quantum bare chip three-dimensional packaging structure provided by the application can be assembled according to the following steps:
1. placing the quantum bare chip 3 in parallel in a groove formed by the substrate 1 and the adjusting plate 2;
2. placing a fixing plate 4 above the quantum bare chip 3 to cover a reference pattern area of the quantum bare chip 3;
3. moving the adjusting plate 2 back and forth and left and right under a microscope with scales (the resolution is C) until the reference pattern on the quantum bare chip is overlapped with the slotted bottom frame of the fixing plate 4, wherein the alignment error between the slotted bottom frame of the fixing plate 4 and the reference pattern on the quantum bare chip is B, and then fixing the component, so that the alignment accuracy is within the range of A+B;
4. the polytetrafluoroethylene sleeve 9 (the machining precision is set as C) is plugged into the through hole of the top plate 7, so that one end of the polytetrafluoroethylene sleeve 9 is propped against the quantum bare chip, the other end of the polytetrafluoroethylene sleeve is flush with the plane of the through hole of the top plate 7, and if the polytetrafluoroethylene sleeve extends out of the plane of the through hole of the top plate 7, a cutter can be used for transversely cutting along the plane of the through hole of the top plate 7 to flush the polytetrafluoroethylene sleeve;
5. the pogo-pi n8 is plugged into a sleeve hole of the polytetrafluoroethylene sleeve 9, one end of the pogo-pi n is contacted with the quantum bare chip, and the other end of the pogo-pi n extends out of the polytetrafluoroethylene sleeve, so that the alignment precision of the connection point on the inner conductor and the quantum bare chip is controlled within the range of A+B+C;
6. and placing the PCB 5 above the assembly, and enabling the non-telescopic end of the pogo-pi n8 to be contacted with the pad of the PCB 5, so that the alignment connection of the quantum bare chip and the three-dimensional packaging box is completed.
According to the quantum bare chip packaging method, based on the quantum bare chip three-dimensional packaging structure, the position of the quantum bare chip can be adjusted through the adjusting plate in the packaging process, so that the alignment packaging precision of the quantum bare chip can be improved. And the coaxial connection structure is adopted, so that the alignment precision of the connection points on the circuit board and the quantum bare chip is relatively improved, and the alignment packaging precision of the quantum bare chip is further improved.
The embodiment of the application also provides an I MPA chip three-dimensional packaging structure, and the I MPA chip three-dimensional packaging structure is similar to the quantum chip three-dimensional packaging structure, and the packaging method is similar to the packaging method, and the I MPA chip three-dimensional packaging structure is mainly different from the coaxial connection structure through holes (namely third through holes) in the top plate.
Fig. 9 is a schematic structural diagram of a circuit board that is not electrically connected to a three-dimensional package structure of an I MPA chip according to an embodiment of the application; the fixing structure includes a substrate 10, an adjusting plate 20, a fixing plate 30 and a top plate 40, which are not electrically connected to the circuit board in this embodiment. The top plate 40 includes two positioning holes 401, four threaded holes 402, and two third through holes 403.
Fig. 10 is an alignment and fixing schematic diagram of an I MPA chip three-dimensional package structure according to an embodiment of the application; the fixing plate 30, the adjustment plate 20, and the substrate 10 are fixed by the positioning pins 60.
The lead connection of the three-dimensional package structure of the I MPA chip provided by the embodiment of the application may be referred to fig. 7, the overall structure schematic diagram may be referred to fig. 8, and after the lead connection is implemented, a circuit board is connected. The specific packaging process of the three-dimensional packaging structure of the I MPA chip provided in this embodiment may refer to the description in the above embodiment, which is not described in detail in this embodiment.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or apparatus that comprises such element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A quantum bare chip three-dimensional packaging structure for packaging of a quantum bare chip, comprising: a substrate, an adjusting plate and a fixing plate;
the substrate is used for bearing the quantum bare chip;
the adjusting plate is positioned on the surface of the substrate for bearing the quantum bare chip, a first through hole is formed in the adjusting plate, and a groove for accommodating the quantum bare chip is formed by the first through hole and the substrate;
the quantum bare chip is positioned in the groove, and a datum line is arranged on the surface of the quantum bare chip, which is away from the substrate;
the fixing plate is located the surface that the adjusting plate deviates from the substrate, be provided with the second through-hole on the fixing plate, the profile of second through-hole is the same with the datum line shape on the quantum bare chip, the fixing plate is used for adjusting the adjusting plate the datum line of quantum bare chip with the profile of second through-hole overlaps the back, with the substrate will the quantum bare chip is fixed.
2. The structure of claim 1, further comprising a circuit board located on a side of the fixed plate facing away from the substrate, the circuit board being electrically connected to the quantum bare chip.
3. The structure of claim 2, further comprising a probe electrically connecting the circuit board and the quantum bare chip.
4. The structure of claim 3, further comprising a top plate; the top plate is arranged between the circuit board and the fixed plate; and a third through hole for accommodating the probe is formed in the top plate.
5. The structure of claim 4, wherein the probes and the third through holes are in one-to-one correspondence.
6. The structure of claim 4, wherein a sealing sleeve is provided on the probe accommodated in the third through hole, the sealing sleeve surrounding the probe.
7. The structure of any one of claims 3-6, wherein one end of the probe is a telescoping tip;
the telescopic top end is contacted with the connection point of the quantum bare chip, and the other end of the probe is contacted with the bonding pad point on the circuit board.
8. The structure according to any one of claims 1 to 6, wherein the substrate has at least two positioning holes, the adjustment plate and the fixing plate each have a plurality of positioning holes having the same number and positions as those of the positioning holes on the substrate, and positioning pins are provided in the positioning holes.
9. The structure of claim 7, wherein the substrate has at least two positioning holes, and the adjustment plate, the fixing plate and the circuit board each have a plurality of positioning holes having the same number and positions as the positioning holes on the substrate, and the positioning holes are provided with positioning pins.
10. The structure of claim 1, wherein the quantum bare chip is a quantum chip or a parametric amplifier with impedance matching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310640444.0A CN116721975A (en) | 2018-07-27 | 2018-07-27 | Three-dimensional packaging structure of quantum bare chip |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310640444.0A CN116721975A (en) | 2018-07-27 | 2018-07-27 | Three-dimensional packaging structure of quantum bare chip |
| CN201810845454.7A CN108735678B (en) | 2018-07-27 | 2018-07-27 | Quantum bare chip three-dimensional packaging structure and packaging method thereof |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810845454.7A Division CN108735678B (en) | 2018-07-27 | 2018-07-27 | Quantum bare chip three-dimensional packaging structure and packaging method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116721975A true CN116721975A (en) | 2023-09-08 |
Family
ID=63941978
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310640444.0A Pending CN116721975A (en) | 2018-07-27 | 2018-07-27 | Three-dimensional packaging structure of quantum bare chip |
| CN201810845454.7A Active CN108735678B (en) | 2018-07-27 | 2018-07-27 | Quantum bare chip three-dimensional packaging structure and packaging method thereof |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810845454.7A Active CN108735678B (en) | 2018-07-27 | 2018-07-27 | Quantum bare chip three-dimensional packaging structure and packaging method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN116721975A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109509717B (en) * | 2018-12-19 | 2024-06-14 | 本源量子计算科技（合肥）股份有限公司 | Quantum chip three-dimensional packaging device and packaging method |
| CN110446368A (en) * | 2019-07-23 | 2019-11-12 | 中国科学技术大学 | Bonding structure, bonding method and the Package boxes comprising the bonding structure |
| CN110473794A (en) * | 2019-07-23 | 2019-11-19 | 中国科学技术大学 | Expansible quantum chip package box structure and preparation method thereof |
| CN110446369A (en) * | 2019-07-23 | 2019-11-12 | 中国科学技术大学 | Bonding structure, bonding method and the Package boxes comprising the bonding structure |
| CN110524889A (en) * | 2019-08-08 | 2019-12-03 | 广州明森合兴科技有限公司 | A kind of positioning system of contactless smart card manufacturing equipment |
| CN110524888A (en) * | 2019-08-08 | 2019-12-03 | 广州明森合兴科技有限公司 | A kind of contactless smart card manufacturing equipment |
| CN110524890A (en) * | 2019-08-08 | 2019-12-03 | 广州明森合兴科技有限公司 | A kind of locating platform for contactless smart card production equipment |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3726318B2 (en) * | 1995-08-22 | 2005-12-14 | 株式会社日立製作所 | Chip size package, manufacturing method thereof, and second level packaging |
| SG95651A1 (en) * | 2001-05-21 | 2003-04-23 | Micron Technology Inc | Method for encapsulating intermediate conductive elements connecting a semiconductor die to a substrate and semiconductor devices so packaged |
| JP2003209202A (en) * | 2002-01-11 | 2003-07-25 | Texas Instr Japan Ltd | Semiconductor device or mounting method of the same |
| JP4103549B2 (en) * | 2002-10-31 | 2008-06-18 | 株式会社デンソー | Multilayer wiring board manufacturing method and multilayer wiring board |
| JP4546990B2 (en) * | 2007-06-21 | 2010-09-22 | 日本特殊陶業株式会社 | Ceramic package and manufacturing method thereof |
| CN207353227U (en) * | 2017-12-28 | 2018-05-11 | 合肥本源量子计算科技有限责任公司 | A kind of quantum chip packaging device |
| CN208478315U (en) * | 2018-07-27 | 2019-02-05 | 合肥本源量子计算科技有限责任公司 | A kind of quantum bare chip stereo encapsulation structure |
-
2018
- 2018-07-27 CN CN202310640444.0A patent/CN116721975A/en active Pending
- 2018-07-27 CN CN201810845454.7A patent/CN108735678B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN108735678A (en) | 2018-11-02 |
| CN108735678B (en) | 2024-02-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108735678B (en) | Quantum bare chip three-dimensional packaging structure and packaging method thereof | |
| US8911266B2 (en) | Contact holder | |
| JP4251855B2 (en) | Manufacturing method of inspection jigs for high frequency and high speed devices | |
| US6727716B1 (en) | Probe card and probe needle for high frequency testing | |
| US4593243A (en) | Coplanar and stripline probe card apparatus | |
| US7456645B2 (en) | Inspection coaxial probe and inspection unit incorporating the same | |
| JP4535828B2 (en) | Inspection unit manufacturing method | |
| US6535006B2 (en) | Test socket and system | |
| US6399900B1 (en) | Contact structure formed over a groove | |
| JP4438601B2 (en) | Inspection unit manufacturing method | |
| JPH02237131A (en) | Apparatus and method for testing of semiconductor ic | |
| US20210005992A1 (en) | Impedance controlled metallized plastic socket | |
| US5563522A (en) | Microwave band probing apparatus | |
| KR102295761B1 (en) | Test Socket | |
| US9702906B2 (en) | Non-permanent termination structure for microprobe measurements | |
| US6498299B2 (en) | Connection structure of coaxial cable to electric circuit substrate | |
| US11156638B2 (en) | Contactors with signal pins, ground pins, and short ground pins | |
| JPH07122602A (en) | High frequency probe and probe circuit | |
| JPH0739231Y2 (en) | Ultra high speed probe board | |
| WO2000004394A1 (en) | Socket for device measurement, and method of measuring device | |
| JPH07191058A (en) | Device for testing intrinsic position of broad-band microwave | |
| KR102184792B1 (en) | Apparatus for inspecting electronic devices using busing | |
| JP2006170700A (en) | Probe calibration jig, probe card with probe calibration jig and semiconductor wafer measurement device | |
| JP2004170181A (en) | Checking tool for high-frequency/high-speed device | |
| JPS6171367A (en) | Fixed probe card |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |