CN116705760A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN116705760A
CN116705760A CN202211699822.4A CN202211699822A CN116705760A CN 116705760 A CN116705760 A CN 116705760A CN 202211699822 A CN202211699822 A CN 202211699822A CN 116705760 A CN116705760 A CN 116705760A
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China
Prior art keywords
insulating film
film
region
conductive film
contact hole
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CN202211699822.4A
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Inventor
工藤章太郎
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication of CN116705760A publication Critical patent/CN116705760A/zh
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Abstract

本公开的各种实施例涉及一种半导体器件及其制造方法。一种半导体器件，包括半导体衬底(SUB)上的绝缘层(IFL)、该绝缘层(IFL)上的导电膜(PL)、覆盖该导电膜(PL)的层间绝缘膜(IL)、该层间绝缘膜(IL)、该导电膜(PL)和该绝缘层(IFL)中的接触孔(CH1)、以及嵌入该接触孔(CH1)中的插塞(PG1)。该层间绝缘膜(IL)的侧表面与该导电膜(PL)的侧表面分离以暴露该导电膜(PL)的上表面的一部分，并且该绝缘层(IFL)的该侧表面与该导电膜(PL)的该侧表面分离以暴露该导电膜(PL)的下表面的一部分。从该导电膜(PL)的该下表面到该接触孔(CH1)的该底部的距离(L1)比从该导电膜(PL)的该侧表面到该层间绝缘膜(IL)的该侧表面的距离(L2)长。

Description

半导体器件及其制造方法
相关申请的交叉引用
于2022年3月2日提交的日本专利申请第2022-032023号的公开内容，包括说明书、附图和摘要，通过引用整体并入本文。
技术领域
本发明涉及一种半导体器件及其制造方法，并且更特别地，涉及一种包括形成在层间绝缘膜中的接触孔的半导体器件及其制造方法。
背景技术
作为功率器件，应用竖直沟槽栅极结构的功率MOSFET(金属氧化物半导体场效应晶体管)和IGBT(绝缘栅极双极晶体管)是已知的。包括功率器件的一些半导体器件(半导体芯片)除了其中形成主器件的单元区域之外还包括电阻区域和二极管区域。
例如，在日本未审查专利申请公开2006-324570中公开了一种包括功率MOSFET和保护二极管的半导体器件。保护二极管形成在元件隔离部分上并且覆盖有层间绝缘膜。在层间绝缘膜中形成接触孔，并且在接触孔中嵌入栅极布线和源极电极。保护二极管的一端电连接到栅极布线，保护二极管的另一端电连接到源电极。
发明内容
在下文中，将参考图27至图32描述由本申请的发明人研究的研究示例1至示例3的半导体器件。这些器件包括作为动力器件的IGBT。图27至图32示出了其中形成电阻元件的区域，作为不同于IGBT的示例性半导体元件。这里，导电膜PL构成电阻器件。
图27示出了研究示例1的半导体器件。如图27中所示，在研究示例1中，导电膜PL经由绝缘膜IF2形成在半导体衬底SUB的上表面上。绝缘膜IF2例如是氧化硅膜。导电膜PL例如是多晶硅膜，并且构成电阻器件。在半导体衬底SUB的上表面上形成层间绝缘膜IL，以便覆盖导电膜PL。层间绝缘膜IL例如是通过CVD方法形成的氧化硅膜。
在层间绝缘膜IL中形成接触孔CH1。接触孔CH1在与到达IGBT的体区域和发射极区域的接触孔相同的工艺中形成。
这里，接触孔CH1通过被蚀刻得比层间绝缘膜IL的厚度更深而形成。因此，接触孔CH1也形成在导电膜PL的一部分中。如果导电膜PL的厚度足够厚(诸如600nm)，则接触孔CH1的底部部分位于导电膜PL内部，并且接触孔CH1不会到达半导体衬底的SUB。
图28示出了研究示例2的半导体器件。在研究示例2中，该器件比研究示例1中的器件更小型化。因此，如图28中所示，通过CMP方法在层间绝缘膜IL的上表面上执行平坦化处理，以提高接触孔的加工精度。在诸如SOC(片上系统)的精细工艺的半导体器件中，使用通过在开放空间中放置虚拟图案来进一步平坦化层间绝缘膜IL的上表面的方法。另一个方面，在诸如IGBT的功率器件中，使用此类方法不是很现实，因为几乎没有空间来填充虚拟图案。
因此，在研究示例2中，导电膜PL的厚度被设置为比研究示例1的薄，并且被设置为例如250nm。因此，层间绝缘膜IL的上表面中的台阶差减小。
然而，由于导电膜PL的厚度和导电膜PL上的层间绝缘膜IL的厚度减小，所以当形成接触孔CH1时，接触孔CH1的底部部分可能穿透导电膜IF2。此外，取决于形成接触孔CH1时的蚀刻速率，接触孔CH1的底部部分到达半导体衬底的SUB，并且出现短路故障。
为了避免此类问题，可以设想通过在与到达IGBT的体区域和发射极区域的接触孔不同的制造过程中形成接触孔CH1来单独控制接触孔CH1的深度。然而，在此情况下，由于执行了掩模数量的增加和制造过程的添加，因此增加了制造成本。
图29至图32示出了研究示例3的半导体器件。在研究示例3中，如图29中所示，绝缘膜IF1形成在绝缘膜IF2下面。绝缘膜IF1例如是通过热氧化方法形成的氧化硅膜。通过在导电膜PL下面设置绝缘层IFL，该绝缘层IFL是作为绝缘膜IF1和绝缘膜IF2的层压膜，即使接触孔CH1穿透绝缘膜IF2，也可以防止接触孔CH1的底部到达半导体衬底的SUB。
在最近的工艺中，为了增加插塞和嵌入在IGBT的接触孔中的发射极区域之间的接触面积以及插塞PG1和导电膜PL之间的接触面积，在层间绝缘膜IL上执行各向同性蚀刻工艺。在此各向同性蚀刻工艺中，使用包含氢氟酸的溶液，并且选择性地蚀刻氧化硅膜。
图30示出了各向同性蚀刻工艺后的状态。通过各向同性蚀刻工艺，层间绝缘膜IL的侧表面收缩，并且导电膜PL的上表面被暴露。与此同时，由氧化硅膜制成的绝缘膜IF2和绝缘膜IF1的一部分也被退回，并且导电膜PL的下表面被暴露。
此后，如图31中所示，在接触孔CH1中形成阻挡金属膜BM，如图32中所示，在阻挡金属膜BM上形成导电膜CF以填充接触孔CH1的内部。阻挡金属膜BM和导电膜CF形成插塞PG1。阻挡金属膜BM通过CVD方法形成，并且由例如钛膜和氮化钛的层压膜形成。导电膜CF通过CVD方法形成并且由例如钨膜制成。
通过上面所描述的各向同性蚀刻工艺，在接触孔CH1中从导电膜PL的侧表面到层间绝缘膜IL的侧表面的距离变为距离L2。从导电膜PL的下表面到接触孔CH1的底部部分的距离是距离L3。通过热氧化方法形成的绝缘膜IF1的蚀刻速率略低于通过CVD方法形成的绝缘膜IF2和层间绝缘膜IL的蚀刻速率。因此，距离L3等于或短于距离L2。
如图31中所示，当距离L3短时，因为当形成阻挡金属膜BM时，在CVD方法中使用的气体没有充分供应到导电膜PL的下表面附近，所以很可能产生阻挡金属膜BM的厚度不够的部分。
当形成导电膜CF时，阻挡金属膜BM也用作晶种膜。因此，如图32中所示，在阻挡金属膜BM薄的部分，导电膜CF不太可能充分生长，并且可能在接触孔CH1中产生间隙。此外，在未形成阻挡金属膜BM的部分中，WF6气体与导电膜CF(多晶硅膜)反应，并且出现导电膜CF的一部分不存在的缺陷。此类位置在图32中示出为有缺陷的位置20并且在随后的制造步骤中容易腐蚀或变形。
为了增加距离L3，可以想到增加各向同性蚀刻工艺的持续时间，但是这也增加了距离L2并且加宽了接触孔CH1的开口宽度。因此，IGBT的接触孔的开口宽度变得太宽，使得IGBT的栅极电极暴露在IGBT的接触孔中。因此，存在IGBT的栅极电极电连接到发射极电极的问题。
本申请的主要目的是抑制上述缺陷并且提高半导体器件的可靠性。从本说明书和附图的描述中，其他目的和新颖特征将变得显而易见。
解决问题的手段
本申请中公开的典型实施例将简要描述如下。
根据实施例的半导体器件包括：
半导体衬底，具有上表面和下表面；
绝缘层，形成为从半导体衬底的上表面到半导体衬底的内部；
第一导电膜，形成在绝缘层上，
层间绝缘膜，形成在半导体衬底的上表面上以覆盖第一导电膜；
第一接触孔，形成在层间绝缘膜、第一导电膜和绝缘层中，使得第一接触孔的底部部分定位在绝缘层中；以及
第一插塞，形成为填充第一接触孔，
其中在第一接触孔中，层间绝缘膜的侧表面与第一导电膜的侧表面分离，使得第一导电膜的上表面的一部分从层间绝缘膜暴露，
其中在第一接触孔中，该绝缘层的侧表面与该第一导电膜的侧表面分离，使得该第一导电膜的下表面的一部分从该绝缘层暴露，并且
其中从第一导电膜的下表面的一部分到第一接触孔的底部部分的第一距离比从第一导电膜的侧表面到层间绝缘膜的侧表面的第二距离长。
根据实施例的制造半导体器件的方法包括：
(a)制备具有上表面和下表面的半导体衬底。
(b)在步骤(a)之后，形成从半导体衬底的上表面延伸到半导体衬底内部的第一绝缘膜；
(c)在步骤(b)之后，在第一绝缘膜上形成厚度比第一绝缘膜薄的第二绝缘膜；
(d)在步骤(c)之后，在第二绝缘膜上形成第一导电膜；
(e)在步骤(d)之后，在半导体衬底的上表面上形成层间绝缘膜，以便覆盖第一导电膜；
(f)在步骤(e)之后，在层间绝缘膜、第一导电膜、第二绝缘膜和第一绝缘膜中形成第一接触孔，使得第一接触孔的底部部分位于第一绝缘膜中，
(g)在步骤(f)之后，使层间绝缘膜、第二绝缘膜和第一绝缘膜经受各向同性蚀刻工艺，以及
(h)在步骤(g)之后，将第一插塞嵌入所述第一接触孔中，
其中通过步骤(g)中的各向同性蚀刻工艺，在第一接触孔中，层间绝缘膜的侧表面与第一导电膜的侧表面分离，使得第一导电膜的上表面的一部分从层间绝缘膜暴露，
其中通过该步骤(g)中的各向同性蚀刻工艺，在第一接触孔中，该第一绝缘膜的侧表面和该第二绝缘膜的侧表面与该第一导电膜的侧表面分离，使得该第一导电膜的下表面的一部分从该第一绝缘膜和第二绝缘膜暴露，并且
其中从第一导电膜的下表面到第一接触孔的底部部分的第一距离比从第一导电膜的侧表面到层间绝缘膜的侧表面的第二距离长。
根据实施例的制造半导体器件的方法是制造具有第一区域和不同于第一区域的第二区域的半导体器件的方法。一种制造该半导体器件的方法，包括以下步骤：
(a)制备具有上表面和下表面的半导体衬底的步骤，
(b)在步骤(a)之后，在第一区域中从高于半导体衬底的上表面的位置到半导体衬底的内部形成第一绝缘膜的步骤，
(c)在步骤(b)之后，在第二区域中的半导体衬底的上表面侧上形成沟槽的步骤，
(d)对第一绝缘膜进行各向同性蚀刻工艺以使第一绝缘膜的厚度在步骤(c)后变薄的步骤，(d)对第一绝缘膜进行各向同性蚀刻工艺，使得第一绝缘膜的厚度在步骤(c)之后变薄的步骤，
(e)在步骤(d)之后在沟槽中形成栅极绝缘膜的步骤，
(f)在步骤(e)之后，在栅极绝缘膜上形成栅极电极以填充沟槽的步骤，
(g)在步骤(f)之后，形成覆盖第一区域中的第一绝缘膜和覆盖第二区域中的栅极电极的第二绝缘膜的步骤，在步骤(f)之后，第二绝缘膜的厚度小于第一绝缘膜的厚度；
(h)在步骤(g)之后，在第一区域和第二区域中的第二绝缘膜上形成第二导电膜的步骤；
(i)在步骤(h)之后，移除第一导电膜和第二绝缘膜，使得第一导电膜和第二绝缘膜选择性地保留在第一绝缘膜上的步骤；
(j)在步骤(i)之后，在半导体衬底的上表面侧上形成第一导电类型的第一杂质区域，使得其底部部分定位在沟槽的底部部分上方的步骤，
(k)在步骤(j)之后，在第一杂质区域中形成与第一导电类型相反的第二导电类型的第二杂质区域的步骤，
(l)在步骤(k)之后，在第一区域和第二区域中的半导体衬底的上表面上形成层间绝缘膜以覆盖第一区域中的第一导电膜并且覆盖第二区域中的栅极电极、第一杂质区域和第二杂质区域的步骤，
(m)在步骤(l)之后，通过CMP方法对第一区域和第二区域中的层间绝缘膜执行平坦化处理的步骤；
(n)在步骤(m)之后，在第一区域中的层间绝缘膜、第一导电膜、第二绝缘膜和第一绝缘膜中形成第一接触孔，使得第一接触孔的底部部分位于第一绝缘膜中，并且在第二区域中的层间绝缘膜、第二杂质区域和第一杂质区域中形成第二接触孔，使得第二接触孔的底部部分位于第一杂质区域中；
(o)在步骤(n)之后，在第一接触孔中埋置第一插塞并且在第二接触孔中埋置第二插塞的步骤。
根据一个实施例，可以提高半导体器件的可靠性。
附图说明
图1是示出第一实施例的整个半导体器件的平面图。
图2是示出根据第一实施例的半导体器件的平面图。
图3是示出根据第一实施例的半导体器件的平面图。
图4是示出根据第一实施例的半导体器件的平面图。
图5是示出根据第一实施例的半导体器件的截面图。
图6是示出根据第一实施例的半导体器件的截面图。
图7是根据第一实施例的半导体器件的一部分的放大截面图。
图8是根据第一实施例的半导体器件的一部分的放大截面图。
图9是示出根据第一实施例的半导体器件的制造过程的截面图。
图10是图示图9之后的制造过程的截面图。
图11是图示图10之后的制造步骤的截面图。
图12是图示图11之后的制造步骤的截面图。
图13是图示图12之后的制造步骤的截面图。
图14是图示图13之后的制造步骤的截面图。
图15是图示图14之后的制造步骤的截面图。
图16是图示图15之后的制造步骤的截面图。
图17是图示图16之后的制造步骤的截面图。
图18是图示图17之后的制造步骤的截面图。
图19是图示图18之后的制造步骤的截面图。
图20是图示图19之后的制造步骤的截面图。
图21是图示图20之后的制造步骤的截面图。
图22是图示图21之后的制造步骤的截面图。
图23是图示图22之后的制造步骤的截面图。
图24是图示图23之后的制造步骤的截面图。
图25是图示图24之后的制造步骤的截面图。
图26是图示图25之后的制造步骤的截面图。
图27是示出根据第一研究示例的半导体器件的截面图。
图28是示出根据第二研究示例的半导体器件的截面图。
图29是示出根据第三研究示例的半导体器件的截面图。
图30是图示图29之后的制造过程的截面图。
图31是图示图30之后的制造过程的截面图。
图32是图示图31之后的制造过程的截面图。
具体实施方式
在下文中，将基于附图详细描述实施例。在用于说明实施例的所有附图中，具有相同功能的构件由相同的附图标记表示，并且省略其重复描述。在以下实施例中，除非特别必要，否则原则上将不再重复相同或类似部分的描述。
下面将参考图1至图8描述根据实施例1的半导体器件100。图1是图示作为半导体器件100的半导体芯片的平面图。
如图1中所示，器件100的大部分被发射极电极EE覆盖，并且在发射极电极EE下方形成构成IGBT的多个单元。栅极线GW形成在发射极电极EE周围。发射极电极EE的中心部分用作发射极焊盘，并且栅极布线的中心部分用作栅极焊盘。诸如布线接合或夹子(铜板)的外部连接端子连接到发射极焊盘和栅极焊盘，使得半导体器件100电连接到另一个半导体芯片、布线板等。
器件100包括区域1A至区域3A，区域1A至区域3A是彼此不同的区域。图1中的区域1A是其中形成电阻元件的电阻元件区域。电阻元件用于栅极电阻器等。图1中的区域2A是其中形成了构成IGBT的多个单元的单元区域。图1中的区域3A是其中形成有二极管元件的二极管元件区域。二极管元件用于栅极保护或温度感测等。
图2是与区域1A相对应的主要部分的平面图。图3是与区域3A相对应的主要部分的平面图。图4是与区域2A相对应的主要部分的平面图。图5是沿着图2的A-A线截取的截面图和沿着图4的B-B线截取的截面图；图6是沿着图3的C-C线截取的截面图。
如图2至图4中所示，接触孔CH1、CH2具有狭缝形状，其中在平面图中，第一方向上的开口宽度比垂直于第一方向的第二方向上的开口宽度宽。也就是说，接触孔CH1、CH2在平面图中具有矩形形状。
然而，接触孔CH1、CH2的平面形状不限于狭缝形状，并且可以是点形状，其中在第一方向上的开口宽度与在第二方向上的开口宽度相同。即，在平面图中具有矩形形状的多个接触孔CH1、CH2可以沿着第一方向布置。
在许多情况下，接触孔CH1、CH2的平面形状是其中在光刻分解之后拐角被倒圆的形状。因此，最终，接触孔CH1、CH2在平面图中具有矩形的拐角被倒圆或圆形的形状。
除了在导电膜PL上形成p型阳极区域PLP和n型阴极区域PLN之外，图3和图6中示出的二极管元件的主要特征与图2和图5中示出的电阻器元件的主要特征基本上相同。因此，下面将描述区域1A中的电阻元件和区域2A中的IGBT中的单元。
如图5和6所示，半导体器件100包括具有低浓度n型漂移区域NV的半导体板SUB。这里，n型半导体衬底SUB本身构成漂移区域NV。注意到，漂移区域NV可以是n型硅衬底和通过外延生长方法将磷(P)引入到硅衬底上而生长的半导体层的叠层。在本申请中，此类叠层也被描述为半导体衬底SUB。
在半导体衬底SUB的下表面上，n型场停止区域(杂质区域)NS形成在半导体衬底SUB上。设置场停止区域NS以防止当IGBT停止时从SUB的上表面上的pn结延伸的耗尽层到达p型集电极区域PC。
在半导体衬底SUB的下表面上，p型集电极区域(杂质区域)PC形成在半导体衬底SUB上。集电极区域PC位于场停止区域NS的下面。
集电极CE形成在半导体衬底SUB的下表面下方。集电极CE电连接到集电极区域PC并且向集电极区域PC提供集电极电势。集电极CE由金属膜(诸如AlSi膜、Ti膜、NiV膜和Au膜)组成。
下面将描述区域1A的配置。在器件100中，形成在区域1A上的导电膜PL用作电阻元件。
如图5中所示，在半导体衬底SUB的上表面上的半导体衬底SUB中形成p型阱区PW。阱区域PW在与区域1A的浮置区域PF相同的工艺中形成，但是在物理上与浮置区域PF分离。
从半导体衬底SUB的上表面到半导体衬底SUB的内部形成绝缘层IFL。换句话说，在半导体衬底SUB中，形成绝缘层IFL，并且绝缘层IFL的下表面位于半导体衬底SUB的上表面之下。
绝缘层IFL包括绝缘膜IF1和绝缘膜IF2。绝缘膜IF1形成在半导体衬底SUB的内部并且例如是氧化硅膜。绝缘膜IF2形成在绝缘膜IF1上，并且例如是氧化硅膜。绝缘膜IF2的厚度小于绝缘膜IF1的厚度。绝缘膜IF1的厚度例如是500nm至600nm。绝缘膜IF2的厚度例如是50nm至100nm。
导电膜PL形成在绝缘层IFL上。导电膜PL例如是p型掺杂多晶硅膜。导电膜PL的厚度例如是150nm至250nm。
在半导体衬底SUB的上表面上形成层间绝缘膜IL，以便覆盖导电膜PL。层间绝缘膜IL例如是氧化硅膜。此外，层间绝缘膜IL经受平坦化处理，用于平坦化层间绝缘膜IL的上表面。因此，半导体衬底SUB的上表面上的层间绝缘膜IL的厚度例如为600nm至800nm，但是导电膜PL的上表面上的层间绝缘膜IL的厚度例如为300nm至450nm。
接触孔CH1形成在层间绝缘膜IL、导电膜PL和绝缘层IFL中。接触孔CH1的底部位于绝缘层IFL中(绝缘膜IF1中)。插件PG1被嵌入在接触孔CH1中。插塞PG1包括阻挡金属膜BM和形成在阻挡金属膜BM上的导电膜CF。阻挡金属膜BM是例如钛膜和形成在钛膜上的氮化钛膜的层压膜。导电膜CF例如是钨膜。
栅极布线GW形成在层间绝缘膜IL上。导电膜PL经由插塞PG1电连接到栅极线GW。通过由导电膜PL在栅极布线GW的中间形成电路径，导电膜PL可以用作栅极电阻器。
第一实施例的主要特征是接触孔CH1的形状以及插塞PG1和导电膜PL在接触孔CH1中彼此接触的点。
<IGBT单元的结构>下面描述区域2A的结构。这里，将示例应用竖直沟槽栅极结构的IGBT。
如图5中所示，在半导体衬底SUB的上表面上的半导体衬底SUB中形成沟槽TR。沟槽TR的深度例如为3至4微米。在沟槽TR中形成栅极绝缘膜GI。栅极电极GE形成在栅极绝缘膜GI上，以便填充沟槽TR。栅极绝缘膜GI例如是氧化硅膜，并且栅极电极GE例如是引入了n型杂质的多晶硅膜。
在半导体衬底SUB的上表面上，在一对栅极电极GE之间的半导体衬底SUB中形成空穴阻挡区域(杂质区域)NHB。p型基极区域(杂质区域)PB形成在空穴阻挡区域NHB中。n型发射极区域(杂质区域)NE形成在p型基极区域PB中。基极区域PB的底部位于沟槽TR的底部上方，并且发射极区域NE的底部位于基极区域PB的底部上方。
此外，在半导体衬底SUB的上表面上，p型浮置区域(杂质区域)PF形成在半导体衬底SUB上，而不是形成有空穴阻挡区域NHB的区域上。p型基极区域PB形成在浮置区域PF中。浮置区PF形成在比沟槽TR的底部更深的位置以便增强高击穿电压特性，并且形成为覆盖沟槽TR的底部。
层间绝缘膜IL也形成在区域2A中的半导体衬底SUB的上表面上以便覆盖栅极电极GE、发射极区域NE和基极区域PB。接触孔CH2形成在区域2A中的层间绝缘膜IL、发射极区域NE和基极区域PB中。接触孔CH2的底部位于基极区域PB中。插件PG2嵌入接触
孔CH2中。插塞PG2被配置为类似于插塞PG1，并且包括阻挡金属5膜BM和导电膜CF。
p型高浓度扩散区域(杂质区域)PR形成在接触孔CH2底部部分周围的基极区域PB中。提供高浓度扩散区PR以降低与插塞PG2的接触电阻并且防止闩锁。
在区域2A中，由于在层间绝缘膜IL上执行各向同性蚀刻工艺0以增加嵌入接触孔CH2中的插塞PG2和发射极区域NE之间的接触面积，因此层间绝缘膜IL的侧表面收缩。也就是说，在接触孔CH2中，层间绝缘膜IL的侧表面与发射极区域NE的侧表面分离，使得发射极区域NE的上表面的一部分被暴露。
在层间绝缘膜IL上形成发射极电极EE。发射极电极EE经由插5塞PG2电连接到发射极区域NE、基极区域PB和高扩散区域PR，
并且向这些区域供应发射极电势。尽管这里未图示，但是栅极互连GW经由其他插塞电连接到栅极电极GE，并且向栅极电极GE供应栅极电势。
发射极电极EE和栅极线GW由例如TiW膜和形成在TiW膜上0的铝膜形成。铝膜是发射极电极EE和栅极线GW的主要导电膜，并且比TiW膜足够厚。
如图6中所示，下面将描述区域3A的结构。在器件100中，形成在区域3A上的导电膜PL用作二极管元件。由于该结构的其余部分与1A的区域相同，因此将省略其说明。
5在图6中示出的二极管器件中，通过离子注入在导电膜PL上形成p型阳极区域PLP和n型阴极区域PLN。接触孔CH1相应地形成在阳极区域PLP和阴极区域PLN中，并且插塞PG1嵌入接触孔CH1中。尽管这里没有图示，但是发射极电极EE和栅极线GW形成在区域3A中的层间绝缘膜IL上。阳极区域PLP经由插塞PG1电连接到发射极电极EE，阴极区域PLN经由插塞PG1电连接到栅极布线GW。
<第一实施例的主要特征>下面将参考图7和图8描述第一实施例的主要特征。图7和图8是接触孔CH1外围的放大截面图。图7示出了插塞PG1没有嵌入接触孔CH1的状态。
在区域1A中，由于在与在区2A中形成接触孔CH2的步骤相同的步骤中在层间绝缘膜IL上执行各向同性蚀刻工艺，因此层间绝缘膜IL的侧表面后退(retreated)。在接触孔CH1中，层间绝缘膜IL的侧表面与导电膜PL的侧表面分离，使得导电膜PL的上表面的一部分被暴露。这些侧之间的距离L2例如是50nm至100nm。
这里，绝缘层IFL也通过上面所描述的各向同性蚀刻工艺被后退。因此，在接触孔CH1中，绝缘层IFL的侧表面(绝缘膜IF1的侧表面和绝缘膜IF2的侧表面)与导电膜PL的侧表面分离，使得导电膜PL的下表面的一部分暴露。换句话说，形成在层间绝缘膜IL中的接触孔CH1的开口宽度和形成在绝缘层IFL中的接触孔CH1的开口宽度比形成在导电膜PL中的接触孔CH1的开口宽度宽。
如稍后将描述的，在第一实施例中，预先形成接触孔CH1，使得接触孔CH1的底部在上面所描述的各向同性蚀刻工艺之前到达绝缘层IFL的内部。由于在此条件下执行上述各向同性蚀刻工艺，所以从导电膜PL的下表面到接触孔CH1的底部部分的距离L1比第三研究示例的距离L3长，并且比距离L2长。例如，L1的距离是150nm至200nm。
在研究示例3中，由于距离L3短，所以可能产生阻挡金属膜BM的厚度不足的部分。因此，在阻挡金属膜BM薄的部分中，导电膜CF难以充分生长，并且在接触孔CH1中容易产生间隙，并且存在WF6气体与导电膜CF反应，并且导电膜CF的一部分缺失的问题。
在第一实施例中，由于距离L1足够长，所以当形成阻挡金属膜BM时，在CVD方法中使用的气体被充分供应到导电膜PL的下表面附近。因此，在接触孔CH1中确保了足够厚的阻挡金属膜BM。因为当形成导电膜CF时，阻挡金属膜BM也用作晶种膜，所以导电膜CF也充分生长。因此，在第一实施例中，解决了在检查示例3中出现的各种问题，使得可以提高半导体器件的可靠性。
阻挡金属膜BM在接触孔CH1中与导电膜PL的上表面的一部分、导电膜PL的侧表面和导电膜PL的下表面的一部分接触。因此，由于可以增加插塞PG1和导电膜PL之间的接触面积，所以可以降低插塞PG1和导电膜PL之间的接触电阻率，并且可以提高插塞PG1和导电膜PL之间的粘附性。
注意到，在区域3A的二极管元件中也可以获得与区域1A的电阻元件相同的优点。
下面将参考图9至图26描述制造根据第一实施例的半导体器件100的方法。
首先，如图9中所示，制备具有n型漂移区域NV的半导体衬底SUB。半导体衬底SUB具有上表面和下表面。接下来，通过例如热氧化在半导体衬底SUB的上表面上形成氧化硅膜10。接下来，通过例如CVD方法在氧化硅膜10上形成氮化硅膜11。
接下来，如图10中所示，通过光刻技术和干法蚀刻工艺选择性地移除区域1A中的氮化硅膜11和氧化硅膜10，并且在氮化硅膜11和氧化硅膜10中形成开口。然后，蚀刻暴露在开口处的半导体衬底SUB的一部分，以在半导体衬底SUB中形成沟槽。
接下来，如图11中所示，热氧化半导体衬底SUB，以从半导体衬底SUB的上表面到半导体衬底SUB的内部形成绝缘膜IF1。在该状态下，绝缘膜IF1被形成到高于半导体衬底SUB的上表面的位置。也就是说，在区域1A的SUB上形成LOCOS绝缘膜IF1。在该情况下，绝缘膜IF1的厚度例如是700nm至800nm。
接下来，如图12中所示，通过使用包含磷酸的溶液的各向同性蚀刻工艺移除氮化硅膜11。接下来，通过光刻和离子注入在区域1A的半导体衬底SUB上形成p型阱区域PW，并且在区域2A的半导体衬底SUB上形成p型浮置区域PF。接下来，通过光刻和离子注入在区域2A的SUB上形成n型空穴阻挡区域NHB。
接下来，如图13中所示，通过光刻技术和干法蚀刻工艺，在区域2A的子区域中形成沟槽TR。
接下来，如图14中所示，通过使用包含氢氟酸的溶液的各向同性蚀刻工艺移除氧化硅膜10。此时，由于绝缘膜IF1也暴露于各向同性蚀刻工艺，因此绝缘膜IF1的上表面后退，并且绝缘膜IF1的厚度减小。
接下来，如图15中所示，在例如1000到1200℃下对半导体衬底SUB进行热处理，以扩散包含在空穴阻挡区域NHB、浮置区域PF和阱区域PW中的杂质。通过此热处理，空穴阻挡区域NHB扩散到沟槽TR的底部附近，并且浮置区域PF扩散到比沟槽TR的底部更深的位置，从而覆盖沟槽TR的底部。
尽管未示出，但是利用形成在包括沟槽TR内部的半导体衬底SUB上的牺牲氧化硅膜来执行此热处理。热处理后，通过使用含有氢氟酸的溶液的各向同性蚀刻工艺移除牺牲氧化硅膜。此时，由于绝缘膜IF1也暴露于各向同性蚀刻工艺，因此绝缘膜IF1的上表面后退，并且绝缘膜IF1的厚度减小。在此情况下，绝缘膜IF1的厚度例如是500nm至600nm。
接下来，如图16中所示，在沟槽TR内和半导体衬底SUB上形成栅极绝缘膜GI。通过热氧化处理形成栅极绝缘膜GI。栅极电介质膜GI的厚度例如是100nm。
接下来，形成栅极电极GE以填充沟槽TR。为了形成栅极电极GE，首先，通过例如CVD方法在栅极绝缘膜GI上形成n型掺杂多晶硅膜。接下来，通过干法蚀刻移除形成在沟槽TR外部的多晶硅膜。形成在沟槽TR内部的多晶硅膜被留下作为栅极电极GE。
接下来，如图17中所示，通过例如CVD方法，在绝缘膜IF1、栅极电极GE和形成在沟槽TR外部的栅极绝缘膜GI上形成绝缘膜IF2。绝缘膜IF2的厚度例如是50nm至100nm。接下来，通过例如CVD方法在绝缘膜IF2上形成导电膜PL。导电膜PL的厚度例如是150nm至250nm。
接下来，通过离子注入将p型杂质引入导电膜PL。注意到，通过光刻技术和离子注入方法将n型和p型杂质引入到区域3A上的导电膜PL中，并且形成阳极区域PLP和阴极区域PLN。接下来，在区域1A上的导电膜PL上形成抗蚀剂图案RP1，以选择性地覆盖位于绝缘膜IF1上的导电膜PL。注意到，阳极区域PLP和阴极区域PLN也被抗蚀剂图案RP1覆盖。
接下来，如图18中所示，通过使用抗蚀剂图案RP1作为掩模执行干法蚀刻工艺来图案化导电膜P1和绝缘膜IF2。因此，在区域1A中形成电阻元件，并且在区域3A中形成二极管元件。图案化的绝缘膜IF2和绝缘膜IF1构成绝缘层IFL。在此干法蚀刻工艺中，形成在沟槽TR外部的栅极绝缘膜GI也被移除。此后，通过灰化移除抗蚀剂图案RP1。
接下来，如图19中所示，通过在半导体衬底SUB的上表面上进行光刻和离子注入，在半导体衬底SUB(浮置区域PF和空穴阻挡区域NHB)上形成p型基极区域PB。基极区域PB的底部位于沟槽TR的底部上方。接下来，通过光刻和离子注入在基极区域PB中形成n型发射极区域NE。此后，执行热处理以激活包含在杂质区域中的杂质。
接下来，如图20中所示，在半导体衬底SUB的区域1A和2A的上表面上形成层间绝缘膜IL，以便覆盖导电膜PL、栅极电极GE、基极区域PB和发射极区域NE。
接下来，如图21中所示，为了平坦化层间绝缘膜IL的上表面，通过CMP方法在1A和区域2A的层间绝缘膜IL上执行平坦化处理。在平坦化处理之后，半导体衬底SUB的上表面上的层间绝缘膜IL的厚度例如为600nm至800nm，导电膜PL的上表面上的层间绝缘膜IL的厚度例如为300nm至450nm。
接下来，如图22中所示，通过光刻技术和干法蚀刻工艺，在区域1A中的层间绝缘膜IL、导电膜PL、绝缘膜IF2和绝缘膜IF1中形成接触孔CH1。同时，在区域2A中，在层间绝缘膜IL、发射极区域NE和基极区域PB中形成接触孔CH2。接下来，通过离子注入在位于接触孔CH2底部的基极区域PB上形成p型高浓度扩散区域PR。
这里，接触孔CH1的底部位于绝缘膜IF1中，并且接触孔CH2的底部位于基极区域PB中。在研究3中，如图29中所示，接触孔CH1穿透导电膜PL，并且接触孔CH1的底部部分位于绝缘膜IF2上或绝缘膜IF2中。在第一实施例中，接触孔CH1比第三实施例中形成得更深。
此时，从导电膜PL的下表面到接触孔CH1的底部部分的距离例如为100nm至150nm。换句话说，图22中蚀刻绝缘层IFL的量被设置为大于图23中通过各向同性蚀刻工艺蚀刻层间绝缘膜IL和绝缘层IFL的量。
接下来，如图23中所示，使用包含氢氟酸的溶液各向同性地蚀刻层间绝缘膜IL和绝缘层IFL(绝缘膜IF2和绝缘膜IF1)。通过各向同性蚀刻工艺，层间绝缘膜IL的侧表面与导电膜PL的侧表面分离，使得导电膜PL的上表面的一部分暴露在接触孔CH1中。此外，在接触孔CH1中，绝缘层IFL的侧表面(绝缘膜IF1的侧表面和绝缘膜IF2的侧表面)与导电膜PL的侧表面分离，使得导电膜PL的下表面的一部分暴露。此外，在接触孔CH2中，层间绝缘膜IL的侧表面与发射极区域NE的侧表面分离，使得发射极区域NE的上表面的一部分被暴露。
然后，接触孔CH1的深度也通过上面所描述的各向同性蚀刻工艺增加。也就是说，如图7中所示，从导电膜PL的下表面到接触孔CH1的底部部分的距离L1比距离L2长。
接下来，如图24中所示，通过CVD方法在包括接触孔CH1的内部和接触孔CH2的内部的层间绝缘膜IL上形成阻挡金属膜BM。阻挡金属膜BM是例如钛膜和氮化钛膜的层压膜。此时，阻挡金属膜BM在接触孔CH1中与导电膜PL的上表面的一部分、导电膜PL的侧表面和导电膜PL的下表面的一部分接触。
接下来，在阻挡金属膜BM上形成导电膜CF，以填充接触孔CH1的内部和接触孔CH2的内部。导电膜CF例如是钨膜，并且使用WF6气体形成。
接下来，如图25中所示，通过使用CMP方法的抛光处理或各向异性干方法蚀刻工艺，移除形成在接触孔CH1外部和接触孔CH2外部的导电膜PL和阻挡金属膜BM。结果，在接触孔CH1中，导电膜PL和阻挡金属膜BM嵌入在插塞PG1中，并且导电膜PL和阻挡金属膜BM嵌入在插塞PG2中的接触孔CH2中。
接下来，如图26中所示，在区域1A的层间绝缘膜IL上形成栅极布线GW，并且在区域2A的层间绝缘膜IL上形成发射极电极EE。首先，通过例如溅射在层间绝缘膜IL上形成TiW膜，并且通过例如溅射在TiW膜上形成铝膜。接下来，通过光刻技术和干法蚀刻工艺对TiW膜和铝膜进行图案化以形成栅极布线GW和发射极电极EE。
此后，在半导体衬底SUB的下表面上形成场停止区域NS、集电极区域PC和集电极CE，从而获得图5的结构。
首先，将支撑带附着到半导体衬底SUB的上表面，并且研磨半导体衬底SUB的下表面，以将半导体衬底SUB的厚度减小到例如80至90微米。然后，通过用氢氟酸蚀刻SUB的下表面来移除接地损伤层。此后，通过从半导体衬底SUB的下表面进行离子注入，形成n型场停止区域NS和p型集电极区域PC。在这些注入之后，执行激光退火以激活包含在场停止区域NS和集电极区域PC中的杂质。接下来，在半导体衬底SUB的下表面上，在半导体衬底SUB的下表面下方，例如，通过溅射方法，形成AlSi膜、Ti膜、金属膜，诸如NiV膜和Au膜。金属膜用作集电极CE。
如上所描述的，制造了根据第一实施例的半导体器件100。
类似于检查示例2，第一实施例的制造方法可以对应于小型化比检查示例1先进的器件。例如，为了提高接触孔的加工精度，减小层间绝缘膜IL的上表面的高度差。为此，通过CMP方法在层间绝缘膜IL的上表面上执行平坦化处理以减小导电膜PL的厚度。此外，通过减小绝缘膜IF1的厚度，使得绝缘膜IF1的上表面基本上与半导体衬底SUB的上表面齐平，层间绝缘膜IL的上表面的台阶减小。
即使在此情况下，通过在导电膜IFL下面形成绝缘层PL，也可以消除接触孔CH1穿透导电膜SUB并且到达半导体衬底OOE的问题。此外，为了避免此类缺陷，因为接触孔CH1不需要在不同于接触孔CH2的制造过程中形成，所以不需要增加掩模的数量和增加制造过程，并且可以抑制制造成本的增加。
此外，在接触孔CH1在图22的过程中比在第三研究中形成得更深之后，通过图23的各向同性蚀刻工艺进一步加深接触孔CH1。即，从导电膜PL的下表面到接触孔CH1的底部部分的L1足够长。因此，由于阻挡金属膜BM是正常形成的，所以使用阻挡金属膜BM作为晶种膜容易充分地生长导电膜CF。此外，由于没有阻挡金属膜BM非常薄的部分，或没有形成阻挡金属膜BM的部分，所以WF6气体与导电膜CF反应，并且缺少导电膜CF的一部分。因此，可以制造高度可靠的半导体器件100。
尽管已经基于上述实施例描述了本发明，但是本发明不限于上述实施例，并且可以在不脱离其主旨的情况下进行各种修改。
例如，在上述实施例中，IGBT被示例为在区域2A中形成的器件，但是在上述实施例中公开的技术不限于IGBT，并且可以应用于具有竖直沟槽栅极结构的功率MOSFET。

Claims (14)

1.一种半导体器件，包括：
半导体衬底，具有上表面和下表面；
绝缘层，形成为从所述半导体衬底的所述上表面到所述半导体衬底的内部；
第一导电膜，形成在所述绝缘层上，
层间绝缘膜，形成在所述半导体衬底的所述上表面上以覆盖所述第一导电膜；
第一接触孔，形成在所述层间绝缘膜、所述第一导电膜和所述绝缘层中，使得所述第一接触孔的底部部分被定位在所述绝缘层中；以及
第一插塞，形成为填充所述第一接触孔，
其中在所述第一接触孔中，所述层间绝缘膜的侧表面与所述第一导电膜的侧表面分离，使得所述第一导电膜的上表面的一部分从所述层间绝缘膜暴露，
其中在所述第一接触孔中，所述绝缘层的侧表面与所述第一导电膜的侧表面分离，使得所述第一导电膜的下表面的一部分从所述绝缘层暴露，并且
其中从所述第一导电膜的所述下表面的所述部分到所述第一接触孔的所述底部部分的第一距离比从所述第一导电膜的所述侧表面到所述层间绝缘膜的所述侧表面的第二距离长。
2.根据权利要求1所述的半导体器件，
其中所述第一插塞包括：阻挡金属膜和第二导电膜，所述第二导电膜形成在所述阻挡金属膜上，并且
其中所述阻挡金属膜在所述第一接触孔中与所述第一导电膜的上表面的所述部分、所述第一导电膜的所述侧表面以及所述第一导电膜的所述下表面的所述部分接触。
3.根据权利要求1所述的半导体器件，
其中所述绝缘层包括：第一绝缘膜和第二绝缘膜，所述第一绝缘膜形成在所述半导体衬底内部，所述第二绝缘膜形成在所述第一绝缘膜上，
其中所述第一绝缘膜的厚度比所述第二绝缘膜的厚度薄，并且
其中所述第一接触孔的所述底部部分位于所述绝缘层的所述第一绝缘膜中。
4.根据权利要求3所述的半导体器件，其中所述层间绝缘膜、所述第一绝缘膜和所述第二绝缘膜的每一者都是氧化硅膜，并且
其中所述第一导电膜是多晶硅膜。
5.根据权利要求1所述的半导体器件，其中所述半导体衬底包括：第一区域和第二区域，在所述第一区域中形成所述第一导电膜，在所述第二区域中形成IGBT单元并且所述第二区域不同于所述第一区域；
其中所述IGBT单元包括形成在所述半导体衬底的上表面中的沟槽；
栅极绝缘膜，形成在所述沟槽中；
栅极电极，形成在所述栅极绝缘膜上以填充所述沟槽；
第一导电类型的基极区域，形成在所述半导体衬底的所述上表面中，使得所述基极区域的底部部分被定位在所述沟槽的底部部分上方；以及
发射极区域，形成在所述基极区域中并且具有与所述第一导电类型相反的第二导电类型，
其中所述层间绝缘膜的一部分形成在所述第二区域上，以覆盖所述栅极电极、所述基极区域以及所述发射极区域，
其中在所述层间绝缘膜的部分中形成第二接触孔，使得所述第二接触孔的底部部分位于所述基极区域中，
其中所述层间绝缘膜的所述部分的侧表面与所述发射极区域的侧表面分离，使得所述发射极区域的上表面的一部分从所述层间绝缘膜的所述部分暴露，并且
其中第二插塞被嵌入所述第二接触孔中。
6.根据权利要求5所述的半导体器件，其中所述第一区域和所述第二区域中的所述层间绝缘膜经受平坦化处理，用于使所述间绝缘膜的上表面平坦化。
7.根据权利要求5所述的半导体器件，还包括：
栅极布线，形成在所述层间绝缘膜上并且电连接到所述栅极电极；
发射极电极，形成在所述第二区域的所述层间绝缘膜上，
其中所述基极区域和所述发射极区域经由所述第二插塞电连接到所述发射极电极，并且
其中所述第一导电膜经由所述第一插塞电连接到所述栅极布线，并且被用作电阻元件和二极管元件中的一者。
8.一种制造半导体器件的方法，包括以下步骤：
(a)制备具有上表面和下表面的半导体衬底；
(b)在所述步骤(a)之后，形成从所述半导体衬底的上表面延伸到所述半导体衬底的内部的第一绝缘膜；
(c)在所述步骤(b)之后，在所述第一绝缘膜上形成厚度比所述第一绝缘膜薄的第二绝缘膜；
(d)在所述步骤(c)之后，在所述第二绝缘膜上形成第一导电膜；
(e)在所述步骤(d)之后，在所述半导体衬底的所述上表面上形成层间绝缘膜，以覆盖所述第一导电膜；
(f)在所述步骤(e)之后，在所述层间绝缘膜、所述第一导电膜、所述第二绝缘膜以及所述第一绝缘膜中形成第一接触孔，使得所述第一接触孔的底部部分位于所述第一绝缘膜中，
(g)在所述步骤(f)之后，使所述层间绝缘膜、所述第二绝缘膜以及所述第一绝缘膜经受各向同性蚀刻工艺，以及
(h)在所述步骤(g)之后，将所述第一插塞嵌入所述第一接触孔中，
其中通过所述步骤(g)中的所述各向同性蚀刻工艺，在所述第一接触孔中，所述层间绝缘膜的侧表面与所述第一导电膜的侧表面分离，使得所述第一导电膜的上表面的一部分从所述层间绝缘膜暴露，
其中通过所述步骤(g)中的所述各向同性蚀刻工艺，在所述第一接触孔中，所述第一绝缘膜的侧表面和所述第二绝缘膜的侧表面与所述第一导电膜的所述侧表面分离，使得所述第一导电膜的下表面的一部分从所述第一绝缘膜和第二绝缘膜暴露，并且
其中从所述第一导电膜的所述下表面到所述第一接触孔的所述底部部分的第一距离比从所述第一导电膜的所述侧表面到所述层间绝缘膜的所述侧表面的第二距离长。
9.根据权利要求8所述的制造半导体器件的方法，其中所述第一插塞包括阻挡金属膜和第二导电膜，
其中所述步骤(h)包括：
(h1)通过CVD方法在所述第一接触孔中形成所述阻挡金属膜；以及
(h2)在所述阻挡金属膜上形成所述第一导电膜，以填充所述第一接触孔，以及
其中所述阻挡金属膜在所述第一接触孔中与所述第一导电膜的所述上表面的一部分、所述侧表面以及所述下表面的一部分接触。
10.根据权利要求8所述的制造半导体器件的方法，其中所述第一绝缘膜是由热氧化方法形成的氧化硅膜，所述第二绝缘膜是通过CVD方法形成的氧化硅膜，并且所述第一导电膜是通过CVD方法形成的多晶硅膜。
11.根据权利要求10所述的制造半导体器件的方法，其中在所述步骤(b)中，所述第一绝缘膜形成在高于所述半导体衬底的所述上表面的位置，
其中在所述第一绝缘膜上执行各向同性蚀刻工艺，使得所述第一绝缘膜的厚度在所述步骤(b)和所述步骤(c)之间减小。
12.根据权利要求8所述的制造半导体器件的方法，还包括在与形成所述第一导电膜的区域不同的区域中形成IGBT单元的步骤，
其中形成所述IGBT单元的所述步骤包括：
(i)在所述步骤(b)之后和所述步骤(c)之前，在所述半导体衬底的上侧中形成沟槽；
(j)在所述步骤(i)之后和所述步骤(c)之前，在所述沟槽中形成栅极绝缘膜；
(k)在所述步骤(j)之后和所述步骤(c)之前，在所述栅极绝缘膜上形成栅极电极以填充所述沟槽；
(l)在所述步骤(d)之后和所述步骤(e)之前，在所述半导体衬底的所述上表面上形成第一导电类型的基极区域，使得所述基极区域的底部部分位于所述沟槽的底部部分上方，以及
(m)在所述步骤(l)之后和所述步骤(e)之前，在所述基极区域中形成第二导电类型的发射极区域，第二导电类型与所述第一导电类型相反，
其中在所述步骤(e)中，形成所述层间绝缘膜的一部分以覆盖所述栅极电极、所述基极区域以及所述发射极区域，
其中在所述步骤(f)中，在所述层间绝缘膜的所述部分中形成第二接触孔，使得所述第二接触孔的底部部分位于所述基极区域中，
其中通过所述步骤(g)，所述层间绝缘膜的所述部分的侧表面与所述发射极区域的侧表面分离，使得所述发射极区域的上表面的一部分从所述层间绝缘膜的所述部分暴露，并且
其中在所述步骤(h)中，第二插塞被嵌入所述第二接触孔中。
13.根据权利要求12所述的制造半导体器件的方法，还包括以下步骤：
(n)在所述步骤(e)之后和所述步骤(f)之前，通过CMP方法在所述层间绝缘膜上执行平坦化处理，以便使所述层间绝缘膜的上表面平坦化。
14.根据权利要求12所述的制造半导体器件的方法，还包括以下步骤：
(o)在所述步骤(h)之后，在所述层间绝缘膜上形成电连接到栅极电极的栅极布线并且在所述层间绝缘膜区域上形成发射极电极，
其中所述基极区域和所述发射极区域经由所述第二插塞电连接到所述发射极电极，并且
其中所述第一导电膜经由所述第一插塞电连接到所述栅极布线，并且被用作电阻元件或二极管元件中的一者。
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