CN116705750A - 多功能半导体装置衬底、使用其的半导体装置组合件及其形成方法 - Google Patents
多功能半导体装置衬底、使用其的半导体装置组合件及其形成方法 Download PDFInfo
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- CN116705750A CN116705750A CN202310202406.7A CN202310202406A CN116705750A CN 116705750 A CN116705750 A CN 116705750A CN 202310202406 A CN202310202406 A CN 202310202406A CN 116705750 A CN116705750 A CN 116705750A
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Abstract
本公开涉及多功能半导体装置衬底、使用其的半导体装置组合件及其形成方法。提供一种半导体装置组合件。所述组合件包含:衬底,其具有上表面,在所述上表面上安置第一装置触点;阻进区域,其从所述衬底的第一侧表面延伸到所述衬底的与第一侧表面相对的第二侧表面;及至少一个迹线,其耦合到所述第一装置触点并跨所述阻进区域朝向所述衬底的第三侧表面延伸。所述组合件进一步包含至少一个半导体装置,所述至少一个半导体装置安置在所述衬底的所述上表面上方并耦合到所述第一装置触点。除了所述至少一个迹线之外,所述衬底的所述阻进区域没有导电结构。
Description
技术领域
本公开大体来说涉及半导体装置组合件,且更特定来说涉及多功能半导体装置衬底、使用其的半导体装置组合件及其形成方法。
背景技术
微电子装置通常具有裸片(即,芯片),所述裸片包含具有非常小组件的高密度的集成电路系统。通常,裸片包含电耦合到集成电路系统的非常小的接合焊盘的阵列。接合焊盘为外部电触点,通过所述外部电触点将电源电压、信号等传输到集成电路系统并从集成电路系统传输。在形成裸片之后,将其“封装”以将接合焊盘耦合到更大的电端子阵列,所述电端子阵列可更容易地耦合到各种电源线、信号线及接地线。封装裸片的常规工艺包含将裸片上的接合焊盘电耦合到引线、球形焊盘或其它类型的电端子阵列,且囊封裸片以保护其免受环境因素影响(例如,水分、颗粒、静电,及物理影响)。
发明内容
在一个方面中,本公开涉及一种半导体装置组合件,其包括:衬底,其包含:上表面,其上安置有第一装置触点,阻进区域,其从所述衬底的第一侧表面延伸到所述衬底的与所述第一侧表面相对的第二侧表面,及至少一个迹线,其耦合到所述第一装置触点,并跨所述阻进区域朝向所述衬底的第三侧表面延伸;及至少一个半导体装置,其安置在所述衬底的所述上表面上方并耦合到所述第一装置触点,其中除了所述至少一个迹线之外,所述衬底的所述阻进区域没有导电结构。
在另一方面中,本公开涉及一种经配置用于不同半导体装置封装的衬底,所述衬底包括:上表面,其上安置有第一装置触点;阻进区域,其从所述衬底的第一侧表面延伸到所述衬底的与所述第一侧表面相对的第二侧表面;及至少一个迹线,其耦合到所述第一装置触点,并跨所述阻进区域朝向所述衬底的第三侧表面延伸,其中除了所述至少一个迹线之外,所述衬底的所述阻进区域没有导电结构。
在又一方面中,本公开涉及一种用于封装半导体装置组合件的方法,其包括:提供衬底,所述衬底包含:上表面,其上安置有第一装置触点及第二装置触点;阻进区域,从所述衬底的第一侧表面延伸到所述衬底的与所述第一侧表面相对的第二侧表面并在所述第一装置触点与所述第二装置触点之间通过;及至少一个迹线,其将所述第一装置触点耦合到所述第二装置触点,并跨所述阻进区域延伸,其中除了所述至少一个迹线之外,所述衬底的所述阻进区域没有导电结构;确定所述半导体装置组合件将根据第一配置还是第二配置形成;如果确定所述半导体装置组合件将根据所述第二配置来形成,那么移除所述衬底的包含所述第二装置触点的部分,并在所述衬底的第三侧表面处暴露所述至少一个迹线;及将至少一个半导体装置安置在所述衬底上方并耦合到所述第一装置触点,其中如果确定所述半导体装置组合件将根据所述第一配置形成,那么所述至少一个半导体装置通过所述第二装置触点及所述至少一个迹线耦合到所述第一装置触点,且其中如果确定所述半导体装置组合件将根据所述第二配置形成,那么所述至少一个半导体装置直接耦合到所述第一装置触点。
附图说明
图1为根据本公开的一个实施例的多功能半导体装置衬底的简化示意俯视平面图。
图2为根据本公开的一个实施例的适用于替代配置的多用途半导体装置衬底的简化示意俯视平面图。
图3为根据本公开的一个实施例的多功能半导体装置衬底的简化示意俯视平面图。
图4为根据本公开的一个实施例的适用于替代配置的多用途半导体装置衬底的简化示意俯视平面图。
图5A及5B为根据本公开的各种实施例的半导体装置组合件的简化示意性截面图,该半导体装置组合件包含适用于两种替代配置的多功能半导体装置衬底。
图6为说明根据本公开的实施例的用于封装半导体装置组合件的方法的流程图。
图7为展示包含根据本公开的实施例配置的半导体装置组合件的系统的示意图。
具体实施方式
下文描述半导体装置的若干实施例以及相关联系统及方法的具体细节。所属领域的技术人员将认识到,本文中所描述方法的合适阶段可以晶片级或裸片级执行。因此,取决于使用的上下文,术语“衬底”可指晶片级衬底或经单个化裸片级衬底。此外,除非上下文另有指示,否则可使用常规半导体制造技术形成本文中所公开的结构。可例如使用化学气相沉积、物理气相沉积、原子层沉积、电镀、化学镀、旋涂及/或其它合适的技术来沉积材料。类似地,可例如使用等离子蚀刻、湿法蚀刻、化学机械平面化或其它合适的技术来移除材料。
半导体装置组合件具有各种各样的配置,具有不同的尺寸,其中封装有不同数目及种类的半导体裸片,且具有各种外部连接方案。尽管一些配置在某些方面重叠(例如,具有不同尺寸及/或其中封装不同数目及种类的半导体装置的两种配置可共享相同的外部连接方案,例如具有相同尺寸、间距及脚位布置的球栅阵列),对于每一种可能的配置,传统上需要单独的衬底设计。传统上所需的各种各样的衬底设计极大地增加了制造及库存管理的成本及复杂性。
为了解决这些及其它缺点,本申请案的各种实施例提供了多用途衬底,其中单个衬底设计与多于一个半导体装置组合件配置兼容(例如,具有共用外部连接方案的多个组合件配置)。多功能衬底可包含多个冗余触点,不同的半导体装置可不同地连接到所述冗余触点,其中冗余触点由衬底的阻进区(keep-out zone)分开,其中仅有的导电元件是连接阻进区的相对侧上的冗余触点的迹线。在一个配置中,可通过沿着阻进区中的一或多个锯切/切割来移除承载一些冗余触点的衬底的一或多个外侧区域,从而减小衬底的大小。当由迹线连接的触点是接地触点时,通过锯切/切割穿过阻进区而暴露的迹线可任选地连接到封装的电磁干扰(EMI)屏蔽,以改进电气性能。
图1为根据本公开的一个实施例的多功能半导体装置衬底的简化示意俯视平面图。衬底100包含衬底主体101(例如,印刷电路板(PCB)等等),在其上表面上安置有各种电触点,所述电触点经配置以将信号路由到衬底主体101的下表面上的外部封装触点(未说明)。在当前所说明的实施例中,触点包含一或多个非冗余触点102(示意性地说明为区,其可包括各种离散接触焊盘、接合指,等)及多个冗余触点。冗余触点可包含一或多个内侧触点,例如触点103a及103b,以及一或多个外侧触点,例如触点104a、104b、105a、105b、106a及106b,每一触点通过对应一或多个迹线(例如,迹线108)电耦合到其对应内侧触点。尽管示意性地说明为单个大区域,但内侧触点103a及103b可替代地提供多个离散内侧触点,每一触点单独地连接到对应的外侧触点。在另一实施例中,内侧触点103a及103b可为大接地平面触点,各触点都冗余地连接到多个其它外侧触点。迹线108可安置在衬底主体101的上表面处,或可替代地安置在衬底主体101的中间深度处,或甚至可安置在衬底主体101的下表面处(或其任一组合)。
内侧触点103a及103b通过阻进区与经由迹线108连接到其的对应外侧触点分离,其中除了从中穿过的迹线108之外,衬底100大体上没有任何导电结构。例如,在图1中所说明的实施例中,阻进区沿着线110a、110b、110c及110d放置(例如,在所说明线的下方及邻近所述线)。触点的冗余以及其中仅有的导电结构是迹线108的阻进区的配置允许衬底100在两个或多于两个不同配置中提供类似的功能性(例如,上表面触点到外部封装触点的类似布线),其中从衬底移除线110a到110d外侧的区域中的0到4个。参考图2可更容易地理解上述情形,图2为类似衬底100的多用途半导体装置衬底的简化示意俯视平面图,但根据本公开的一个实施例,该衬底已适用于替代配置。
转到图2,可看到衬底200具有与衬底100在线110a到110d内侧的部分类似的特征—即,触点202、203a及203b。这些可类似地是提供多个离散触点的区,或替代地为大平面触点(例如,用于电源及/或接地)。触点203a及203b电连接到迹线,例如迹线208,迹线远离触点203a及203b朝向衬底主体201的边缘表面侧向延伸。通过分离图1中所说明的线110a到110d外侧的衬底100的那些部分(例如,通过锯切、切割、激光切割、蚀刻,等等),迹线108可在衬底主体101的侧表面处暴露,如已对在衬底主体201的侧表面处暴露的迹线208所做一般。这些暴露的表面可电耦合到其它结构(例如,当迹线耦合到接地平面触点时EMI屏蔽),或替代地用介电材料或绝缘材料(例如,模制化合物)覆盖以防止与其意外电接触。
与衬底100一样,衬底200可向封装的半导体装置提供类似外部连接,但具有适合于不同封装配置的较小的形状因数(例如,其中封装更小、更少或更密集封装的半导体装置)。如与专用离散衬底经设计用于每一封装配置的惯例方法相比,提供具有单一设计(例如,衬底100的设计)的衬底,所述设计可被转换以用于一或多个额外配置(例如,通过从对应于分离对应冗余触点的阻进区的线的外侧移除衬底的一或多个区域),可在成本、制造简单性及库存管理方面提供显著的优势。
转到图3,根据本公开的另一实施例的另一多功能半导体装置衬底的简化示意俯视平面图。衬底300包含衬底主体301(例如,PCB等等),在其上表面上安置有各种电触点,所述电触点经配置以将信号路由到衬底主体301的下表面上的外部封装触点(未说明)。在当前所说明的实施例中,触点包含一或多个非冗余触点302及多个冗余触点。冗余触点可包含一或多个内侧触点(例如触点303a到303d),以及一或多个外侧触点(例如触点304a到304d及305a到305d),每一触点通过对应一或多个迹线(例如,迹线308)电耦合到其对应内侧触点。迹线308可安置在衬底主体301的上表面处,或可替代地安置在衬底主体301的中间深度处,或甚至可安置在衬底主体301的下表面处(或其任一组合)。
内侧触点303a到303d通过阻进区与经由迹线308与其连接的对应外侧触点分离,其中除了从中穿过的迹线308之外,衬底300大体上没有任何导电结构。例如,在图3中所说明的实施例中,阻进区沿着线310a、310b、310c及310d放置(例如,在所说明线的下方及邻近所述线)。触点的冗余以及其中仅导电结构是迹线308的阻进区的配置允许衬底300在两个或多于两个不同配置中提供类似功能(例如,上表面触点到外部封装触点的类似布线),其中从衬底移除线310a到310d外侧的区域中的0到4个。参考图4可更容易地理解上述情形,图4为类似衬底300的多用途半导体装置衬底的简化示意俯视平面图,但根据本公开的一个实施例,该衬底已适用于替代配置。
转到图4,可看到衬底400具有与衬底300在线310c及310d内侧的部分类似的特征—即,触点402、403a到403b、405a到405d。触点403a到403d电连接到迹线,例如迹线408,其远离触点403a及403d侧向延伸。一些迹线408仍然将内侧触点403a到403d耦合到外侧触点405a到405d,因为没有移除阻进区外侧的衬底400的所有部分。尽管如此,由于衬底的一些部分已经移除(即,在线310a及310b外侧的那些部分),一些迹线408延伸到衬底主体401的侧表面。就这一点来说,通过分离图3中所说明的线310a及310b外侧的衬底300的那些部分(例如,通过锯切、切割、激光切割、蚀刻,等),迹线308可在衬底主体301的侧表面处暴露,如已对在衬底主体401的侧表面处暴露的迹线408所做一般。这些暴露的表面可电耦合到其它结构(例如,当迹线耦合到接地平面触点时EMI屏蔽),或替代地用介电材料或绝缘材料(例如,模制化合物)覆盖以防止与其意外电接触。
与衬底300一样,衬底400可向封装的半导体装置提供类似外部连接,但具有适合于不同封装配置的较小的形状因数(例如,其中封装更小、更少或更密集封装的半导体装置)。如与专用离散衬底经设计用于每一封装配置的惯例方法相比,提供具有单一设计(例如,衬底300的设计)的衬底,所述设计可被转换以用于一或多个额外配置(例如,通过从对应于分离对应冗余触点的阻进区的线的外侧移除衬底的一或多个区域),可在成本、制造简单性及库存管理方面提供显著的优势。
根据本公开的各种实施例,在图5A及5B中示意性地说明包含相同多模式衬底的半导体装置组合件的两个此类替代配置。在图5A中所说明的第一配置中,半导体装置组合件500a包含以第一配置布置的多模式衬底501a,其中冗余触点502a及502b通过在其间延伸的迹线503a耦合(例如,跨衬底501a的阻进区,如上文更详细说明)。一或多个半导体装置(例如半导体装置505a)堆叠可安置在衬底501a上方,且通过多个引线接合506a连接到迹线508及冗余焊盘502a及502b。冗余焊盘502a及502b又可通过安置在衬底501a中的各种迹线、通孔及其它导电结构(为了清楚起见在说明中省略,但对于所属领域的技术人员来说是众所周知的)连接到多个外部封装触点中的对应触点(例如,外部焊盘、焊料球、引脚,等),例如外部封装触点504。半导体装置505a、引线接合506a及衬底501a(例如,至少其上表面)可被模制化合物507a囊封。
根据本公开的一个方面,在图5B的第二配置中,已提供与图5A的衬底类似的多模衬底,但已对其进行处理以移除阻进区外侧的一或多个衬底区域。就这一点来说,如参考图5B可看出,由于移除图5A中分离冗余焊盘502a及502b的阻进区外侧的区域,半导体装置组合件500b具有明显更小的侧向尺寸。在半导体装置组合件500b中,衬底501b包含内侧焊盘502a及迹线503a的部分503b,其一直延伸到衬底501b的侧表面。比半导体装置组合件500a的半导体装置505a大的半导体装置505b的单个堆叠安置在衬底上方,并通过级联的一系列引线接合506b直接连接到内侧触点502a。类似于半导体装置组合件500a,半导体装置组合件500b具有多个外部封装触点,例如外部封装触点504,所述外部封装触点以类似方式布置(例如具有相同的数目、间距、尺寸及/或脚位配置),且触点502a同样通过衬底501b中的导电结构(未说明)连接到所述外部封装触点。同样地,类似囊封剂,例如模制材料507b,囊封半导体装置505b、引线接合506b及至少一部分衬底501b(例如,衬底501b的上表面)。利用连接到触点502a的迹线的剩余部分503b的暴露,还提供外部导电结构508(例如,EMI屏蔽),其在五个侧面上环绕半导体装置组合件500b,并在EMI屏蔽与多个外部触点当中的接地触点之间提供接地连接。在不需要EMI屏蔽的替代布置中,模制化合物507b可替代地设置在衬底501b的侧表面周围,以使迹线部分503b的暴露表面与无意接触绝缘。
图6为说明根据本公开的实施例的用于封装半导体装置组合件的方法的流程图。所述方法包含提供(框610)多模式衬底,所述多模式衬底包含其上安置有第一触点及第二触点的上表面、从衬底的第一侧表面延伸到衬底的与第一侧表面相对的第二侧表面并在第一触点与第二触点之间通过的阻进区域,及将第一触点耦合到第二触点并跨阻进区域延伸的至少一个迹线。如上文所述,除了至少一个迹线之外,衬底的阻进区域没有导电结构。所述方法进一步包含确定(框620)半导体装置组合件将根据第一配置还是第二配置来形成,且如果确定半导体装置组合件将根据第二配置来形成,那么移除(框630)衬底的包含第二触点的部分,并在衬底的第三侧表面处暴露至少一个迹线。所述方法进一步包含将至少一个半导体装置安置(框640)在衬底上方并耦合到第一触点。如果确定半导体装置组合件将根据第一配置形成,那么至少一个半导体装置通过第二触点及至少一个迹线耦合到第一触点,且如果确定半导体装置组合件将根据第二配置形成,那么至少一个半导体装置直接耦合到第一触点。
根据本公开的一个方面,上文所说明及描述的半导体装置组合件可包含存储器裸片,例如动态随机存取存储器(DRAM)裸片、“与非”(NAND)存储器裸片、“或非”(NOR)存储器裸片、磁性随机存取存储器(MRAM)裸片、相变存储器(PCM)裸片、铁电随机存取存储器(FeRAM)裸片、静态随机存取存储器(SRAM)裸片等等。在其中在单个组合件中提供多个裸片的实施例中,半导体装置可为相同类型的存储器裸片(例如,两个NAND、两个DRAM,等)或不同类型的存储器裸片(例如,一个DRAM及一个NAND等)。根据本公开的另一方面,上文所说明及描述的组合件的半导体裸片可包含逻辑裸片(例如,控制器裸片、处理器裸片等),或逻辑及存储器裸片的混合(例如,存储器控制器裸片及由此控制的存储器裸片)。
上文所描述的半导体装置及半导体装置组合件中的任何者可并入到大量更大及/或更复杂的系统中的任何者中,其代表性实例为图7中示意性展示的系统700。系统700可包含半导体装置组合件(例如,或离散半导体装置)702、电源704、驱动器706、处理器708及/或其它子系统或组件710。半导体装置组合件702可包含与上文所描述的半导体装置的特征大体类似的特征。所得系统700可执行广泛各种功能中的任何者,例如存储器存储、数据处理及/或其它合适的功能。因此,代表性系统700可包含但不限于手持装置(例如,移动电话、平板、数字阅读器及数字音频播放器)、计算机、车辆、电器及其它产品。系统700的组件可容纳在单个单元或分布在多个互连单元上方(例如,通过通信网络)。系统700的组件还可包含远程装置及广泛各种计算机可读媒体中的任一个。
本文中所论述的装置,包含存储器装置,可形成在半导体衬底或裸片上,例如硅、锗、硅锗合金、砷化镓、氮化镓等。在一些状况下,衬底为半导体晶片。在其它状况下,衬底可为绝缘体上硅(SOI)衬底,例如玻璃上硅(SOG)或蓝宝石上硅(SOP),或另一衬底上的半导体材料的外延层。可通过使用各种化学物质(包含但不限于磷、硼或砷)掺杂来控制衬底或衬底的子区域的导电性。可在衬底的初始形成或生长期间通过离子植入或通过任何其它掺杂手段执行掺杂。
本文中所描述的功能可以硬件、由处理器执行的软件、固件或其任一组合来实施。其它实例及实施方案在本公开及随附权利要求书的范围内。实施功能的特征也可实际上位于各种位置处,包含经分布使得在不同物理部位处实施功能的部分。
如本文中(包含在权利要求书中)所使用,如在物项列表(例如,后面接以例如“中的至少一个”或“中的一或多个”的短语的物项列表)中所使用的“或”指示包含性列表,使得(例如)A、B或C中的至少一个的列表意指A或B或C或AB或AC或BC或ABC(即,A及B及C)。此外,如本文中所使用,短语“基于”不应被认作对条件的闭集的参考。例如,被描述为“基于条件A”的示范性步骤可基于条件A及条件B两者而不背离本公开的范围。换句话说,如本文中所使用,短语“基于”应在方式上应被认作与短语“至少部分地基于”相同。
如本文中所使用,术语“垂直”、“侧向”、“上部”、“下部”、“上面”及“底面”可指代半导体装置中的特征鉴于图中所展示的定向的相对方向或位置。例如,“上部”或“最上部”可指代特征经定位比另一特征更靠近页的顶部。然而,这些术语应被广义地解释为包含具有其它定向的半导体装置,例如倒置或倾斜定向,其中顶部/底部、上方/下方、上面/下面,上/下及左/右可取决于定向互换。
应注意,上文所描述方法描述可能实施方案,且可重新布置或以其它方式修改操作及步骤,且其它实施方案为可能的。此外,可组合来自方法中的两者或多于两者的实施例。
从前述内容,将了解,出于说明的目的,本文中已描述本公开的特定实施例,但在不脱离本公开的范围的情况下可进行各种修改。确切地说,在前述描述中,论述许多具体细节,以便对本技术的实施例进行全面且有利的描述。然而,所属领域的技术人员将认识到,在没有具体细节中的一或多个的情况下,可实践本公开。在其它情况下,通常与存储器系统及装置相关联的已知结构或操作未展示,或未详细描述,以避免模糊技术的其它方面。一般说来,应理解,除本文中所公开的那些具体实施例外,各种其它装置、系统及方法可在本技术的范围内。
Claims (20)
1.一种半导体装置组合件,其包括:
衬底,其包含:
上表面,其上安置有第一装置触点,
阻进区域,其从所述衬底的第一侧表面延伸到所述衬底的与所述第一侧表面相对的第二侧表面,及
至少一个迹线,其耦合到所述第一装置触点,并跨所述阻进区域朝向所述衬底的第三侧表面延伸;及
至少一个半导体装置,其安置在所述衬底的所述上表面上方并耦合到所述第一装置触点,
其中除了所述至少一个迹线之外,所述衬底的所述阻进区域没有导电结构。
2.根据权利要求1所述的半导体装置组合件,其进一步包括安置在所述上表面上并通过所述至少一个迹线耦合到所述第一装置触点的第二装置触点。
3.根据权利要求2所述的半导体装置组合件,其中所述第二装置触点位于所述阻进区域的与所述第一装置触点相对的一侧上。
4.根据权利要求3所述的半导体装置组合件,其中所述至少一个半导体装置通过第二接地及所述至少一个迹线耦合到所述第一装置触点。
5.根据权利要求1所述的半导体装置组合件,其中所述阻进区域延伸到所述衬底的所述第三侧表面。
6.根据权利要求1所述的半导体装置组合件,其中所述至少一个迹线在所述衬底的所述第三侧表面处暴露。
7.根据权利要求6所述的半导体装置组合件,其进一步包括电磁干扰EMI屏蔽,所述电磁干扰屏蔽电耦合到所述衬底的所述第三侧表面处的所述暴露的至少一个迹线。
8.根据权利要求1所述的半导体装置组合件,其进一步包括安置在所述衬底的与所述上表面相对的下表面上的至少一个外部触点,所述至少一个外部触点通过所述衬底耦合到所述第一装置触点。
9.一种经配置用于不同半导体装置封装的衬底,所述衬底包括:
上表面,其上安置有第一装置触点;
阻进区域,其从所述衬底的第一侧表面延伸到所述衬底的与所述第一侧表面相对的第二侧表面;及
至少一个迹线,其耦合到所述第一装置触点,并跨所述阻进区域朝向所述衬底的第三侧表面延伸,
其中除了所述至少一个迹线之外,所述衬底的所述阻进区域没有导电结构。
10.根据权利要求9所述的衬底,其进一步包括安置在所述上表面上并通过所述至少一个迹线耦合到所述第一装置触点的第二装置触点。
11.根据权利要求10所述的衬底,其中所述第二装置触点位于所述阻进区域的与所述第一装置触点相对的一侧上。
12.根据权利要求9所述的衬底,其中所述阻进区域延伸到所述衬底的所述第三侧表面。
13.根据权利要求9所述的衬底,其中所述至少一个迹线在所述衬底的所述第三侧表面处暴露。
14.根据权利要求9所述的衬底,其进一步包括安置在所述衬底的与所述上表面相对的下表面上的至少一个外部触点,所述至少一个外部触点通过所述衬底耦合到所述第一装置触点。
15.根据权利要求9所述的衬底,其中所述阻进区域为第一阻进区域,且所述至少一个迹线为第一至少一个迹线,所述衬底进一步包括:
第三装置触点,其安置在所述上表面上;
第二阻进区域,其从所述第一侧表面延伸到所述第二侧表面;及
第二至少一个迹线,其耦合到所述第三装置触点,并跨所述第二阻进区域朝向所述衬底的与所述第三侧表面相对的第四侧表面延伸。
16.根据权利要求15所述的衬底,其进一步包括安置在所述上表面上并通过所述第二至少一个迹线耦合到所述第三装置触点的第四装置触点。
17.根据权利要求9所述的衬底,其中所述阻进区域为第一阻进区域,且所述至少一个迹线为第一至少一个迹线,所述衬底进一步包括:
第三装置触点,其安置在所述上表面上;
第二阻进区域,其从所述第三侧表面延伸到所述衬底的与所述第三侧表面相对的第四侧表面;及
第二至少一个迹线,其耦合到所述第三装置触点,并跨所述第二阻进区域朝向所述第一侧表面延伸。
18.根据权利要求17所述的衬底,其进一步包括安置在所述上表面上并通过所述第二至少一个迹线耦合到所述第三装置触点的第四装置触点。
19.一种用于封装半导体装置组合件的方法,其包括:
提供衬底,所述衬底包含:
上表面,其上安置有第一装置触点及第二装置触点;
阻进区域,从所述衬底的第一侧表面延伸到所述衬底的与所述第一侧表面相对的第二侧表面并在所述第一装置触点与所述第二装置触点之间通过;及
至少一个迹线,其将所述第一装置触点耦合到所述第二装置触点,并跨所述阻进区域延伸,其中除了所述至少一个迹线之外,所述衬底的所述阻进区域没有导电结构;
确定所述半导体装置组合件将根据第一配置还是第二配置形成;
如果确定所述半导体装置组合件将根据所述第二配置来形成,那么移除所述衬底的包含所述第二装置触点的部分,并在所述衬底的第三侧表面处暴露所述至少一个迹线;及
将至少一个半导体装置安置在所述衬底上方并耦合到所述第一装置触点,
其中如果确定所述半导体装置组合件将根据所述第一配置形成,那么所述至少一个半导体装置通过所述第二装置触点及所述至少一个迹线耦合到所述第一装置触点,且
其中如果确定所述半导体装置组合件将根据所述第二配置形成,那么所述至少一个半导体装置直接耦合到所述第一装置触点。
20.根据权利要求19所述的方法,其进一步包括在所述移除所述衬底的所述部分之后,将电磁干扰EMI屏蔽电耦合到所述衬底的所述第三侧表面处的所述暴露的至少一个迹线。
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