CN116705598A - 半导体结构及其制造方法 - Google Patents
半导体结构及其制造方法 Download PDFInfo
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Abstract
本公开提供了一种半导体结构及其制造方法,该半导体结构的制造方法包括:提供初始半导体结构,所述初始半导体结构包括基底和多晶硅层;在所述初始半导体结构上形成有第一掩膜层,所述第一掩膜层具有第一离子注入窗口,所述第一离子注入窗口定义出第一晶体管的栅极位置;进行第一离子注入工艺,通过所述第一离子注入窗口对所述第一晶体管的栅极进行功函数调节,以形成半导体结构。本公开提供的半导体结构的制造方法,能够对晶体管的栅极进行功函数调节。
Description
技术领域
本公开涉及半导体技术领域,具体而言,涉及一种半导体结构及其制造方法。
背景技术
随着超大规模集成电路技术的迅速发展,MOS(Metal Oxide Semiconductor)晶体管的尺寸在不断减小,通常包括MOS晶体管沟道长度的减小,栅氧化层厚度的减薄等以获得更快的器件速度。
MOS晶体管根据导电沟道的类型可分为P型MOS晶体管和N型MOS晶体管。由于NMOS和PMOS的阈值电压不同,NMOS和PMOS需要使用不同的功函数调节层。
需要说明的是,在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解,因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的其他特性和优点将通过下面的详细描述变得显然,或部分地通过本公开的实践而习得。
根据本公开实施例的一个方面,提供了一种半导体结构的制造方法,该制造方法包括:
提供初始半导体结构,所述初始半导体结构包括基底和多晶硅层;
在所述初始半导体结构上形成有第一掩膜层,所述第一掩膜层具有第一离子注入窗口,所述第一离子注入窗口定义出第一晶体管的栅极位置;
进行第一离子注入工艺,通过所述第一离子注入窗口对所述第一晶体管的栅极进行功函数调节,以形成半导体结构。
在本公开的一种示例性实施例中,所述半导体结构还形成有绝缘氧化层,所述绝缘氧化层形成于所述基底与所述多晶硅层之间。
在本公开的一种示例性实施例中,在所述进行第一离子注入工艺后,所述制造方法还包括:
使用第一溶剂去除所述第一掩膜层,以形成所述半导体结构,其中,所述第一溶剂为氨水和双氧水的混合水溶液。
在本公开的一种示例性实施例中,所述第一溶剂中,氨水的浓度为第一范围,双氧水的浓度为第二范围,水的浓度为第三范围,所述第三范围大于所述第二范围,所述第二范围大于所述第一范围。
在本公开的一种示例性实施例中,所述第一溶剂中,所述水的浓度与所述氨水和双氧水的浓度之和的比值大于5。
在本公开的一种示例性实施例中,所述使用第一溶剂去除所述第一掩膜层包括:
使用第一溶剂与第二溶剂同时去除所述第一掩膜层,其中,第二溶剂为硫酸和双氧水的混合水溶液。
在本公开的一种示例性实施例中,通过所述第一溶剂多次清洗所述第一掩膜层。
在本公开的一种示例性实施例中,通过所述第一溶剂清洗所述第一掩膜层时的温度为25℃~30℃。
在本公开的一种示例性实施例中,通过所述第一溶剂清洗所述第一掩膜层的时间为30s~150s。
在本公开的一种示例性实施例中,在所述使用第一溶剂去除所述第一掩膜层之后,形成所述半导体结构之前,所述制造方法还包括:
在所述初始半导体结构上形成第二掩膜层,所述第二掩膜层具有第二离子注入窗口,所述第二离子注入窗口定义出第二晶体管的栅极位置;
进行第二离子注入工艺,通过所述第二离子注入窗口对所述第二晶体管的栅极进行功函数调节;
在所述第二离子注入工艺之后,使用所述第一溶剂去除所述第二掩膜层。
在本公开的一种示例性实施例中,所述第一晶体管与所述第二晶体管的类型相反,对应所述第一离子注入工艺的注入离子类型与所述第二离子注入工艺的注入离子类型相反。
在本公开的一种示例性实施例中,所述第一晶体管是P型晶体管,所述第二晶体管是N型晶体管,所述第一离子注入的离子包括B离子,所述第二离子注入的离子包括AS/P离子。
在本公开的一种示例性实施例中,所述第一晶体管是N型晶体管,所述第二晶体管是P型晶体管,所述第一离子注入的离子包括AS/P离子,所述第二离子注入的离子包括B离子。
根据本公开实施例的另一个方面,提供了一种半导体结构,包括基底和多晶硅层,通过上述的制造方法对所述多晶硅层进行处理,以得到所述半导体结构。
在本公开的一种示例性实施例中,所述半导体结构还包括:
绝缘氧化层,位于所述基底与所述多晶硅层之间。
本公开提供的半导体结构的制造方法,通过在初始半导体结构上形成具有第一离子注入窗口的第一掩膜层,通过第一离子注入窗口定义出第一晶体管的栅极位置,接着通过第一离子注入窗口对第一晶体管的栅极进行功函数调节,以形成半导体结构,实现了对晶体管的栅极功函数的调节。
应当理解的是,以上的一般描述和后文的细节描述仅是示例性和解释性的,并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分,示出了符合本公开的实施例,并与说明书一起用于解释本公开的原理。显而易见地,下面描述中的附图仅仅是本公开的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。在附图中:
图1为本公开的一种实施例提供的开态电流与关态电流的调节关系示意图;
图2为本公开的一种实施例提供的阈值电压与漏源电流的调节关系示意图;
图3为本公开的一种实施例提供的阈值电压与关态电流的调节关系示意图;
图4为本公开的一种实施例提供的半导体结构的制造方法的流程图;
图5为本公开的一种实施例提供的半导体结构的示意图;
图6为本公开另的一种实施例提供的半导体结构的制造方法的流程图;
图7为本公开又的一种实施例提供的半导体结构的制造方法的流程图;
图8为本公开的一种实施例提供的半导体结构优化前后EOT对比示意图;
图9为本公开的一种实施例提供的半导体结构优化前后VT/IDS/IOFF的对比示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而,示例实施方式能够以多种形式实施,且不应被理解为限于在此阐述的范例;相反,提供这些实施方式使得本公开将更加全面和完整,并将示例实施方式的构思全面地传达给本领域的技术人员。
此外,所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中,提供许多具体细节从而给出对本公开的实施例的充分理解。然而,本领域技术人员将意识到,可以实践本公开的技术方案而没有特定细节中的一个或更多,或者可以采用其它的方法、组元、装置、步骤等。在其它情况下,不详细示出或描述公知方法、装置、实现或者操作以避免模糊本公开的各方面。
附图中所示的方框图仅仅是功能实体,不一定必须与物理上独立的实体相对应。即,可以采用软件形式来实现这些功能实体,或在一个或多个硬件模块或集成电路中实现这些功能实体,或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
附图中所示的流程图仅是示例性说明,不是必须包括所有的内容和操作/步骤,也不是必须按所描述的顺序执行。例如,有的操作/步骤还可以分解,而有的操作/步骤可以合并或部分合并,因此实际执行的顺序有可能根据实际情况改变。
由于多种因素的综合影响,MOS晶体管在工作时其沟道实际上并不可能完全被夹断,即MOS晶体管的漏极电流ID不可能达到真正的0状态。因此,在实际应用中,当MOS晶体管的漏极电流很接近0时即认为此时晶体管栅极与源极之间的电压差称为MOS晶体管的夹断电压,此时所产生的漏极电流称为晶体管的关态电流Ioff。与此相对地,对于NMOS而言,当驱动电压VGS大于0且VGS是夹断电压的某一倍数(不小于1)时所产生的漏极电流称为开态电流Ion;对于PMOS而言,当VGS小于0且VGS的绝对值是夹断电压的某一倍数(不小于1)时所产生的漏极电流称为开态电流Ion。晶体管的关态电流Ioff实际上是晶体管的漏电流,当晶体管的关态电流越小则表示晶体管的功耗越小,因此,对于MOS晶体管而言常,开关电流比Ion/Ioff越大,则表示晶体管的功耗越小,速度越快。因此,需要提高晶体管的开关电流比Ion/Ioff。
如图1-图3所示,标点1为未做调节时半导体器件的电学性能,横轴表征的是开态电流ION,纵轴表征的是关态电流IOFF,标点2为通过传统的调节方式形成的新的半导体器件的电学性能,主要通过调节LDD(漏区浅掺杂)、halo(沟道区源端高掺杂)及沟道浓度等方式实现,可以看出在提升了ION(开态电流)的同时漏电IOFF(关态电流)也会被拉高,阈值电压VT被降低,这是由于这些调节作用在沟道内部及附近对ION/IOFF/VT的影响是同步的,无法单独实现提升ION的同时保持VT/IOFF不变,而IOFF被拉高,意味功耗增大,VT降低,意味器件开启电压降低,容易被误开启。
本公开的实施例首先提供了一种半导体结构的制造方法,如图4所示,该制造方法包括:
步骤S100、提供初始半导体结构,初始半导体结构包括基底和多晶硅层;
步骤S200、在初始半导体结构上形成有第一掩膜层,第一掩膜层具有第一离子注入窗口,第一离子注入窗口定义出第一晶体管的栅极位置;
步骤S300、进行第一离子注入工艺,通过第一离子注入窗口对第一晶体管的栅极进行功函数调节,以形成半导体结构。
本公开提供的半导体结构的制造方法,通过在初始半导体结构上形成具有第一离子注入窗口的第一掩膜层,通过第一离子注入窗口定义出第一晶体管的栅极位置,接着通过第一离子注入窗口对第一晶体管的栅极进行功函数调节,以形成半导体结构,实现了对晶体管的栅极功函数的调节。
下面,将对本公开提供的半导体结构的制造方法的各步骤进行详细的说明。
在步骤S100中,提供初始半导体结构,初始半导体结构包括基底和多晶硅层。
具体地,提供初始半导体结构,如图5所示,该半导体结构包括基底10和多晶硅层30。基底10为半导体材料,包括但不限于单晶硅衬底、多晶硅衬底、氮化镓衬底或蓝宝石衬底,另外,半导体基底为单晶衬底或多晶衬底时,还可以是本征硅衬底或者是轻微掺杂的硅衬底,进一步,可以为N型多晶硅衬底或P型多晶硅基底。
如图5所示,基底10形成有浅沟槽隔离结构(STI)110。可通过浅槽隔离技术对半导体基底进行隔离,在半导体衬底上形成浅沟槽隔离沟槽,浅沟槽隔离沟槽的深度例如可为20nm~40nm,接着在刻蚀出的浅沟槽隔离沟槽中采用化学气相沉积(chemical vapordeposition,CVD)、物理气相沉积(physical vapor deposition,PVD)或其他的沉积技术形成浅沟槽隔离结构。浅沟槽隔离结构隔离出的多个有源区,其中,浅沟槽隔离结构的材料可以包括氮化硅或氧化硅等绝缘材料。作为示例,有源区内形成有MOS器件的源漏极和沟道区域(未示出),MOS器件还包括栅极,源极与漏极分别位于栅极相对的两侧。
如图5所示,多晶硅层30与基底10之间还设有绝缘氧化层20,绝缘氧化层20用于实现多晶硅层30与基底10之间的电性绝缘。绝缘氧化层20的材料例如可为氧化硅、氮氧化硅、氮化硅、氧化铪等高介电常数材料或其他适合的绝缘物质(例如有机高分子化合物)或上述材料的组合。绝缘氧化层20的形成方法例如是物理气相沉积法、化学气相沉积法、旋涂法或其组合。
多晶硅层30可作为半导体器件的栅极。早期,金属铝被普遍用作MOS的首选栅材料,MOS制备过程始于源区和漏区的定义和掺杂。然后,采用栅罩来定义栅氧化区,从而形成铝金属门。这种制造工艺的一个主要缺点是,如果栅极掩模不对中,它会产生寄生重叠输入电容Cgd和Cgs。由于电容是反馈电容,因此电容Cgd危害更大。由于米勒电容,晶体管的开关速度降低了。
解决栅极掩模失调的一个方法是所谓的“自对准门过程”。这个过程首先是创建栅极区域,然后使用离子注入创建漏和源区。栅下的薄栅氧化物作为掺杂过程的遮罩,防止栅区(通道)下进一步掺杂。因此,这个过程使得栅极相对于源和漏区的自对准。因此,源和漏区不会延伸到栅极下方。漏源区的掺杂工艺要求采用超高温退火方法(通常>8000℃)。如果用铝作为浇口材料,它会在如此高的温度下熔化。这是因为铝的熔点约为660℃,但是,如果用多晶硅作为浇口材料就不会熔化。因此,多晶硅栅极的自对准过程是可能的。而在铝栅的情况下,这是不可能的,这导致高的Cgd和Cgs。因此,现在的半导体器件中大多使用多晶硅作为栅极材料。
其中,源极、漏极、栅极分别通过接触插塞、导线与测试端相连,接收测试电压、电流,输出工作电压、电流。
其中,可在基底10上相邻的两个浅沟槽隔离结构之间的区域采用各向异性刻蚀再形成字线沟槽(图中未示出),可通过化学气相沉积法、物理气相沉积法或其他方式在字线沟槽内形成金属字线。形成字线的导电材料包括钨、钛、镍、铝、氧化钛、氮化钛中的一种或它们的组合,本领域技术人员还可选取其他导电材料,本公开对此不做限制。
在步骤S200中,在初始半导体结构上形成有第一掩膜层,第一掩膜层具有第一离子注入窗口,第一离子注入窗口定义出第一晶体管的栅极位置。
具体地,如图5所示,在初始半导体结构上沉积第一掩膜材料层,第一掩膜材料层例如为光刻胶,接着通过对光刻胶曝光、显影形成图案化的第一掩膜层40,使得图案化的第一掩膜层40具有第一离子注入窗口,第一离子注入窗口定义出第一晶体管的栅极位置。其中,光刻胶可为正性光刻胶或负性光刻胶。
在步骤S300中,进行第一离子注入工艺,通过第一离子注入窗口对第一晶体管的栅极进行功函数调节,以形成半导体结构。
具体地,未掺杂多晶硅具有非常高的电阻率,约108Ω/cm。因此,多晶硅的掺杂方式使得其电阻降低,同时为了调节半导体器件的阈值电压,会对多晶硅进行不同掺杂类型的离子注入,减小金属栅极和半导体基底之间的功函数差。
在本公开的一种实施例中,如图5所示,根据第一离子注入窗口对多晶硅层30进行离子注入形成N型多晶硅层,以作为N型晶体管的栅极。多晶硅层30进行离子注入的掺杂粒子例如为磷(P)或砷(As)中的至少一种,掺杂浓度可为1013atom/cm2-1016atom/cm2。通过调节掺杂浓度可以进一步调节多晶硅栅极的单位面积电阻,掺杂浓度越高,多晶硅栅极的单位面积电阻越低。光刻胶未覆盖N型晶体管的栅极区域,即N型多晶硅层(N-POLY)打开,因此后续洗光刻胶的时候会有P/As原子析出,导致多晶硅栅耗尽效应(当多晶硅的掺杂浓度有限时,其上存在压降,那么多晶硅栅极的内部就会有电场存在,从而使绝缘氧化层界面附近处的电子/空穴容易被电场吸引到多晶硅栅极一侧,导致绝缘氧化层界面附近出现耗尽层,使半导体器件的等效绝缘层厚度EOT变大)。
在本公开的另一种实施例中,根据第一离子注入窗口对多晶硅层30进行离子注入形成P型多晶硅层,以作为P型晶体管的栅极。多晶硅层30进行离子注入的掺杂粒子例如为硼(B),掺杂浓度可为1013atom/cm2-1016atom/cm2。通过调节掺杂浓度可以进一步调节多晶硅栅极的单位面积电阻,掺杂浓度越高,多晶硅栅极的单位面积电阻越低。光刻胶未覆盖P型晶体管的栅极区域,即P型多晶硅层(P-POLY)打开,因此后续洗光刻胶的时候会有B原子析出,导致多晶硅栅耗尽效应。
具体地,在进行第一离子注入工艺后,如图6所示,制造方法还包括步骤S400:使用第一溶剂去除第一掩膜层,以形成半导体结构。
在多晶硅层30进行第一工艺离子注入工艺完成后,使用第一溶剂清洗初始半导体结构上的光刻胶(第一掩膜层40),以形成半导体结构。其中,第一溶剂(APM溶剂)为氨水(NH4OH)和双氧水(H2O2)的混合水溶液。
其中,氨水的浓度为第一范围,双氧水的浓度为第二范围,水的浓度为第三范围,第三范围大于第二范围,第二范围大于第一范围。通过改善上述溶液的配比,可以减少多晶硅中注入离子的析出,减小多晶硅栅耗尽效应,减小等效氧化层厚度,减少多晶硅的离子析出损失也可以降低多晶硅的阻值。通过缩短工艺的时间,再加上改善上述溶液的配比可以使多晶硅层在厚度上的损失相对常规工艺减少约1.5nm,即相对常规工艺多晶硅层的厚度增加了1.5nm,由于多晶硅层的厚度与方块阻值成反比(ρ(电阻率)=R*a(宽度)*t(厚度)/b(长度)),从而使器件的性能得到优化。
其中,在第一溶剂中,水的浓度与氨水和双氧水的浓度之和的比值大于5,优选地,氨水(NH4OH)、双氧水(H2O2)与水(H2O)的摩尔比为1:1~10:50~100,例如1:1:50、1:5:70、1:10:100等,本公开在此不一一列举。
具体地,使用第一溶剂去除第一掩膜层包括:使用第一溶剂与第二溶剂同时去除第一掩膜层。其中,第二溶剂(SPM溶剂)为硫酸(H2SO4)和双氧水(H2O2)的混合水溶液,可将第一溶剂与第二溶剂混合同时清洗初始半导体结构上的光刻胶(第一掩膜层)。
在本公开的一种实施例中,通过第一溶剂(和第二溶剂)清洗初始半导体结构上的光刻胶,包括:将初始半导体结构送入旋涂设备,并使真空吸盘吸附初始半导体结构背离光刻胶一侧的背面;向光刻胶喷淋第一溶剂(和第二溶剂);旋转初始半导体结构,使第一溶剂铺满光刻胶的表面,并被甩出;停止旋转初始半导体结构,将初始半导体结构从旋涂设备中取出。
在本公开的另一种实施例中,通过第一溶剂(和第二溶剂)清洗初始半导体结构上的光刻胶,包括:向光刻胶表面喷淋第一溶剂(和第二溶剂);采用超声波清洗光刻胶。
在本公开的另一种实施例中,通过第一溶剂(和第二溶剂)清洗初始半导体结构上的光刻胶,制造方法还包括:通过等离子灰化和/或湿法清洗去除部分光刻胶,再通过第一溶剂与第二溶剂清洗剩余的光刻胶。
其中,通过第一溶剂(和第二溶剂)清洗光刻胶,并对光刻胶进行清洗为多次,以提高清洗的效果。
其中,通过第一溶剂(和第二溶剂)清洗光刻胶的时间为30s~150s,例如30s、50s、70s、100s、130s、150s等,本公开在此不一一列举。当然,对光刻胶进行清洗的时间也可小于30s或大于150s,本公开对此不做限制。通过控制清洗的时间,减少多晶硅与第一溶剂(第二溶剂)的反应时间,可以减少多晶硅中掺杂离子,B离子和/或AS/P离子与第一溶剂(第二溶剂)反应,从而可以减少多晶硅栅耗尽效应的形成,使具有该半导体结构的器件的EOT减少从而ION得到提升。
其中,通过第一溶剂(和第二溶剂)清洗光刻胶,并对光刻胶进行清洗的温度为25℃~30℃,例如25℃、26℃、27℃、28℃、29℃、30℃等,本公开在此不一一列举。当然,对光刻胶进行清洗的温度也可小于25℃或大于30℃,本公开对此不做限制。
通过降低清洗光刻胶的温度可以减少多晶硅层中注入的离子被反应,从而可以减少depletion(空乏区)的形成,使具有该半导体结构的器件的EOT减少从而ION得到提升。从EOT与VT/IDS/IOFF的敏感度可知,由于EOT对电流的敏感度很高,而VT与IOFF很微弱,减少微量的B或者P的析出只会使ION得到改善,是相比于implant(离子注入)的改善更为精细控制。
本公开通过控制在栅极功函数调节之后的清洗方式,改善ION的性能。首先,主要是通过减少多晶硅层中P及B的析出达到减少氧化层的电学厚度,从而达到提升ION,且不影响VT及IOFF的效果;如图8所示,横坐标的“初始”代表没有做优化的晶圆,“优化”代表使用本公开制造方法优化的晶圆;纵坐标为NMOS的EOT值,单位是 可以看出,优化前NMOS的EOT为/>优化后NMOS的EOT为/>优化后的晶圆的EOT明显降低。
其次,本公开通过调节及减少clean的液体浓度减少poly的损失,通过降低clean的反应温度降低poly中P或B的扩散及析出,实现的技术效果如图1中标点3所示,在较大幅度提升了开态电流ION的情况下,避免了拉高或过多拉高关态电流IOFF;如图2中标点3所示,在保证阈值电压VT未降低或基本未降低的情况下,较大幅度提升了漏源电流IDS;如图3中标点3所示,在保证阈值电压VT降低或基本未降低的情况下,避免了拉高关态电流IOFF;如图9所示,横坐标的“初始”代表没有做优化的晶圆,“优化”代表使用本申请制造方法优化的晶圆;纵坐标从上到下分别是VT/IDS/IOFF。可以看出,优化前后NMOS的VT没有太大变化,IDS在经本申请的制造方法优化后相对增加,IOFF在经本申请的制造方法优化后相对减小,从而实现了单独实现提升ION的同时避免VT/IOFF拉高的目的,提升了器件开关比。
具体地,在使用第一溶剂清洗光刻胶之后,形成半导体结构之前,如图7所示,制造方法还包括步骤S500、在初始半导体结构上形成第二掩膜层,第二掩膜层具有第二离子注入窗口,第二离子注入窗口定义出第二晶体管的栅极位置;进行第二离子注入工艺,通过第二离子注入窗口对第二晶体管的栅极进行功函数调节。
在去除第一掩模层之后,接着在初始半导体结构上沉积第二掩模材料层,第二掩模材料层例如为光刻胶材料,接着通过曝光、显影形成图案化的光刻胶层,形成具有第二离子注入窗口的第二掩模层,根据第二离子注入窗口对多晶硅层露出的区域进行离子注入,例如形成P型多晶硅层,以作为P型晶体管的栅极。
具体地,在第二离子注入工艺之后,形成半导体结构之前,如图7所示,制造方法还包括步骤S600、使用第一溶剂去除第二掩膜层。
通过第一溶剂清洗去除覆盖于第二区域上的光刻胶,形成半导体结构。其中,清洗第二掩膜层的具体工艺步骤,可与上述清洗第一掩膜层的工艺步骤相同,其具有的有益效果与清洗清洗第一掩膜层相同,在此不再赘述。
在本公开的一种实施例中,多晶硅层第二离子注入的掺杂离子例如为硼(B),掺杂浓度为1013atom/cm2-1016atom/cm2。通过调节掺杂浓度可以进一步调节多晶硅栅极的单位面积电阻,掺杂浓度越高,多晶硅栅极的单位面积电阻越低。
在本公开的另一种实施例中,多晶硅层第二离子注入的掺杂离子例如为磷(P)或砷(As)中的至少一种,掺杂浓度可为1013atom/cm2-1016atom/cm2。通过调节掺杂浓度可以进一步调节多晶硅栅极的单位面积电阻,掺杂浓度越高,多晶硅栅极的单位面积电阻越低。
其中,第一离子注入工艺的注入离子类型与第二离子注入工艺的注入离子类型相反,第一晶体管与第二晶体管的类型相反。
本公开的实施例还提供了一种半导体结构,包括基底和多晶硅层,通过上述的制造方法对多晶硅层进行处理,以得到所述半导体结构。
其中,半导体结构还包括:绝缘氧化层,绝缘氧化层位于所述基底与所述多晶硅层之间。绝缘氧化层用于实现多晶硅层与基底之间的电性绝缘。绝缘氧化层的材料例如可为氧化硅、氮氧化硅、氮化硅、氧化铪等高介电常数材料或其他适合的绝缘物质或上述材料的组合。绝缘氧化层的形成方法例如是物理气相沉积法、化学气相沉积法、旋涂法或其组合。
本公开上述提供的具有多晶硅栅极的半导体结构,可应用于例如金属氧化物半导体场效应晶体管(metal oxide semiconductor field effect transistor,MOSFET)、绝缘栅阻隔型双极晶体管(Insulated Gate Bipolar Transistor,IGBT)或结场效应晶体管(Junction Field Effect Transistor,JFET)等。上述包括本公开半导体结构的晶体管可应用于半导体存储器中,该半导体存储器可为计算存储器(例如,DRAM、SRAM、DDR3SDRAM、DDR2SDRAM、DDRSDRAM等)、消费型存储器(例如,DDR3SDRAM、DDR2SDRAM、DDRSDRAM、SDRSDRAM等)、图形存储器(例如,DDR3SDRAM、GDDR3SDMRA、GDDR4SDRAM、GDDR5SDRAM等)、移动存储器等等。其具有的有益效果可参照上述对半导体结构叙述,在此不再赘述。
本领域技术人员在考虑说明书及实践这里公开的发明后,将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化,这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的,本公开的真正范围和精神由下面的权利要求指出。
应当理解的是,本公开并不局限于上面已经描述并在附图中示出的精确结构,并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。
Claims (15)
1.一种半导体结构的制造方法,其特征在于,包括:
提供初始半导体结构,所述初始半导体结构包括基底和多晶硅层;
在所述初始半导体结构上形成有第一掩膜层,所述第一掩膜层具有第一离子注入窗口,所述第一离子注入窗口定义出第一晶体管的栅极位置;
进行第一离子注入工艺,通过所述第一离子注入窗口对所述第一晶体管的栅极进行功函数调节,以形成半导体结构。
2.根据权利要求1所述的制造方法,其特征在于,所述半导体结构还形成有绝缘氧化层,所述绝缘氧化层形成于所述基底与所述多晶硅层之间。
3.根据权利要求2所述的制造方法,其特征在于,在所述进行第一离子注入工艺后,所述制造方法还包括:
使用第一溶剂去除所述第一掩膜层,以形成所述半导体结构,其中,所述第一溶剂为氨水和双氧水的混合水溶液。
4.根据权利要求3所述的制造方法,其特征在于,所述第一溶剂中,氨水的浓度为第一范围,双氧水的浓度为第二范围,水的浓度为第三范围,所述第三范围大于所述第二范围,所述第二范围大于所述第一范围。
5.根据权利要求4所述的制造方法,其特征在于,所述第一溶剂中,所述水的浓度与所述氨水和双氧水的浓度之和的比值大于5。
6.根据权利要求3所述的制造方法,其特征在于,所述使用第一溶剂去除所述第一掩膜层包括:
使用第一溶剂与第二溶剂同时去除所述第一掩膜层,其中,第二溶剂为硫酸和双氧水的混合水溶液。
7.根据权利要求3所述的制造方法,其特征在于,通过所述第一溶剂多次清洗所述第一掩膜层。
8.根据权利要求3所述的制造方法,其特征在于,通过所述第一溶剂清洗所述第一掩膜层时的温度为25℃~30℃。
9.根据权利要求3所述的制造方法,其特征在于,通过所述第一溶剂清洗所述第一掩膜层的时间为30s~150s。
10.根据权利要求3所述的制造方法,其特征在于,在所述使用第一溶剂去除所述第一掩膜层之后,形成所述半导体结构之前,所述制造方法还包括:
在所述初始半导体结构上形成第二掩膜层,所述第二掩膜层具有第二离子注入窗口,所述第二离子注入窗口定义出第二晶体管的栅极位置;
进行第二离子注入工艺,通过所述第二离子注入窗口对所述第二晶体管的栅极进行功函数调节;
在所述第二离子注入工艺之后,使用所述第一溶剂去除所述第二掩膜层。
11.根据权利要求10所述的制造方法,其特征在于,所述第一晶体管与所述第二晶体管的类型相反,对应所述第一离子注入工艺的注入离子类型与所述第二离子注入工艺的注入离子类型相反。
12.根据权利要求11所述的制造方法,其特征在于,所述第一晶体管是P型晶体管,所述第二晶体管是N型晶体管,所述第一离子注入的离子包括B离子,所述第二离子注入的离子包括AS/P离子。
13.根据权利要求11所述的制造方法,其特征在于,所述第一晶体管是N型晶体管,所述第二晶体管是P型晶体管,所述第一离子注入的离子包括AS/P离子,所述第二离子注入的离子包括B离子。
14.一种半导体结构,其特征在于,包括基底和多晶硅层,通过权利要求1-13任一项所述的制造方法对所述多晶硅层进行处理,以得到所述半导体结构。
15.根据权利要求14所述的半导体结构,其特征在于,所述半导体结构还包括:
绝缘氧化层,位于所述基底与所述多晶硅层之间。
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