CN116679991A - Method, system, equipment and storage medium for managing starting of memory - Google Patents
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1417—Boot up procedures
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Abstract
The embodiment of the application provides a method, a system, equipment and a storage medium for starting management of a memory, and belongs to the technical field of memories. The method comprises the following steps: bit data in any flash memory page is acquired, and the bit data is analyzed to obtain a target bit value and a corresponding target proportion value; acquiring an error correction range of a target bit value; if the target proportion value is out of the error correction range, a first starting result is obtained, and the flash memory page starting operation is stopped according to the first starting result; if the target proportion value is in the error correction range, performing hardware error correction operation on the bit data, obtaining a second starting result when the hardware error correction is successful, and completing flash memory page starting operation according to the second starting result; if the hardware error correction fails, executing the software error correction operation on the bit data, obtaining a third starting result of the flash memory page starting operation when the software error correction is successful, and if the software error correction fails, obtaining a fourth starting result of stopping the flash memory page starting operation. The application can improve the starting speed of the memory.
Description
Technical Field
The present application relates to the field of memory technologies, and in particular, to a method, a system, an apparatus, and a storage medium for managing startup of a memory.
Background
A Memory (Memory) is a Memory means for storing programs and various data information. The memory is used as an indispensable device in each computing task, and the starting speed is an important index. The memory includes a flash memory, and in the process of starting the memory, it is generally necessary to reconstruct flash memory data, if the data to be reconstructed is damaged due to abnormal power failure, it takes more time to correct the error data in the reconstruction process, so that the memory device starts up and times out, and the time out of the memory can cause the external main control system to read codes or data to report errors.
Because the memory cannot predict the correctness of the data, error correction is often required to be performed on all the data in the flash memory, in the related art, the time is reduced by optimizing the error correction efficiency and shortening the process of hardware decoding or software decoding until all the error correction actions are invalid, and the data is considered to be in error and discarded.
Disclosure of Invention
The embodiment of the application mainly aims to provide a method, a system, equipment and a storage medium for starting management of a memory, which can improve the starting speed of the memory.
To achieve the above object, a first aspect of an embodiment of the present application provides a method for managing startup of a memory, the method including: acquiring bit data in any flash memory page, and analyzing the bit data to obtain a target bit value and a corresponding target proportion value; acquiring an error correction range of the target bit value; if the target proportion value is out of the error correction range, determining that the flash memory page has no error correction requirement, obtaining a first starting result, and stopping starting operation of the flash memory page according to the first starting result; if the target proportion value is in the error correction range, determining that the flash memory page has error correction requirements, executing hardware error correction operation on the bit data, obtaining a second starting result when the hardware error correction is successful, and completing the starting operation of the flash memory page according to the second starting result; if the hardware error correction fails, executing software error correction operation on the bit data, obtaining a third starting result when the software error correction is successful, and completing the starting operation of the flash memory page according to the third starting result; and if the software error correction fails, a fourth starting result is obtained, and the starting operation of the flash memory page is stopped according to the fourth starting result.
In some embodiments, the parsing the bit data to obtain a target bit value and a corresponding target scale value includes: analyzing to obtain a first bit value and a second bit value according to the bit data, wherein the first bit value is used for representing one minimum information value of the flash memory page, and the second bit value is used for representing the other minimum information value of the flash memory page; and selecting any one from the first bit value and the second bit value to perform proportion calculation with the bit data, so as to obtain a target proportion value.
In some embodiments, the obtaining the error correction range of the target bit value includes: obtaining sample labels corresponding to each flash memory page sample; if the sample labels comprise a first sample label representing that the flash page sample has no error correction requirement or a second sample label representing that the flash page sample has error correction requirement, summarizing the sample labels to obtain the sample label number; summarizing the first sample tags to obtain a first sample tag number, and performing proportional operation on the first sample tag number and the sample tag number to obtain a first sample proportional value; summarizing the second sample tags to obtain a second sample tag number, and performing proportional operation on the second sample tag number and the sample tag number to obtain a second sample proportional value; determining that the first sample ratio value and the second sample ratio value are a first boundary value and a second boundary value of the error correction range, respectively, and determining that a range between the first boundary value and the second boundary value is the error correction range.
In some embodiments, the obtaining the error correction range of the target bit value includes: acquiring sample bit data of the corresponding flash memory page sample when the sample tag is the first sample tag, or acquiring sample bit data of the corresponding flash memory page sample when the sample tag is the second sample tag; obtaining a plurality of sample proportion values according to the sample bit data; selecting a plurality of median or mode values of the sample proportion values to obtain a first interval endpoint value, performing difference operation on a sample base number and the first interval endpoint value to obtain a second interval endpoint value, determining that the first interval endpoint value and the second interval endpoint value are a third boundary value and a fourth boundary value of the error correction range respectively, and determining that a range between the third boundary value and the fourth boundary value is the error correction range; or, performing an average operation or a weighting operation on the plurality of sample proportion values to obtain a third interval endpoint value, performing a difference operation on a sample base number and the third interval endpoint value to obtain a fourth interval endpoint value, determining that the third interval endpoint value and the fourth interval endpoint value are respectively a fifth boundary value and a sixth boundary value of the error correction range, and determining that a range between the fifth boundary value and the sixth boundary value is the error correction range.
In some embodiments, after the obtaining the sample tag corresponding to each flash page sample, the method further includes: if the sample label is empty, executing the hardware error correction operation on the flash memory page samples one by one, and obtaining a second sample label for representing that the flash memory page samples have error correction requirements when the hardware error correction is successful; and if the hardware error correction fails, performing software error correction operation on the sample bit data, obtaining a second sample label for representing that the flash page sample has error correction requirements when the software error correction is successful, and obtaining the first sample label when the software error correction fails.
In some embodiments, the method further comprises: when the starting result is the first starting result or the fourth starting result, adding a bad page label for the corresponding flash memory page; and determining the flash memory page as an invalid page according to the bad page tag.
In some embodiments, the method presets a target result proportion threshold, the method further comprising: counting the number of the first starting results to obtain a first target result value; counting the number of the second starting results and the number of the third starting results to obtain a second target result value; proportional operation is carried out on the first target result value and the second target result value, and a target result proportional value is obtained; and if the target result proportion value exceeds the target result proportion threshold value, re-determining the error correction range according to the sample bit data of the flash memory page samples.
To achieve the above object, a second aspect of an embodiment of the present application provides a system for managing startup of a memory, the system including: the data acquisition module is used for acquiring bit data in any flash memory page, and analyzing the bit data to obtain a target bit value and a corresponding target proportion value; an error correction module, configured to obtain an error correction range of the target bit value; if the target proportion value is out of the error correction range, determining that the flash memory page has no error correction requirement, obtaining a first starting result, and stopping starting operation of the flash memory page according to the first starting result; if the target proportion value is in the error correction range, determining that the flash memory page has error correction requirements, executing hardware error correction operation on the bit data, obtaining a second starting result when the hardware error correction is successful, and completing the starting operation of the flash memory page according to the second starting result; if the hardware error correction fails, executing software error correction operation on the bit data, obtaining a third starting result when the software error correction is successful, and completing the starting operation of the flash memory page according to the third starting result.
To achieve the above object, a third aspect of the embodiments of the present application provides an electronic device, which includes a memory and a processor, where the memory stores a computer program, and the processor executes the computer program to implement the method according to the embodiment of the first aspect.
To achieve the above object, a fourth aspect of the embodiments of the present application proposes a storage medium, which is a computer-readable storage medium storing a computer program, which when executed by a processor implements the method according to the embodiment of the first aspect.
The method, the system, the equipment and the storage medium for managing the starting of the memory, which are provided by the embodiment of the application, can be applied to a starting management system of the memory. Firstly, acquiring bit data in a flash memory page, analyzing the bit data according to the acquired bit data to obtain a target bit value and a corresponding target proportion value, wherein the bit data in the flash memory consists of a bit value 1 and a bit value 0, the bit value 1 or the bit value 0 can be selected as the target bit value, then, comparing the target proportion value with an acquired error correction range, judging that the flash memory page has no error correction requirement if the target proportion value is out of the error correction range, obtaining a first starting result, and stopping starting operation of the flash memory page according to the first starting result; if the target proportion value is in the error correction range, judging that the flash memory page has error correction requirements, then carrying out hardware error correction on the flash memory page, if the hardware error correction is successful, obtaining a second starting result, if the hardware error correction is failed, obtaining a third starting result, and completing the starting operation of the flash memory page according to the second starting result and the third starting result by the memory. The embodiment of the application can judge the target proportion value corresponding to the target bit value according to the error correction range obtained in advance, and carry out error correction operation on the bit data in the flash memory pages with the target proportion value falling in the error correction range, thereby reducing unnecessary error correction process on the bit data in all the flash memory pages, shortening the starting time of the memory and further improving the starting speed of the memory.
Drawings
FIG. 1 is an alternative flow chart of a method for boot management of a memory provided by an embodiment of the present application;
FIG. 2 is a flowchart illustrating a method for managing startup of a memory according to an embodiment of the present application;
FIG. 3 is a flow chart of one implementation of step S101 in FIG. 1;
FIG. 4 is a flow chart of one implementation of step S102 in FIG. 1;
FIG. 5 is another implementation flowchart of step S102 in FIG. 1;
FIG. 6 is a flow chart of one implementation after step S301 in FIG. 4;
FIG. 7 is another alternative flow chart of a method for boot management of a memory provided by an embodiment of the present application;
FIG. 8 is a flowchart of a further alternative method for boot management of a memory provided by an embodiment of the present application;
FIG. 9 is a functional block diagram of a method for managing startup of a memory according to an embodiment of the present application;
fig. 10 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present application.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
It should be noted that although functional block division is performed in a device diagram and a logic sequence is shown in a flowchart, in some cases, the steps shown or described may be performed in a different order than the block division in the device, or in the flowchart. The terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the application only and is not intended to be limiting of the application.
First, several nouns involved in the present application are parsed:
flash Memory (fast Memory), which is one of memories, refers to a semiconductor Memory chip that is commonly used in power failure without losing information, has the advantages of small volume, low power consumption and uneasy physical damage, and is an ideal storage medium for mobile digital products.
According to different connection modes of the basic storage units of the flash memory, the flash memory products can be divided into four categories, namely: storage type Flash memory (NAND Flash), coded type Flash memory (NOR Flash), DINOR Flash (DINOR (digital Bit-Line NOR Flash), AND Flash (AND Flash).
ECC (Error Correcting Code) error correction is an error detection and correction algorithm for NAND flash. NAND flash memory typically fails when there is no problem in operation timing and circuit stability, however, NAND flash memory typically does not cause the entire Block or Page to be unreadable or to fail entirely, but only one or a few bits (bit values) to fail. The ECC error correction comprises hardware error correction and software error correction, wherein a space is reserved in the NAND flash memory for carrying out hardware error correction operation on a hardware error correction module, the hardware error correction can correct 1 bit error and detect 2 bit errors, the calculation speed is high, but the error above 1 bit cannot be corrected, and the error above 2 bits cannot be detected. When more bits are needed for bit correction, software error correction is adopted, and the bit data in the NAND flash memory is subjected to software error correction by means of external software.
Currently, the starting speed of a storage device as a means for storing executable code and data is an important indicator. Because the memory has abnormal power-down condition, the storage device needs to reconstruct data in the starting process, if the data to be reconstructed is damaged due to abnormal power-down, the reconstruction process comprises error correction operation on error data, however, the error correction of the error data can take more time, and the starting time of the storage device is overtime. If the storage device is not started up in a specified time, the external master control system can be caused to read codes or data to report errors.
Since the memory cannot predict data errors, all data needs to be tried for error correction, which may include hardware decoding and software decoding, and the data is not considered to be erroneous and discarded until all error correction actions are invalid. In the related art, the rebuilding time is reduced by optimizing the error correction efficiency and shortening the flow of hardware decoding or software decoding, so as to reduce the starting time of the memory.
Based on the above, the embodiment of the application provides a method, a system, an electronic device and a storage medium for managing the starting of a memory, which can improve the starting speed of the memory.
The embodiment of the application can be applied to NAND flash memories, and can be applied to other flash memories or other memories on the premise of meeting the requirements of the embodiment of the application, and the embodiment is not particularly limited.
The method, system, device and storage medium for managing the startup of the memory provided by the embodiment of the application are specifically described by the following embodiments, and the method for managing the startup of the memory in the embodiment of the application is described first.
As shown in fig. 1, fig. 1 is an optional flowchart of a method for managing startup of a memory according to an embodiment of the present application, where the method in fig. 1 may include, but is not limited to, steps S101 to S106.
Step S101, bit data in any flash memory page is obtained, and the bit data is analyzed to obtain a target bit value and a corresponding target proportion value;
in some embodiments, a NAND flash memory (hereinafter referred to as "flash memory") includes a plurality of flash memory blocks, each of which includes a plurality of flash memory pages, each of the flash memory pages having bit data for storing information therein, selecting any one of the plurality of flash memory pages, and acquiring the bit data in the flash memory page. In the flash memory, bit data is bit value 1 or bit value 0, and bit value 1 and bit value 0 are stored in different arrangement sequences in specified positions of a flash memory page, constituting data that can be read.
In some embodiments, the bit data is parsed to obtain a target bit value, where a bit value 1 or a bit value 0 is selected as the target bit value, for example, the parsed bit value 1 is used as the target bit value, and the proportion of the bit value 1 in the bit data is calculated to obtain the target proportion value.
Step S102, obtaining an error correction range of a target bit value;
in some embodiments, the purpose of obtaining the error correction range for the target bit value is to determine the relationship of the target scale value for the obtained flash page to the error correction range to determine whether the bit data in the flash page requires error correction.
It should be noted that, the error correction range may be obtained in various manners, which may be preset, or may be obtained by counting and calculating a certain sample flash page and the data related to the flash page.
Step S103, if the target proportion value is out of the error correction range, determining that the flash memory page has no error correction requirement, obtaining a first starting result, and stopping the starting operation of the flash memory page according to the first starting result;
in some embodiments, the data written to flash memory is often randomly encoded such that the proportion of bit data in each flash page is approximately 50% each, which is referred to as a zero proportion, which may also be referred to as a zero-standard value. When the bit data in the flash memory page is in error, the bit data will be turned over, and the corresponding zero-to-one ratio will be changed correspondingly, so the zero-to-one ratio can be used as a measure of the error of the bit data in the flash memory page. Further, when the zero-to-one ratio is deviated by 50% to a small extent, the bit data in the flash page can be data corrected by hardware error correction and software error correction, but when the deviation of the zero-to-one ratio is large and exceeds the error correction range, the bit data cannot be corrected, i.e. the flash page is not available.
In some embodiments, comparing the target proportion value with the obtained error correction range, it can be understood that when the target proportion value falls outside the error correction range, the flash page cannot be restored to the available state by the error correction operation with a high probability, so that it is directly determined that the flash page is not necessary for error correction, and a first starting result is obtained, where the first starting result indicates that the flash page is not operated when the flash is started.
Step S104, if the target proportion value is in the error correction range, determining that the flash memory page has error correction requirements, executing hardware error correction operation on the bit data, obtaining a second starting result when the hardware error correction is successful, and completing the starting operation of the flash memory page according to the second starting result;
in some embodiments, when the target proportion value falls within the error correction range, the bit data in the flash memory page can be recovered to be available through error correction operation with high probability, so that further error correction judgment is required for the flash memory page. Firstly, determining that the flash memory page has error correction necessity, executing hardware error correction operation on bit data in the flash memory page, and if the hardware error correction operation is successful, obtaining a second starting result, wherein the second starting result indicates that the error correction of the flash memory page is successful, the bit data is recovered to be normal, and when the flash memory is started, the flash memory page can work.
Step S105, if the hardware error correction fails, executing software error correction operation on the bit data, obtaining a third starting result when the software error correction is successful, and completing the starting operation of the flash memory page according to the third starting result;
in some embodiments, if the hardware error correction fails, in the case that it is determined that the flash memory page has error correction necessary, further software error correction operation is required to further determine the error correction condition of the flash memory page according to the software error correction result. For example, if the software error correction is successful, the flash page can obtain a third starting result, where the third starting result indicates that the error correction of the flash page is successful, the bit data is recovered to be normal, and when the flash is started, the flash page can work normally.
And step S106, if the software error correction fails, a fourth starting result is obtained, and the starting operation of the flash memory page is stopped according to the fourth starting result.
In some embodiments, if the software fails to correct the error, it indicates that the flash page cannot be recovered by error correction, i.e. the bit data recovery fails, and the flash page does not work when the flash is started.
As shown in fig. 2, fig. 2 is a flow chart of a method for managing startup of a memory according to an embodiment of the present application, firstly, obtaining bit data of a flash memory page, analyzing to obtain a zero-to-one ratio of the bit data, then, obtaining an error correction range of the flash memory page, determining whether the zero-to-one ratio is within the error correction range, and if the zero-to-one ratio is not within the error correction range, directly determining that the flash memory page is in error; if the zero proportion is in the error correction range, performing hardware error correction operation on bit data in the flash memory page, and if the hardware error correction is successful, directly judging that the flash memory page is recovered to be normal without performing software error correction operation; if the hardware error correction fails, continuing to execute the software error correction operation, and if the software error correction is successful, judging that the flash memory page is recovered to be normal; if the software error correction fails, judging that the flash memory page is in error.
It can be understood that by setting the error correction range, comparing the target proportion value with the error correction range, and directly determining the flash memory page corresponding to the target proportion value falling outside the error correction range as an error flash memory page, the unnecessary process of correcting the bit data in all the flash memory pages is reduced, the starting time of the flash memory is shortened, and the starting speed of the flash memory is further improved.
As shown in fig. 3, fig. 3 is a flowchart of one implementation of step S101 in fig. 1, and in some embodiments, step S101 may include steps S201 to S202:
step S201, according to the bit data, analyzing to obtain a first bit value and a second bit value, wherein the first bit value is used for representing one minimum information value of a flash memory page, and the second bit value is used for representing the other minimum information value of the flash memory page;
in some embodiments, the bit is the smallest unit of information, the acquired bit data includes a plurality of bit values 1 or 0, and the bit data is subjected to data parsing to obtain a first bit value or a second bit value, where the first bit value may be the bit value 1, and the second bit value may be the bit value 0.
Step S202, selecting any one from the first bit value and the second bit value to perform proportion calculation with the bit data, and obtaining a target proportion value.
In some embodiments, the first bit value may be selected to perform a scaling operation with the bit data to obtain a target scaling value, for example, 512 bit data are included in a certain flash memory page, where the total number of bit values 1 is 300, and the number of bit values 1 in the flash memory page and the total number of bit data in the flash memory page are scaled to obtain a target scaling value of 58.59%, where it is understood that if the error correction range is 40% to 60%, the target scaling value falls within the error correction range, that is, the flash memory page has a need for error correction, and the error correction is subsequently required for the bit data in the flash memory page.
Or, the second bit value and the bit data may be selected to perform the proportional operation, and since the bit data in the flash memory page only has two cases of the bit value 1 and the bit value 0, it is feasible to select any bit value and the total bit data to perform the proportional operation, and the specific implementation of the proportional operation of the second bit value and the bit data is basically the same as the specific implementation of the proportional operation of the first bit value and the bit data, which is not repeated herein.
As shown in fig. 4, fig. 4 is a flowchart of one implementation of step S102 in fig. 1, and in some embodiments, step S102 may include steps S301 to S305:
Step S301, obtaining sample labels corresponding to each flash memory page sample;
in some embodiments, the error correction range may be obtained according to a plurality of flash page samples, and each flash page sample includes a respective corresponding sample tag, where the sample tag includes an error correction tag corresponding to the flash page sample, and the error correction tag indicates whether error correction is necessary for the corresponding flash page sample, and when the flash page sample is sufficiently many, the error correction range can be obtained according to the error correction tags of the plurality of flash pages and the proportion of the error correction tags.
Step S302, if the sample label comprises a first sample label which represents that the flash page sample has no error correction requirement or a second sample label which represents that the flash page sample has error correction requirement, summarizing the sample labels to obtain the sample label number;
in some embodiments, if the sample tag in the obtained flash page sample is not empty, that is, if the sample tag is a first sample tag indicating that the sample has no error correction requirement or a second sample tag indicating that the sample has error correction requirement, the overall statistics is first performed on the sample tag, so as to obtain the number of sample tags when the sample tag is not empty, that is, the number of sample tags.
Step S303, summarizing the first sample tags to obtain a first sample tag number, and performing proportional operation on the first sample tag number and the sample tag number to obtain a first sample proportional value;
in some embodiments, summarizing a first sample tag in the sample tags to obtain a first sample tag number, wherein the first sample tag number represents the number of sample tags without error correction requirements, and then performing proportional operation on the sample tag number and the first sample tag number to obtain a first sample proportional value, and the first sample proportional value represents the ratio of the sample tags without error correction requirements to the total sample tags.
For example, there are 512 sample tags in total, 200 first sample tags in total, and the first sample proportion value is 39.06%, i.e., the first sample tag without error correction requirement accounts for 39.06% of all sample tags.
Step S304, summarizing the second sample labels to obtain a second sample label number, and performing proportional operation on the second sample label number and the sample label number to obtain a second sample proportional value;
in some embodiments, summarizing a second sample tag in the sample tags to obtain a second sample tag number, wherein the second sample tag number represents the number of sample tags with error correction requirements, and then, performing proportional operation on the sample tag number and the second sample tag number to obtain a second sample proportional value, wherein the second sample proportional value represents the duty ratio of the sample tags with error correction requirements in the total sample tags.
For example, there are 512 sample tags in total, 312 second sample tags in total, and the second sample proportion value is 62.40%, that is, the second sample tags with error correction requirements account for 62.40% of all sample tags.
In step S305, it is determined that the first sample ratio value and the second sample ratio value are the first boundary value and the second boundary value of the error correction range, respectively, and the range between the first boundary value and the second boundary value is determined as the error correction range.
In some embodiments, the first sample proportion value obtained as described above may be used as a first boundary value of the error correction range, the second sample proportion value may be used as a second boundary value of the error correction range, and the error correction range may be obtained therefrom, where the error correction range includes the first boundary value and the second boundary value. As exemplified above, when the first sample tag having no error correction requirement has a 39.06% ratio among all sample tags and the second sample tag having an error correction requirement has a 62.40% ratio among all sample tags, it is determined that the error correction range is 39.06% to 62.40%, i.e., [39.06,62.40], which can be used in the startup management method of the memory described above.
As shown in fig. 5, fig. 5 is another implementation flowchart of step S102 in fig. 1, and in some embodiments, step S102 may include steps S401 to S404:
Step S401, obtaining sample bit data of a corresponding flash memory page sample when the sample tag is a first sample tag, or obtaining sample bit data of a corresponding flash memory page sample when the sample tag is a second sample tag;
in some embodiments, the obtaining of the error correction range may further be implemented, specifically, obtaining the above-mentioned flash page sample when the sample tag is the first sample tag, and obtaining sample bit data of the flash page sample, where the purpose is to determine the error correction range by categorizing and summarizing characteristics of the bit data in the sample tag of the same type.
It should be noted that, since the bit data in the flash page sample has only two cases of bit value 1 and bit value 0, the flash page sample when the sample tag is the second sample tag can be obtained as well, and the sample bit data of the flash page sample can be obtained to determine the error correction range.
Step S402, obtaining a plurality of sample proportion values according to sample bit data;
in some embodiments, sample proportion values of a plurality of flash page samples may be obtained according to a plurality of sample bit data, specifically, a first sample bit value of the sample bit value of 1 may be obtained, and a case that the first sample bit value occupies the total sample bit data may be determined to obtain the sample proportion value.
Step S403, selecting the median or mode of a plurality of sample proportion values to obtain a first interval endpoint value, performing a difference operation on the sample base and the first interval endpoint value to obtain a second interval endpoint value, determining that the first interval endpoint value and the second interval endpoint value are a third boundary value and a fourth boundary value of an error correction range respectively, and determining that a range between the third boundary value and the fourth boundary value is the error correction range;
in some embodiments, the error correction range without error correction requirements is obtained by selecting the median or mode of the plurality of sample scale values, as the sample scale value obtained for the first sample bit value.
For example, the sample radix is 1, the obtained plurality of sample ratio values are 39.12%, 56.43%, 42.35%, 60.67%, 58.51%, 42.35%, 55.89%, the median of these data is selected to be 55.89%, a second interval endpoint value is obtained, a difference operation is performed between the sample radix and the median to obtain a first interval endpoint value 44.11%, the first interval endpoint value and the second interval endpoint value are respectively used as a third boundary value and a fourth boundary value of the error correction range, and the error correction range can be determined to be [44.11, 55.89], and similarly, the error correction range at this time includes the third boundary value and the fourth boundary value, that is, when the target ratio value of the flash memory page is 44.11% or 55.89%, it is determined that the target ratio value falls within the error correction range, that is, the flash memory page has the error correction requirement.
For example, the sample radix is 1, the obtained sample ratio values are 39.12%, 56.43%, 42.35%, 60.67%, 58.51%, 42.35%, 55.89%, the mode of these data is selected to be 42.35%, a first section endpoint value is obtained, the sample radix and the mode are subjected to a difference operation to obtain a second section endpoint value 57.65%, and the first section endpoint value and the second section endpoint value are respectively used as a third boundary value and a fourth boundary value of the error correction range, so that the error correction range can be determined to be [42.35, 57.65].
Alternatively, a tolerance may be added to the first section end point value and the second section end point value, and the tolerance is set to 5% for example. The error correction range [44.11, 55.89] can be changed to [39.11, 60.89], and the setting of the fault tolerance can enable the error correction range to be more reasonable and conform to the actual operation condition.
In step S404, or, an average operation or a weighting operation is performed on the plurality of sample ratio values to obtain a third interval endpoint value, a difference operation is performed on the sample base number and the third interval endpoint value to obtain a fourth interval endpoint value, the third interval endpoint value and the fourth interval endpoint value are determined to be a fifth boundary value and a sixth boundary value of the error correction range, respectively, and a range between the fifth boundary value and the sixth boundary value is determined to be the error correction range.
For example, the sample radix is 1, the obtained sample ratio values are 39.12%, 56.43%, 42.35%, 60.67%, 58.51%, 42.35%, 55.89%, the average of these data is 50.76%, the fourth interval endpoint value is obtained by calculating the average, the sample radix and the average are subjected to a difference operation, the third interval endpoint value is 49.24%, the third interval endpoint value and the fourth interval endpoint value are respectively used as the fifth boundary value and the sixth boundary value of the error correction range, and the error tolerance of 8% is increased, so that the error correction range can be determined to be [41.24, 58.76], and similarly, the error correction range at this time includes the fifth boundary value and the sixth boundary value, that is, when the target ratio value of the flash memory page is 49.24% or 50.76%, it is determined that the target ratio value falls within the error correction range, that is, the flash memory page has an error correction requirement.
For example, the sample radix is 1, and the obtained plurality of sample proportion values are 39.12%, 56.43%, 42.35%, 60.67%, 58.51%, 42.35%, and 55.89%, where the flash memory page where the first three sample proportion value data are located is an important flash memory page, the sample proportion value of the flash memory page can be given a higher proportion coefficient when calculating, and the flash memory page where the last four sample proportion value data are located is a general flash memory page, and the sample proportion value of the flash memory page can be given a lower proportion coefficient when calculating. For example, if the calculated scaling factor of the important flash page is 1, the calculated scaling factor of the general flash page is 0.6, the weighted calculation is performed on these data to obtain a third interval endpoint value of 38.34%, the difference is performed on the sample base and the average to obtain a fourth interval endpoint value 61.66%, and the third interval endpoint value and the fourth interval endpoint value are respectively the fifth boundary value and the sixth boundary value of the error correction range, the error correction range can be determined to be [38.34, 61.66].
It should be noted that, the value of the fault tolerance may be set according to the specific situation, or the fault tolerance may not be added according to the specific situation, and the embodiment of the present application is only described in a preferred embodiment, and is not limited in particular.
It should be noted that the error correction range may be set in various manners, and the embodiment of the present application is only described in the preferred embodiment, and is not limited in particular.
As shown in fig. 6, fig. 6 is a flowchart of one implementation after step S301 in fig. 4, and the method in fig. 6 may include, but is not limited to including, step S501 to step S502.
Step S501, if the sample label is empty, executing hardware error correction operation on the flash memory page samples one by one, and obtaining a second sample label for representing that the flash memory page samples have error correction requirements when the hardware error correction is successful;
in some embodiments, the sample tag is empty, if when the sample tag is empty, hardware error correction operation needs to be performed on the flash page samples without the sample tag one by one, and if the hardware error correction is successful, a second sample tag for representing that the flash page samples have error correction requirements is obtained.
Step S502, if the hardware error correction fails, performing a software error correction operation on the sample bit data, obtaining a second sample tag for representing that the flash page sample has error correction requirements when the software error correction is successful, and obtaining a first sample tag when the software error correction fails.
In some embodiments, if the hardware error correction fails, continuing to perform a software error correction operation on the bit data of the flash page sample, and determining according to a result of the software error correction to obtain a sample tag, where if the software error correction is successful, obtaining a first sample tag for indicating that the flash page sample has no error correction requirement.
As shown in fig. 7, fig. 7 is another optional flowchart of a method for managing startup of a memory according to an embodiment of the present application, where the method in fig. 7 may include, but is not limited to, steps S601 to S602.
Step S601, when the starting result is a first starting result or a fourth starting result, adding a bad page label to the corresponding flash memory page;
in some embodiments, in the above method, if the starting result obtained by a certain flash page is the first starting result or the fourth starting result, a bad page tag may be added to the starting result, which indicates that the flash page is in error.
Step S602, determining that the flash memory page is an invalid page according to the bad page tag.
In some embodiments, when performing the rebuilding operation on each flash page, the flash memory may determine that the corresponding flash page is an invalid page according to the bad page tag, and does not process the flash page including the bad page tag. That is, when the flash memory is started, the flash memory pages which are invalid due to errors can be skipped according to the bad page tags, so that the reconstruction speed of the flash memory can be further improved.
As shown in fig. 8, fig. 8 is a flowchart of a method for managing the startup of a memory according to an embodiment of the present application, where the method in fig. 8 may include, but is not limited to, steps S701 to S704.
Step S701, counting the number of the first starting results to obtain a first target result value;
in some embodiments, after the completion of the flash memory rebuilding, the starting result is counted as the number of first starting results, and a first target result value is obtained, where the first result value is used to represent the number of flash memory pages without error correction requirements after the completion of the flash memory rebuilding.
Step S702, counting the number of the second starting results and the number of the third starting results to obtain a second target result value;
in some embodiments, after the reconstruction of the flash memory is completed once, the number of the starting results is counted to obtain a second target result value, where the second result value is used to represent the number of flash memory pages having error correction requirements after the reconstruction of the flash memory is completed once.
Step S703, performing a proportional operation on the first target result value and the second target result value to obtain a target result proportional value;
in some embodiments, the first target result value and the second target result value are subjected to a proportional operation to obtain a target result proportional value, where the target result proportional value is used to represent a ratio of the number of flash memory pages with error correction requirements to the number of flash memory pages without error correction requirements after completing one flash memory reconstruction, and the target result proportional value can reflect the execution degree and the accuracy after performing flash memory reconstruction according to the error correction range.
In step S704, if the target result proportion value exceeds the target result proportion threshold value, the error correction range is redetermined according to the sample bit data of the plurality of flash memory page samples.
In some embodiments, a target result proportion threshold is preset, where the target result proportion threshold represents a proportion value of a flash memory page with error correction requirement and a flash memory page without error correction requirement expected to be reached in the flash memory reconstruction process, and if the target result proportion does not reach the preset target result proportion threshold, it indicates that the error correction range does not meet the actual error correction requirement, and the error correction range should be readjusted and determined.
For example, after completing one flash reconstruction, the target result proportion value obtained is 95%, and the preset target result proportion threshold value is 90%, that is, the original error correction range is set to be too small, so that the error correction range needs to be readjusted, for example, some fault tolerance can be appropriately increased, so that more flash pages can be corrected, and the actual flash reconstruction needs are also more met.
In some embodiments, the flash page sample may be obtained again and the error correction range may be redetermined according to the specific implementation manner of determining the error correction range through the flash page sample, or the error tolerance may be increased based on the original error correction range, so that the updated error correction range may be better used as a basis for flash reconstruction.
It should be noted that, the manner of redefining the error correction range may be varied, and the embodiment of the present application is merely described in the preferred embodiment, and is not limited thereto.
It can be understood that the error correction range adjusted by continuous updating can be more in line with the actual flash memory reconstruction, and the starting speed of the memory can be further improved in the continuous optimization process.
As shown in fig. 9, fig. 9 is a schematic diagram of a functional module of a method for managing startup of a memory according to an embodiment of the present application, and the embodiment of the present application further provides a system for managing startup of a memory, which can implement the method for managing startup of a memory, where the system for managing startup of a memory includes:
the bit data acquisition module 801 is configured to acquire bit data in any flash page, and parse the bit data to obtain a target bit value and a corresponding target proportion value;
an error correction range obtaining module 802, configured to obtain an error correction range of the target bit value;
the error correction module 803 is configured to determine that the flash memory page has no error correction requirement if the target proportion value is outside the error correction range, obtain a first starting result, and stop the starting operation of the flash memory page according to the first starting result; if the target proportion value is in the error correction range, determining that the flash memory page has error correction requirements, executing hardware error correction operation on the bit data, obtaining a second starting result when the hardware error correction is successful, and completing the starting operation of the flash memory page according to the second starting result; if the hardware error correction fails, executing software error correction operation on the bit data, obtaining a third starting result when the software error correction is successful, and completing the starting operation of the flash memory page according to the third starting result; if the software error correction fails, a fourth starting result is obtained, and the starting operation of the flash memory page is stopped according to the fourth starting result.
The specific implementation of the memory startup management system is basically the same as the specific embodiment of the memory startup management method, and will not be described herein. On the premise of meeting the requirements of the embodiment of the application, the starting management system of the memory can also be provided with other functional modules so as to realize the starting management method of the memory in the embodiment.
The embodiment of the application also provides electronic equipment, which comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the starting management method of the memory when executing the computer program. The electronic equipment can be any intelligent terminal including a tablet personal computer, a vehicle-mounted computer and the like.
As shown in fig. 10, fig. 10 is a schematic hardware structure of an electronic device according to an embodiment of the present application, where the electronic device includes:
the processor 901 may be implemented by a general purpose CPU (central processing unit), a microprocessor, an application specific integrated circuit (ApplicationSpecificIntegratedCircuit, ASIC), or one or more integrated circuits, etc. for executing related programs to implement the technical solution provided by the embodiments of the present application;
The memory 902 may be implemented in the form of read-only memory (ReadOnlyMemory, ROM), static storage, dynamic storage, or random access memory (RandomAccessMemory, RAM). The memory 902 may store an operating system and other application programs, and when the technical solutions provided in the embodiments of the present disclosure are implemented by software or firmware, relevant program codes are stored in the memory 902, and the processor 901 invokes a startup management method for executing the memory of the embodiments of the present disclosure;
an input/output interface 903 for inputting and outputting information;
the communication interface 904 is configured to implement communication interaction between the device and other devices, and may implement communication in a wired manner (e.g. USB, network cable, etc.), or may implement communication in a wireless manner (e.g. mobile network, WIFI, bluetooth, etc.);
a bus 905 that transfers information between the various components of the device (e.g., the processor 901, the memory 902, the input/output interface 903, and the communication interface 904);
wherein the processor 901, the memory 902, the input/output interface 903 and the communication interface 904 are communicatively coupled to each other within the device via a bus 905.
The embodiment of the application also provides a computer readable storage medium, which stores a computer program, and the computer program realizes the method for managing the starting of the memory when being executed by a processor.
The memory, as a non-transitory computer readable storage medium, may be used to store non-transitory software programs as well as non-transitory computer executable programs. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory optionally includes memory remotely located relative to the processor, the remote memory being connectable to the processor through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The embodiments described in the embodiments of the present application are for more clearly describing the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application, and those skilled in the art can know that, with the evolution of technology and the appearance of new application scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.
It will be appreciated by persons skilled in the art that the embodiments of the application are not limited by the illustrations, and that more or fewer steps than those shown may be included, or certain steps may be combined, or different steps may be included.
The above described apparatus embodiments are merely illustrative, wherein the units illustrated as separate components may or may not be physically separate, i.e. may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Those of ordinary skill in the art will appreciate that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof.
The terms "first," "second," "third," "fourth," and the like in the description of the application and in the above figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be understood that in the present application, "at least one (item)" and "a plurality" means one or more, and "a plurality" means two or more. "and/or" for describing the association relationship of the association object, the representation may have three relationships, for example, "a and/or B" may represent: only a, only B and both a and B are present, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.
In the several embodiments provided by the present application, it should be understood that the disclosed systems and methods may be implemented in other ways. For example, the system embodiments described above are merely illustrative, e.g., the division of the above elements is merely a logical functional division, and there may be additional divisions in actual implementation, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including multiple instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method of the various embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing a program.
The preferred embodiments of the present application have been described above with reference to the accompanying drawings, and are not thereby limiting the scope of the claims of the embodiments of the present application. Any modifications, equivalent substitutions and improvements made by those skilled in the art without departing from the scope and spirit of the embodiments of the present application shall fall within the scope of the claims of the embodiments of the present application.
Claims (10)
1. A method for managing the start-up of a memory, wherein the method is applied to the memory, the memory comprises a flash memory chip, the flash memory chip comprises a plurality of flash memory blocks, the flash memory blocks comprise a plurality of flash memory pages, and the method comprises:
acquiring bit data in any flash memory page, and analyzing the bit data to obtain a target bit value and a corresponding target proportion value;
acquiring an error correction range of the target bit value;
if the target proportion value is out of the error correction range, determining that the flash memory page has no error correction requirement, obtaining a first starting result, and stopping starting operation of the flash memory page according to the first starting result;
if the target proportion value is in the error correction range, determining that the flash memory page has error correction requirements, executing hardware error correction operation on the bit data, obtaining a second starting result when the hardware error correction is successful, and completing the starting operation of the flash memory page according to the second starting result;
If the hardware error correction fails, executing software error correction operation on the bit data, obtaining a third starting result when the software error correction is successful, and completing the starting operation of the flash memory page according to the third starting result;
and if the software error correction fails, a fourth starting result is obtained, and the starting operation of the flash memory page is stopped according to the fourth starting result.
2. The method for managing the start of a memory according to claim 1, wherein said parsing the bit data to obtain a target bit value and a corresponding target scale value comprises:
analyzing to obtain a first bit value and a second bit value according to the bit data, wherein the first bit value is used for representing one minimum information value of the flash memory page, and the second bit value is used for representing the other minimum information value of the flash memory page;
and selecting any one from the first bit value and the second bit value to perform proportion calculation with the bit data, so as to obtain a target proportion value.
3. The startup management method of a memory according to claim 1, wherein the acquiring the error correction range of the target bit value includes:
obtaining sample labels corresponding to each flash memory page sample;
If the sample labels comprise a first sample label representing that the flash page sample has no error correction requirement or a second sample label representing that the flash page sample has error correction requirement, summarizing the sample labels to obtain the sample label number;
summarizing the first sample tags to obtain a first sample tag number, and performing proportional operation on the first sample tag number and the sample tag number to obtain a first sample proportional value;
summarizing the second sample tags to obtain a second sample tag number, and performing proportional operation on the second sample tag number and the sample tag number to obtain a second sample proportional value;
determining that the first sample ratio value and the second sample ratio value are a first boundary value and a second boundary value of the error correction range, respectively, and determining that a range between the first boundary value and the second boundary value is the error correction range.
4. A method of startup management of a memory according to claim 1 or 3, wherein the obtaining the error correction range of the target bit value includes:
acquiring sample bit data of the corresponding flash memory page sample when the sample tag is the first sample tag, or acquiring sample bit data of the corresponding flash memory page sample when the sample tag is the second sample tag;
Obtaining a plurality of sample proportion values according to the sample bit data;
selecting a plurality of median or mode values of the sample proportion values to obtain a first interval endpoint value, performing difference operation on a sample base number and the first interval endpoint value to obtain a second interval endpoint value, determining that the first interval endpoint value and the second interval endpoint value are a third boundary value and a fourth boundary value of the error correction range respectively, and determining that a range between the third boundary value and the fourth boundary value is the error correction range;
or, performing an average operation or a weighting operation on the plurality of sample proportion values to obtain a third interval endpoint value, performing a difference operation on a sample base number and the third interval endpoint value to obtain a fourth interval endpoint value, determining that the third interval endpoint value and the fourth interval endpoint value are respectively a fifth boundary value and a sixth boundary value of the error correction range, and determining that a range between the fifth boundary value and the sixth boundary value is the error correction range.
5. The method for managing the startup of the memory according to claim 3 or 4, wherein after the obtaining the sample tag corresponding to each flash page sample, further comprises:
If the sample label is empty, executing the hardware error correction operation on the flash memory page samples one by one, and obtaining a second sample label for representing that the flash memory page samples have error correction requirements when the hardware error correction is successful;
and if the hardware error correction fails, performing software error correction operation on the sample bit data, obtaining a second sample label for representing that the flash page sample has error correction requirements when the software error correction is successful, and obtaining the first sample label when the software error correction fails.
6. The startup management method of a memory according to claim 1, characterized in that the method further comprises:
when the starting result is the first starting result or the fourth starting result, adding a bad page label for the corresponding flash memory page;
and determining the flash memory page as an invalid page according to the bad page tag.
7. The startup management method of a memory according to claim 1, wherein the method presets a target result proportion threshold, the method further comprising:
counting the number of the first starting results to obtain a first target result value;
counting the number of the second starting results and the number of the third starting results to obtain a second target result value;
Proportional operation is carried out on the first target result value and the second target result value, and a target result proportional value is obtained;
and if the target result proportion value exceeds the target result proportion threshold value, re-determining the error correction range according to the sample bit data of the flash memory page samples.
8. A startup management system for a memory, comprising:
the data acquisition module is used for acquiring bit data in any flash memory page, and analyzing the bit data to obtain a target bit value and a corresponding target proportion value;
an error correction module, configured to obtain an error correction range of the target bit value; if the target proportion value is out of the error correction range, determining that the flash memory page has no error correction requirement, obtaining a first starting result, and stopping starting operation of the flash memory page according to the first starting result; if the target proportion value is in the error correction range, determining that the flash memory page has error correction requirements, executing hardware error correction operation on the bit data, obtaining a second starting result when the hardware error correction is successful, and completing the starting operation of the flash memory page according to the second starting result; if the hardware error correction fails, executing software error correction operation on the bit data, obtaining a third starting result when the software error correction is successful, and completing the starting operation of the flash memory page according to the third starting result; and if the software error correction fails, a fourth starting result is obtained, and the starting operation of the flash memory page is stopped according to the fourth starting result.
9. An electronic device comprising a memory storing a computer program and a processor implementing the method of boot management of the memory according to any one of claims 1 to 7 when the computer program is executed by the processor.
10. A computer-readable storage medium storing a computer program, characterized in that the computer program, when executed by a processor, implements the startup management method of the memory according to any one of claims 1 to 7.
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| CN106415502A (en) * | 2014-12-12 | 2017-02-15 | 华为技术有限公司 | Data storage method and device |
| CN113470728A (en) * | 2021-06-29 | 2021-10-01 | 成都佰维存储科技有限公司 | Error correction capability test method and device, readable storage medium and electronic equipment |
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