CN116666302A - Shallow trench isolation structure, preparation method thereof and semiconductor structure - Google Patents

Shallow trench isolation structure, preparation method thereof and semiconductor structure Download PDF

Info

Publication number
CN116666302A
CN116666302A CN202210153623.7A CN202210153623A CN116666302A CN 116666302 A CN116666302 A CN 116666302A CN 202210153623 A CN202210153623 A CN 202210153623A CN 116666302 A CN116666302 A CN 116666302A
Authority
CN
China
Prior art keywords
layer
oxide layer
substrate
hard mask
oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210153623.7A
Other languages
Chinese (zh)
Inventor
高远皓
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to CN202210153623.7A priority Critical patent/CN116666302A/en
Priority to PCT/CN2022/081487 priority patent/WO2023155263A1/en
Publication of CN116666302A publication Critical patent/CN116666302A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps

Abstract

The application relates to a shallow trench isolation structure, a preparation method thereof and a semiconductor structure. The preparation method comprises providing a substrate, and sequentially laminating a pad oxygen layer and a hard mask layer on the surface of the substrate; etching the pad oxide layer and the substrate by taking the patterned hard mask layer as a mask so as to form an opening in the pad oxide layer and form a groove in the substrate; forming a substrate oxide layer in the groove; forming a first barrier layer, wherein the first barrier layer covers the hard mask layer and the substrate oxide layer; forming a first oxide layer, wherein the first oxide layer covers the first barrier layer; removing the first blocking layer and the first oxide layer on the upper surface of the hard mask layer; and removing the pad oxygen layer and the hard mask layer on the upper surface of the substrate to form a second barrier layer. The application can improve the isolation performance of the shallow trench isolation structure so as to improve the use reliability and yield of the semiconductor structure.

Description

Shallow trench isolation structure, preparation method thereof and semiconductor structure
Technical Field
The present application relates to the field of semiconductor integrated circuit manufacturing technology, and in particular, to a shallow trench isolation structure, a method for manufacturing the same, and a semiconductor structure.
Background
With the development of semiconductor technology, the feature size of devices in integrated circuits is becoming smaller. After the semiconductor process has entered the deep submicron stage, isolation and planarization processes are becoming increasingly important in order to achieve high density and high performance devices and semiconductor structures.
At present, the shallow trench isolation (Shallow Trench Isolation, STI for short) process has excellent isolation performance, and has gradually become one of the mainstream isolation technologies for isolating the active area of the device.
However, in the related art, the formation of the shallow trench isolation structure is often not separated from the use of the hard mask layer and the pad oxide layer. For example, a pad oxide layer and a hard mask layer are sequentially laminated on the surface of a substrate; then etching the hard mask layer, the pad oxide layer and the substrate in sequence to form a groove in the substrate; filling oxide in the groove to form a shallow groove isolation structure; and finally removing the hard mask layer and the pad oxide layer. Because the material of the pad oxide layer and the material of the shallow trench isolation structure contain oxide, in the process of removing the pad oxide layer, the corner or boundary of the shallow trench isolation structure is easy to be etched, so that the local edge of the shallow trench isolation structure has defects such as pits, holes or sharp corners. Thereby affecting the isolation performance of the shallow trench isolation structure and further affecting the electrical performance of the semiconductor structure, such as occurrence of defects of leakage current, narrow channel effect and the like.
Disclosure of Invention
Based on the above, the embodiment of the application provides a shallow trench isolation structure, a preparation method thereof and a semiconductor structure, which can ensure the surface quality of the shallow trench isolation structure so as to improve the isolation performance of the shallow trench isolation structure, thereby improving the electrical performance of the semiconductor structure and improving the use reliability and yield of the semiconductor structure.
In order to achieve the above objective, in one aspect, some embodiments of the present application provide a method for manufacturing a shallow trench isolation structure, which includes the following steps.
Providing a substrate, and sequentially laminating an oxygen-filling layer and a hard mask layer on the surface of the substrate.
And etching the pad oxide layer and the substrate by taking the patterned hard mask layer as a mask so as to form an opening in the pad oxide layer and form a groove in the substrate.
A substrate oxide layer is formed within the trench.
A first barrier layer is formed overlying the hard mask layer and the substrate oxide layer.
A first oxide layer is formed, and the first oxide layer covers the first barrier layer.
And removing the first blocking layer and the first oxide layer on the upper surface of the hard mask layer.
And removing the pad oxygen layer and the hard mask layer on the upper surface of the substrate to form a second barrier layer.
In some embodiments, the method of making further comprises the following steps.
Oxidizing a portion of the surface of the second barrier layer and the substrate to form a second oxide layer.
And removing the second oxide layer and part of the substrate oxide layer so that the substrate oxide layer remained in the groove forms a shallow groove isolation structure.
In some embodiments, removing the second oxide layer and a portion of the substrate oxide layer includes: and cleaning the structure obtained after the second oxide layer is formed by using hydrofluoric acid diluted solution so as to remove the second oxide layer and part of the substrate oxide layer.
In some embodiments, a substrate oxide layer is formed within the trench, including the following steps.
Oxide is deposited within the pattern of trenches, openings, and hard mask layers.
Oxide within the pattern of openings and hard mask layer is removed so that the oxide remaining within the trenches forms the substrate oxide layer.
In some embodiments, forming a substrate oxide layer within the trench further comprises: after depositing oxide within the pattern of trenches, openings, and hard mask layers, exposed surfaces of the hard mask layers and oxide are polished using a chemical mechanical polishing process prior to removing the oxide within the pattern of openings and hard mask layers.
In some embodiments, removing the first barrier layer and the first oxide layer from the upper surface of the hard mask layer and removing the pad oxide layer and the hard mask layer from the upper surface of the substrate to form a second barrier layer includes the following steps.
And removing the parts of the first barrier layer and the first oxide layer, which are positioned on the upper surface of the hard mask layer, so as to form an intermediate barrier layer and an intermediate oxide layer.
And removing the hard mask layer.
And removing the pad oxide layer and the intermediate oxide layer to form a second barrier layer on the intermediate barrier layer.
In some embodiments, a chemical mechanical polishing process is used to remove portions of both the first barrier layer and the first oxide layer on the upper surface of the hard mask layer to form an intermediate barrier layer and an intermediate oxide layer.
In some embodiments, a wet etch process is used to remove the hard mask layer.
In some embodiments, a wet etch process is used to remove the pad oxide layer and the intermediate oxide layer.
In some embodiments, the material of the pad oxide layer and the first oxide layer is the same.
In some embodiments, the material of the first barrier layer comprises polysilicon.
In some embodiments, the first barrier layer has a thickness in the range of 1nm to 3nm.
In another aspect, some embodiments of the present application provide a shallow trench isolation structure, which is prepared by using the preparation method described in some embodiments above.
In yet another aspect, some embodiments of the present application provide a semiconductor structure comprising: a substrate, a plurality of transistors, and shallow trench isolation structures as described in some embodiments above. Wherein the substrate has a trench. The shallow trench isolation structure is arranged in the trench and isolates a plurality of active areas in the substrate. The transistors are disposed in the corresponding active regions.
In some embodiments, a transistor includes: a metal oxide semiconductor field effect transistor. The gate length of the metal oxide semiconductor field effect transistor is less than 50nm.
In the embodiment of the application, after the pad oxygen layer and the hard mask layer are formed, the patterned hard mask layer is used as a mask to etch the pad oxygen layer and the substrate, so that an opening can be formed in the pad oxygen layer, and a groove can be formed in the substrate. And then forming a substrate oxide layer in the groove, forming a first blocking layer on the substrate oxide layer and the hard mask layer, and forming a first oxide layer on the first blocking layer, so that the first blocking layer and the first oxide layer on the upper surface of the hard mask layer can be removed, and the first blocking layer and the first oxide layer on the upper surface of the substrate oxide layer are reserved. Based on this, after the pad oxide layer and the hard mask layer on the upper surface of the substrate are subsequently removed, a second barrier layer may be formed based on the first barrier layer. For example, in the process of removing the pad oxide layer, the first oxide layer on the upper surface of the substrate oxide layer and the pad oxide layer may be removed simultaneously, so that the first barrier layer on the upper surface of the substrate oxide layer forms a second barrier layer.
It can be seen that the first barrier layer and the first oxide layer on the upper surface of the substrate oxide layer can be used to protect and isolate the substrate oxide layer during the process of removing the pad oxide layer and the hard mask layer. And after the pad oxide layer and the hard mask layer are removed, the second barrier layer covers the substrate oxide layer, so that the phenomenon of overetching at the edge of the substrate oxide layer due to accumulation of etching liquid can be effectively avoided. Therefore, defects such as pits, holes or sharp corners and the like of the shallow trench isolation structure formed by the substrate oxide layer can be avoided. Thus, the shallow trench isolation structure with higher molding surface quality can be obtained, so that the edge integrity of the shallow trench isolation structure is ensured.
In addition, since the second barrier layer covers the exposed surface of the oxide layer of the substrate, the second barrier layer protrudes from the upper surface of the substrate. Therefore, the second barrier layer may be subjected to an oxidation treatment so that a part of the surface of the second barrier layer and the substrate may be oxidized and converted into a second oxide layer, and then removed by cleaning the oxidized surface, to ensure that a substrate having a flat upper surface is obtained. Thereby simplifying the preparation process of the shallow trench isolation structure and further ensuring that the shallow trench isolation structure has higher surface quality.
Therefore, the embodiment of the application can ensure the surface quality of the formed shallow trench isolation structure so as to improve the isolation performance of the shallow trench isolation structure, thereby improving the electrical performance of the semiconductor structure and improving the use reliability and yield of the semiconductor structure.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a schematic flow chart of a method for fabricating a shallow trench isolation structure according to an embodiment;
FIG. 2 is a schematic cross-sectional view of the structure after forming the pad oxide layer and the hard mask layer according to one embodiment;
FIG. 3 is a schematic cross-sectional view of a structure after formation of a photoresist layer according to one embodiment;
FIG. 4 is a schematic cross-sectional view of the structure after forming a patterned hard mask layer, as provided in one embodiment;
FIG. 5 is a schematic cross-sectional view of the structure after forming a trench, as provided in one embodiment;
FIG. 6 is a flowchart of step S300 provided in an embodiment;
FIG. 7 is a schematic cross-sectional view of the structure after depositing oxide within the pattern of trenches, openings, and hard mask layer, as provided in one embodiment;
FIG. 8 is a schematic cross-sectional view of the resulting structure after formation of a substrate oxide layer, as provided in one embodiment;
FIG. 9 is a flowchart of step S300 provided in another embodiment;
FIG. 10 is a schematic cross-sectional view of the structure after formation of a first barrier layer, as provided in one embodiment;
FIG. 11 is a schematic cross-sectional view of a structure after forming a first oxide layer according to one embodiment;
FIG. 12 is a flowchart of step S600 provided in one embodiment;
FIG. 13 is a schematic cross-sectional view of the structure after forming an intermediate barrier layer and a first intermediate oxide layer, as provided in one embodiment;
FIG. 14 is a schematic cross-sectional view of the structure after forming a second barrier layer and a second intermediate oxide layer according to one embodiment;
FIG. 15 is a schematic cross-sectional view of a structure after removal of a pad oxide layer according to one embodiment;
FIG. 16 is a schematic flow chart of a method for fabricating a shallow trench isolation structure according to another embodiment;
FIG. 17 is a schematic cross-sectional view of a structure after forming a second oxide layer according to one embodiment;
fig. 18 is a schematic cross-sectional view of a structure obtained after forming a shallow trench isolation structure according to an embodiment.
Reference numerals illustrate:
10-substrate, 11-pad oxide layer, 12-hard mask layer, 130-oxide, 13-substrate oxide layer,
14-first barrier layer, 14 '-intermediate barrier layer, 15-first oxide layer, 15' -intermediate oxide layer,
16-a second barrier layer, 17-a second oxide layer, 18-a shallow trench isolation structure,
k-opening, G-trench, 20-photoresist pattern.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Embodiments of the application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the application.
Referring to fig. 1, some embodiments of the present application provide a method for manufacturing a shallow trench isolation structure, which includes the following steps.
S100, providing a substrate, and sequentially laminating an oxygen pad layer and a hard mask layer on the surface of the substrate.
And S200, etching the pad oxygen layer and the substrate by taking the patterned hard mask layer as a mask so as to form an opening in the pad oxygen layer and form a groove in the substrate.
S300, forming a substrate oxide layer in the groove.
S400, forming a first barrier layer, wherein the first barrier layer covers the hard mask layer and the substrate oxide layer.
S500, forming a first oxide layer, wherein the first oxide layer covers the first barrier layer.
And S600, removing the first barrier layer and the first oxide layer on the upper surface of the hard mask layer, and removing the pad oxide layer and the hard mask layer on the upper surface of the substrate to form a second barrier layer.
In the embodiment of the application, after the pad oxygen layer and the hard mask layer are formed, the patterned hard mask layer is used as a mask to etch the pad oxygen layer and the substrate, so that an opening can be formed in the pad oxygen layer, and a groove can be formed in the substrate. And then forming a substrate oxide layer in the groove, forming a first blocking layer on the substrate oxide layer and the hard mask layer, and forming a first oxide layer on the first blocking layer, so that the first blocking layer and the first oxide layer on the upper surface of the hard mask layer can be removed, and the first blocking layer and the first oxide layer on the upper surface of the substrate oxide layer are reserved. Based on this, after the pad oxide layer and the hard mask layer on the upper surface of the substrate are subsequently removed, a second barrier layer may be formed based on the first barrier layer.
It can be seen that the first barrier layer and the first oxide layer on the upper surface of the substrate oxide layer can be used to protect and isolate the substrate oxide layer during the process of removing the pad oxide layer and the hard mask layer. And after the pad oxide layer and the hard mask layer are removed, the second barrier layer formed on the substrate oxide layer covers the substrate oxide layer, so that overetching caused by accumulation of etching liquid at the edge of the substrate oxide layer can be effectively avoided. Therefore, defects such as pits, holes or sharp corners and the like of the shallow trench isolation structure formed by the substrate oxide layer can be avoided. Thus, the shallow trench isolation structure with higher molding surface quality can be obtained, so that the edge integrity of the shallow trench isolation structure is ensured.
In addition, the second barrier layer covers the exposed surface of the oxide layer of the substrate, i.e. the second barrier layer protrudes from the upper surface of the substrate. This facilitates the oxidation treatment of the second barrier layer to convert a portion of the surface of the second barrier layer and the substrate to a second oxide layer, which is then removed by cleaning the oxide surface to ensure that a substrate having a planar upper surface is obtained. Thereby simplifying the preparation process of the shallow trench isolation structure and further ensuring that the shallow trench isolation structure has higher surface quality.
Therefore, the embodiment of the application can ensure the surface quality of the formed shallow trench isolation structure so as to improve the isolation performance of the shallow trench isolation structure, thereby improving the electrical performance of the semiconductor structure and improving the use reliability and yield of the semiconductor structure.
In step S100, referring to S100 in fig. 1 and fig. 2, a substrate 10 is provided, and an oxygen pad layer 11 and a hard mask layer 12 are sequentially stacked on a surface of the substrate 10.
In some embodiments, the substrate 10 may be constructed of a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate 10 may have a single-layer structure or a multilayer structure. For example, the substrate 10 may be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrate or II/VI semiconductor substrate. Alternatively, and also for example, the substrate 10 may be a layered substrate comprising a material such as Si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.
In one example, substrate 10 includes, but is not limited to, a silicon substrate or a silicon-based substrate.
In one example, pad Oxide layer 11 includes, but is not limited to, silicon dioxide (SiO 2 ) A layer.
In some embodiments, the pad oxide layer 11 may be formed as a transition buffer layer between the hard mask layer 12 and the substrate 10 using a Low Pressure Chemical Vapor Deposition (LPCVD), a Plasma Enhanced Chemical Vapor Deposition (PECVD), an Atomic Layer Chemical Vapor Deposition (ALCVD), or the like.
In one example, the hard mask layer 12 includes, but is not limited to, a silicon nitride layer. For example, the hard mask layer 12 may be a silicon oxynitride layer.
In some embodiments, the hard mask layer 12 may be formed using a High Density Plasma Chemical Vapor Deposition (HDPCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD) process as a mask for the trenches on the subsequent substrate 10 and patterned by a patterning process.
Illustratively, as shown in fig. 3, a photoresist material is coated on the upper surface of the hard mask layer 12 and subjected to a photolithography process such as exposure, development, etc. to form a photoresist pattern 20 defining the trench locations and having openings. As such, the hard mask layer 12 may be etched, for example, using reactive ion etching or plasma etching, based on the photoresist pattern 20 to form a patterned hard mask layer 12, such as shown in fig. 4.
In step S200, referring to S200 in fig. 1 and fig. 4 and 5, the patterned hard mask layer 12 is used as a mask to etch the pad oxide layer 11 and the substrate 10, so as to form an opening K in the pad oxide layer 11 and a trench G in the substrate 10.
It will be appreciated that the etching of the pad oxide layer 11 and the substrate 10 in step S200 includes wet etching or dry etching, wherein the dry etching includes at least any one of Reactive Ion Etching (RIE), inductively coupled plasma etching (ICP), or high-concentration plasma etching (HDP). In the embodiment of the present application, the etching methods of the pad oxide layer 11 and the substrate 10 may be the same or different.
In some embodiments, the oxygen-filled layer 11 may be etched using reactive ions or plasma.
In some embodiments, the substrate 10 may be etched using a fluorine-containing etching gas, or wet etched using a hydrofluoric acid solution.
In addition, the number and the forming positions of the openings K and the trenches G may be selected according to the active regions to be isolated. The embodiment of the present application is not limited thereto.
In step S300, referring to S300 in fig. 1 and fig. 6 to 9, a substrate oxide layer 13 is formed in the trench G.
As illustrated in fig. 6, 7, and 8, step S300 includes the following steps.
S310, depositing oxide 130 within the pattern of trench G, opening K and hard mask layer 12.
In one example, oxide 130 includes, but is not limited to, silicon dioxide (SiO 2 )。
In some embodiments, oxide 130 may be deposited using a high density plasma chemical vapor deposition (HDP-CVD) or the like process.
S320, the Oxide 130 located in the pattern of the opening K and the hard mask layer 12 is removed, so that the Oxide 130 remaining in the trench G constitutes a substrate Oxide layer (Liner Oxide) 13.
In the embodiment of the present application, the substrate oxide layer 13 is formed by depositing the oxide 130 in the patterns of the trench G, the opening K and the hard mask layer 12, and then removing the oxide 130 in the patterns of the opening K and the hard mask layer 12. In this way, the compactness of the material of the substrate oxide layer 13 can be improved, and the forming surface of the substrate oxide layer 13 is ensured to be flush with the upper surface of the substrate 10.
In some embodiments, referring to fig. 7, 8 and 9, after depositing the oxide 130 in the pattern of the trench G, the opening K and the hard mask layer 12, the step S300 further includes the following steps before removing the oxide 130 in the pattern of the opening K and the hard mask layer 12.
S315, polishing the exposed surfaces of the hard mask layer 12 and the oxide 130 by using a chemical mechanical polishing process.
In this manner, the exposed surfaces of the hard mask layer 12 and the oxide 130 are ensured to be flush and flat, so as to facilitate accurate etching of the oxide 130 to be flush with the upper surface of the substrate 10.
In step S400, referring to S400 in fig. 1 and fig. 10, a first barrier layer 14 is formed, and the first barrier layer 14 covers the hard mask layer 12 and the substrate oxide layer 13.
It will be appreciated that after formation of the substrate oxide layer 13, the upper surface of the substrate oxide layer 13 may be coplanar with the upper surface of the substrate 10. Thus, after the first barrier layer 14 is formed, the portion of the first barrier layer 14 covering the substrate oxide layer 13 is located in the opening K of the pad oxide layer 11 and the pattern of the hard mask layer 12.
In some embodiments, the material of the first barrier layer 14 comprises polysilicon. In this way, it is convenient to perform the oxidation treatment on the second barrier layer 16 after the second barrier layer 16 is formed based on the first barrier layer 14, and remove the second barrier layer by removing the oxidized surface, thereby simplifying the preparation process of the shallow trench isolation structure and ensuring the surface quality of the formed shallow trench isolation structure.
In some embodiments, the thickness of the first barrier layer 14 may be selected as desired. For example, the thickness of the first barrier layer 14 may be 1nm to 3nm, for example, 1nm, 2nm or 3nm. But is not limited thereto.
Here, if the thickness of the first barrier layer 14 is thin, the structure of the first barrier layer 14 is easily unstable, for example, it is difficult to stably form, which is disadvantageous in that the second barrier layer 16 having a predetermined shape is formed based on the first barrier layer 14 after the etching through a plurality of times. In addition, if the thickness of the first barrier layer 14 is large, it takes a long time to perform the oxidation treatment of the second barrier layer 16 formed by the first barrier layer 14 in the later stage, which is disadvantageous in improving the production efficiency.
Therefore, in the embodiment of the present application, the thickness of the first barrier layer 14 is set within the range of 1nm to 3nm, so that the concave surface of the first barrier layer 14 due to the pattern of the openings K of the pad oxide layer 11 and the hard mask layer 12 exists on the molding surface (i.e., the first barrier layer 14 has the concave recess due to the pattern of the openings K of the pad oxide layer 11 and the hard mask layer 12), so that the second barrier layer 16 with the U-shaped structure can be formed later. And, it is convenient to partially remove the first barrier layer 14 to form the second barrier layer 16 and to oxidize the second barrier layer 16, so as to be beneficial to improving the production efficiency.
In step S500, referring to S500 in fig. 1 and fig. 11, a first oxide layer 15 is formed, and the first oxide layer 15 covers the first barrier layer 14.
Here, after the first oxide layer 15 is formed, the recess of the first barrier layer 14 formed by the opening K of the pad oxide layer 11 and the hard mask layer 12 may be filled with a portion of the material of the first oxide layer 15.
In some embodiments, the first oxide layer 15 and the pad oxide layer 11 are the same material, e.g., both are silicon dioxide. In this way, the pad oxide layer 11 and the first oxide layer 15 are removed by the same process, so as to simplify the manufacturing process of the shallow trench isolation structure.
In step S600, referring to S600 in fig. 1 and fig. 12 to 15, the first barrier layer 14 and the first oxide layer 15 on the upper surface of the hard mask layer 12 are removed, and the pad oxide layer 11 and the hard mask layer 12 on the upper surface of the substrate 10 are removed to form the second barrier layer 16.
For example, referring to fig. 12 to 15, step S600 includes the following steps.
At S610, as shown in fig. 13, portions of both the first barrier layer 14 and the first oxide layer 15 on the upper surface of the hard mask layer 12 are removed to form an intermediate barrier layer 14 'and an intermediate oxide layer 15'.
In some embodiments, a chemical mechanical polishing process may be used to remove portions of both the first barrier layer 14 and the first oxide layer 15 that are located on the upper surface of the hard mask layer 12 to form an intermediate barrier layer 14 'and an intermediate oxide layer 15', and to ensure that the upper surfaces of the intermediate barrier layer 14 'and the intermediate oxide layer 15' are located on the same plane.
Here, the polishing liquid and the polishing time used in the chemical mechanical polishing process may be selected and set according to actual requirements, which is not limited in the embodiment of the present application.
S620, as shown in fig. 14, the hard mask layer 12 is removed.
In some embodiments, a wet etch process is used to remove the hard mask layer 12.
For example, the hard mask layer 12 is wet etched using a hot phosphoric acid solution, which may be at a temperature of 150-170 ℃.
It will be appreciated that after the removal of the hard mask layer 12, a first pure water cleaning process may also be performed to remove residual hot phosphoric acid. Since the temperature of the hot phosphoric acid is too high, if the substrate 10 is directly put into a room temperature water tank for cleaning, there is a risk of chipping. Thus, the temperature of the first pure water cleaning process may be 50 ℃ to 70 ℃.
S630, as shown in fig. 15, the pad oxide layer 11 and the intermediate oxide layer 15 'are removed so that the intermediate barrier layer 14' forms the second barrier layer 16.
In some embodiments, the pad oxide layer 11 and the intermediate oxide layer 15' are removed using a wet etching process.
For example, the pad oxide layer 11 and the intermediate oxide layer 15' are etched using hydrofluoric acid.
In the embodiment of the present application, after the first oxide layer 15 is formed, a portion of the material of the first oxide layer 15 may be used to fill up the recess in the first barrier layer 14 formed by the openings K of the pad oxide layer 11 and the hard mask layer 12. In this way, after removing the portions of the first barrier layer 14 and the first oxide layer 15 on the upper surface of the hard mask layer 12, the intermediate barrier layer 14 'has a U-shaped thin-wall structure, and the intermediate oxide layer 15' fills up the intermediate barrier layer 14', so that the intermediate barrier layer 14' can be supported, thereby being beneficial to ensuring the structural stability of the intermediate barrier layer 14 'in the subsequent process of removing the hard mask layer 12, the pad oxide layer 11 and the intermediate oxide layer 15'.
It should be noted that the second barrier layer 16 may be formed in other manners. For example, first, the portions of both the first barrier layer 14 and the first oxide layer 15 on the upper surface of the hard mask layer 12 are removed to form an intermediate barrier layer 14 'and a first intermediate oxide layer 15'; then, the hard mask layer 12, and the portions of the intermediate barrier layer 14 'and the first intermediate oxide layer 15' protruding from the upper surface of the pad oxide layer 11 are removed to form a second barrier layer 16 and a second intermediate oxide layer; finally, the pad oxide layer 11 and the second intermediate oxide layer are removed. But is not limited thereto, so that the second barrier layer 16 is formed to effectively isolate the substrate oxide layer 13.
In addition, in some embodiments, the removal of the above-described layer structures may also be achieved using a dry etching process.
It should be noted that, in some embodiments, referring to fig. 16, the method for manufacturing the shallow trench isolation structure further includes the following steps.
And S700, oxidizing a part of the surfaces of the second barrier layer and the substrate to form a second oxide layer.
S800, removing the second oxide layer and part of the substrate oxide layer so that the substrate oxide layer remained in the groove forms a shallow groove isolation structure.
In the embodiment of the application, in the process of removing the pad oxygen layer, the first oxide layer on the upper surface of the substrate oxide layer and the pad oxygen layer can be removed synchronously, so that the first barrier layer on the upper surface of the substrate oxide layer forms a second barrier layer. Based on the above, after the second barrier layer and part of the surface of the substrate are oxidized, the second barrier layer and part of the surface of the substrate are oxidized and converted into the second oxide layer, so that the second oxide layer can be removed by cleaning the oxidized surface, the preparation process of the shallow trench isolation structure is simplified, and the shallow trench isolation structure is further ensured to have higher surface quality. And the isolation performance of the shallow trench isolation structure can be further improved, so that the electrical performance of the semiconductor structure is further improved, and the use reliability and yield of the semiconductor structure are effectively improved.
In step S700, referring to S700 in fig. 16 and fig. 17, a portion of the surface of the second barrier layer 16 and the substrate 10 is oxidized to form a second oxide layer 17.
In some embodiments, the resulting structure after forming the second barrier layer 16 is placed in an oxidizing environment, such as by flowing a stream of an oxidizing agent through the resulting structure after forming the second barrier layer 16, and placing the resulting structure in a high temperature environment such that the material of the second barrier layer 16 and a portion of the surface of the substrate 10 is converted from polysilicon or silicon to silicon oxide. The temperature of the high temperature environment can be selected and set according to actual requirements, and the thickness of the oxidized material of the substrate 10 can be selected and set according to actual requirements. The embodiments of the present disclosure are not limited in this regard.
Furthermore, it is understood that an SC1 cleaning process may also be performed to remove impurities from the substrate before oxidizing the second barrier layer 16 and a portion of the surface of the substrate 10 to form the second oxide layer 17. The cleaning solution of the SC1 cleaning process comprises ammonia water, hydrogen peroxide and water, and the ammonia water is as follows: hydrogen peroxide: the volume ratio of water is, for example, 1:2:100 to 1:2:10. The concentration of ammonia is, for example, 27%, and the concentration of hydrogen peroxide is, for example, 30%. The temperature of the SC1 cleaning solution is, for example, 20℃to 50 ℃. The cleaning time of the SC1 cleaning liquid is, for example, 0.5 to 10 minutes. Also, after the SC1 cleaning process is performed, a second pure water cleaning process may be optionally performed to remove the SC1 solution remaining on the substrate 10. The temperature of the second pure water cleaning process is, for example, 20 to 30 ℃.
In step S800, referring to S800 in fig. 16 and fig. 18, the second oxide layer 17 and a portion of the substrate oxide layer 13 are removed, so that the substrate oxide layer remaining in the trench G forms the shallow trench isolation structure 18.
In some embodiments, removing the second oxide layer 17 and a portion of the substrate oxide layer 13 includes: the structure obtained after the formation of the second oxide layer 17 is cleaned with a diluted solution of hydrofluoric acid to remove the second oxide layer 17 and a portion of the substrate oxide layer 13.
Here, in the diluted hydrofluoric acid solution, the volume ratio of hydrofluoric acid to water is, for example, 1:100 to 1:500. The temperature of the diluted hydrofluoric acid solution is, for example, 15 to 30 ℃. The structure obtained after the second oxide layer 17 is formed is cleaned with a diluted solution of hydrofluoric acid, which may be regarded as removing the second oxide layer 17 and a part of the substrate oxide layer 13 by a wet etching process.
Some embodiments of the present application further provide a shallow trench isolation structure, which is prepared by using the preparation method described in some embodiments above.
Some embodiments of the present application also provide a semiconductor structure, including: a substrate, a plurality of transistors, and shallow trench isolation structures as described in some embodiments above. Wherein the substrate has a trench. The shallow trench isolation structure is arranged in the trench and isolates a plurality of active areas in the substrate. The transistors are disposed in the corresponding active regions.
In some embodiments, the plurality of active regions may be arranged in an array. The active region includes a source region and a drain region. The material of the active region is, for example, polysilicon (poly), and the source and drain regions of the active region are respectively different doped regions of polysilicon. The transistor typically includes a gate, a source, and a drain; wherein the source electrode may be connected to the source region of the active region and the drain electrode may be connected to the drain region of the active region.
In some embodiments, a transistor includes: a Metal-oxide semiconductor field effect transistor (MOSFET) such as an N-type Metal-oxide semiconductor field effect transistor (NMOSFET) or a P-type Metal-oxide semiconductor field effect transistor (PMOSFET).
Illustratively, the gate length of the metal oxide semiconductor field effect transistor is less than 50nm.
The gate length of the mosfet herein refers to the length of the conductive channel that the gate can control, i.e. the distance between the drain and the source.
In the embodiment of the application, the edge of the shallow trench isolation structure is complete, and different active areas can be effectively isolated under the condition that the size scale of the semiconductor structure is smaller, so that reverse narrow channel effect of the metal oxide semiconductor field effect transistor is avoided, and the electrical performance of the metal oxide semiconductor field effect transistor is effectively improved, for example, the switching response speed of the metal oxide semiconductor field effect transistor is effectively improved.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.

Claims (15)

1. The preparation method of the shallow trench isolation structure is characterized by comprising the following steps:
providing a substrate, and sequentially laminating an oxygen-filling layer and a hard mask layer on the surface of the substrate;
etching the pad oxide layer and the substrate by taking the patterned hard mask layer as a mask so as to form an opening in the pad oxide layer and form a groove in the substrate;
forming a substrate oxide layer in the groove;
forming a first barrier layer, wherein the first barrier layer covers the hard mask layer and the substrate oxide layer;
forming a first oxide layer, wherein the first oxide layer covers the first barrier layer;
removing the first blocking layer and the first oxide layer on the upper surface of the hard mask layer;
and removing the pad oxygen layer and the hard mask layer on the upper surface of the substrate to form a second barrier layer.
2. The method for manufacturing a shallow trench isolation structure according to claim 1, further comprising:
oxidizing a portion of the surface of the second barrier layer and the substrate to form a second oxide layer;
and removing the second oxide layer and part of the substrate oxide layer so that the substrate oxide layer remained in the groove forms a shallow groove isolation structure.
3. The method of claim 2, wherein removing the second oxide layer and a portion of the substrate oxide layer comprises:
and cleaning the structure obtained after the second oxide layer is formed by using hydrofluoric acid diluted solution so as to remove the second oxide layer and part of the substrate oxide layer.
4. The method of claim 1, wherein forming a substrate oxide layer in the trench comprises:
depositing an oxide within the pattern of the trench, the opening, and the hard mask layer;
the oxide in the pattern of the opening and the hard mask layer is removed so that the oxide remaining in the trench constitutes the substrate oxide layer.
5. The method of claim 4, wherein forming a substrate oxide layer in the trench, further comprises:
after depositing oxide within the pattern of trenches, the openings, and the hard mask layer, the exposed surfaces of the hard mask layer and the oxide are polished using a chemical mechanical polishing process prior to removing the oxide within the pattern of openings and the hard mask layer.
6. The method of claim 1, wherein removing the first barrier layer and the first oxide layer on the upper surface of the hard mask layer, and removing the pad oxide layer and the hard mask layer on the upper surface of the substrate to form a second barrier layer, comprises:
removing the parts of the first barrier layer and the first oxide layer, which are positioned on the upper surface of the hard mask layer, so as to form an intermediate barrier layer and an intermediate oxide layer;
removing the hard mask layer;
and removing the pad oxide layer and the intermediate oxide layer to enable the intermediate barrier layer to form the second barrier layer.
7. The method of claim 6, wherein a chemical mechanical polishing process is used to remove portions of the first barrier layer and the first oxide layer on the top surface of the hard mask layer to form an intermediate barrier layer and an intermediate oxide layer.
8. The method of claim 6, wherein the hard mask layer is removed by a wet etching process.
9. The method of claim 6, wherein the pad oxide layer and the intermediate oxide layer are removed by a wet etching process.
10. The method of claim 9, wherein the pad oxide layer and the first oxide layer are made of the same material.
11. The method of any one of claims 1 to 10, wherein the material of the first barrier layer comprises polysilicon.
12. The method of any one of claims 1 to 10, wherein the first barrier layer has a thickness in the range of 1nm to 3nm.
13. A shallow trench isolation structure, characterized in that it is prepared by the preparation method according to any one of claims 1 to 12.
14. A semiconductor structure, comprising:
a substrate having a trench;
the shallow trench isolation structure as set forth in claim 13 disposed within said trench; the shallow trench isolation structure isolates a plurality of active areas in the substrate;
and a plurality of transistors; the transistors are disposed in the corresponding active regions.
15. The semiconductor structure of claim 14, wherein the transistor comprises: a metal oxide semiconductor field effect transistor; the gate length of the metal oxide semiconductor field effect transistor is less than 50nm.
CN202210153623.7A 2022-02-18 2022-02-18 Shallow trench isolation structure, preparation method thereof and semiconductor structure Pending CN116666302A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202210153623.7A CN116666302A (en) 2022-02-18 2022-02-18 Shallow trench isolation structure, preparation method thereof and semiconductor structure
PCT/CN2022/081487 WO2023155263A1 (en) 2022-02-18 2022-03-17 Shallow trench isolation structure, preparation method therefor, and semiconductor structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210153623.7A CN116666302A (en) 2022-02-18 2022-02-18 Shallow trench isolation structure, preparation method thereof and semiconductor structure

Publications (1)

Publication Number Publication Date
CN116666302A true CN116666302A (en) 2023-08-29

Family

ID=87577415

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210153623.7A Pending CN116666302A (en) 2022-02-18 2022-02-18 Shallow trench isolation structure, preparation method thereof and semiconductor structure

Country Status (2)

Country Link
CN (1) CN116666302A (en)
WO (1) WO2023155263A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117637597B (en) * 2024-01-26 2024-04-09 合肥晶合集成电路股份有限公司 Manufacturing method of semiconductor structure

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6475875B1 (en) * 2001-07-09 2002-11-05 Chartered Semiconductor Manufacturing Ltd. Shallow trench isolation elevation uniformity via insertion of a polysilicon etch layer
KR100450392B1 (en) * 2002-11-27 2004-09-30 주식회사 하이닉스반도체 Method of forming a isolation layer in a semiconductor device
TWI336918B (en) * 2007-05-08 2011-02-01 Nanya Technology Corp Method of manufacturing the shallow trench isolation structure
CN103839868A (en) * 2014-02-21 2014-06-04 上海华力微电子有限公司 Manufacturing method for shallow-trench isolation structure

Also Published As

Publication number Publication date
WO2023155263A1 (en) 2023-08-24

Similar Documents

Publication Publication Date Title
JP2005150403A (en) Manufacturing method of semiconductor device
JP2008041901A (en) Semiconductor device and its manufacturing method
US20070293045A1 (en) Semiconductor device and method for fabricating the same
US20100129983A1 (en) Method of Fabricating Semiconductor Device
CN116666302A (en) Shallow trench isolation structure, preparation method thereof and semiconductor structure
US20070077723A1 (en) Method of forming shallow trench isolation in a semiconductor device
US6187649B1 (en) Shallow trench isolation process
US6066543A (en) Method of manufacturing a gap filling for shallow trench isolation
US20090098702A1 (en) Method to Form CMOS Circuits Using Optimized Sidewalls
US6979651B1 (en) Method for forming alignment features and back-side contacts with fewer lithography and etch steps
KR20090066406A (en) Method for manufacturing isolation layer of semiconductor device
KR20050002443A (en) Manufacturing method for semiconductor device
US6541342B2 (en) Method for fabricating element isolating film of semiconductor device, and structure of the same
KR100403316B1 (en) Forming method for field oxide of semiconductor device
US20090170276A1 (en) Method of Forming Trench of Semiconductor Device
US7981802B2 (en) Method for manufacturing shallow trench isolation layer of semiconductor device
KR100801733B1 (en) Method of fabricating the trench isolation layer having side oxides with a different thickness
KR100235951B1 (en) Method of forming a device isolation film of semiconductor device
CN108649015B (en) Preparation method of SON device
US7371665B2 (en) Method for fabricating shallow trench isolation layer of semiconductor device
CN116230512A (en) Gate manufacturing method and semiconductor device
KR100520177B1 (en) A method for forming a field oxide of semiconductor device
KR100826776B1 (en) Method for forming isolation layer in semiconductor device
KR20070001553A (en) Method for forming isolation layer of semiconductor device
KR20020054666A (en) A method for forming a field oxide of semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination