CN1166481C - Forming method for high resolution welding lug - Google Patents
Forming method for high resolution welding lug Download PDFInfo
- Publication number
- CN1166481C CN1166481C CNB021244790A CN02124479A CN1166481C CN 1166481 C CN1166481 C CN 1166481C CN B021244790 A CNB021244790 A CN B021244790A CN 02124479 A CN02124479 A CN 02124479A CN 1166481 C CN1166481 C CN 1166481C
- Authority
- CN
- China
- Prior art keywords
- wafer
- soldering
- dielectric layer
- high resolution
- formation method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The present invention relates to a method for forming high resolution welding lugs. The method utilizes a dielectric layer, particularly a release film and a laser perforating mode or the preparation processes of plasma etching to accurately position the forming position of welding lugs arranged on crystal. Therefore, openings which are accurately aligned by high resolution are formed in the dielectric layer, and the welding lugs can be accurately formed on a lower metallic layer of the welding lugs on the crystal. Meanwhile, the space among the welding lugs can be further reduced, and welding lugs with high aspect ratio, thin space and high concentration are successfully formed. In addition, the manufacturing time can be saved greatly, and the cost can be reduced.
Description
Technical field
The present invention relates to a kind of high resolution welding lug formation method, particularly a kind of soldering projection formation method that forms the soldering projection of high aspect ratio (High Aspect Ratio) the highly dense intensity of thin space.
Background technology
The semiconductor chip that contains integrated circuit is an epochmaking assembly in the electronic installation.These semiconductor chips are fixed on one usually to have on the ground of terminal to connect other external circuit.This ground can be single-layer metal lead frame or multilayer printed circuit board.Except the connection that other external circuit of semiconductor chip is provided, ground also provides mechanical support.The outside of semiconductor chip coats can protect semiconductor chip not to be subjected to the influence of external environment and external impacts.
Figure 1A to Fig. 1 G shows a kind of projection formation method of conventional package technology.Shown in Figure 1A; show the assembly encapsulation structure before a soldering projection forms, this assembly encapsulation structure comprises an assembly 100, a weld pad 102 (Pad), a protective layer 104 (Passivation Layer) and a soldering projection lower metal layer 106 (Under Bump Metal).Shown in Figure 1B,, must form a photoresist layer 108 on the structure shown in Figure 1A in order to form soldering projection on soldering projection lower metal layer 106.Then shown in Fig. 1 C, with lithography process with photoresist layer 108 exposure imagings to expose soldering projection lower metal layer 106, make soldering projection can be formed at soldering projection lower metal layer 106.Then shown in Fig. 1 D, one soldering projection (Solder Bump) 110 is formed on the soldering projection lower metal layer 106, and general process of electroplating is complicated and permanent manufacturing cost consuming time is higher with electroplating technique.The another kind of soldering projection that forms is to utilize steel version (Stencil Mask) solder(ing) paste to be utilized print process insert opening on the steel version in the method on the soldering projection lower metal layer 106, and prerequisite is that the pattern on the steel version must accurately be aimed at soldering projection lower metal layer 106.Also having a kind of method of soldering projection on soldering projection lower metal layer 106 that form is to utilize printing (the Photo Film Defined Printing) mode of a kind of photoresistance film definition, but is subject to the resolution of photoresistance film (Photo Film) and is unsuitable for forming the soldering projection of high aspect ratio (High Aspect Ratio) thin space (Fine Pitch).
Remove the result of photoresist layer 108 behind Fig. 1 E demonstration formation soldering projection 110.And Fig. 1 F shows that etching soldering projection lower metal layer 106 is to expose the result of protective layer 104.Before formally welding, after the heating of reflow (Reflow) technology, the kenel that soldering projection 110 forms shown in Fig. 1 G.
The projection formation method of above-mentioned conventional package technology has following multinomial shortcoming.Projection formation method shown in Figure 1A to Fig. 1 G has been used consuming time and expensive electroplating technology, aims at difficult and steel version cost height and use the steel version to form soldering projection.The mode of the printing (Photo Film Defined Printing) of photoresistance film definition is subject to the resolution of photoresistance film (Photo Film) and is unsuitable for forming the soldering projection of high aspect ratio (High Aspect Ratio) thin space in addition.
Because the shortcoming of above-mentioned conventional package structure and technology, therefore be necessary to develop and a kind of novel structure that improves and technology to overcome the shortcoming of traditional structure and technology.
Summary of the invention
A purpose of the present invention is to overcome the deficiencies in the prior art and defective, and the soldering projection formation method that a kind of low cost and technology are simplified and the technology required time is short is provided.
Another object of the present invention is for providing a kind of high aspect ratio soldering projection formation method that forms less soldering projection and soldering projection spacing.
A further object of the present invention is for providing a kind of alignment accuracy high high resolution welding lug formation method.
In order to reach above-mentioned purpose, the invention provides a kind of high resolution welding lug formation method, this high resolution welding lug formation method comprises following steps: a wafer at first is provided, wherein has a plurality of weld pads, on this wafer and have protective layer and a plurality of soldering projection lower conductor layer that be positioned at this weld pad on of a plurality of openings to expose this weld pad; Then form a dielectric layer and cover this wafer; The pattern that shifts a plurality of soldering projections then enters this dielectric layer to form a plurality of openings and to expose this soldering projection lower conductor layer; At last scolder such as soldering paste or tiny soldered balls are inserted this opening and carried out reflow process.
One of this method of the present invention comprises following steps: a wafer is provided, wherein has a plurality of weld pads, on this wafer and have protective layer and a plurality of soldering projection lower conductor layer (UBM) that be positioned at this weld pad on of a plurality of openings to expose this weld pad; Form a non-photosensitive dielectric layer and cover this wafer; The pattern that shifts a plurality of soldering projections by a vertical direction perforate method for processing enters this dielectric layer to form a plurality of openings and to expose this soldering projection lower conductor layer; Scolder is inserted this opening; This wafer is carried out a reflow process to form a plurality of soldering projections; And remove this dielectric layer.
Described this non-photosensitive dielectric layer comprises a fractal film.
Described this vertical direction perforate method for processing comprises the laser beam drilling method.
Described this vertical direction perforate method for processing comprises plasma etching method.
Described this soldering paste or tiny soldered balls are inserted in the mode of scraper printing.
After described this dielectric layer removes, this wafer is carried out a dry etch process clean this wafer surface.
After this above-mentioned dielectric layer removes, this wafer is carried out a reflow process.
Two of this method of the present invention comprises following steps: a wafer is provided, wherein has a plurality of weld pads, on this wafer and have protective layer and a plurality of soldering projection lower conductor layer that be positioned at this weld pad on of a plurality of openings to expose this weld pad; Form in regular turn that a non-photosensitive dielectric layer covers this wafer and a fractal film covers this non-photosensitive dielectric layer; The pattern that shifts a plurality of soldering projections with a vertical direction perforate method for processing enters this fractal film and non-photosensitive dielectric layer to form a plurality of openings and to expose this soldering projection lower conductor layer; Scolder is inserted this opening; This wafer is carried out reflow process to form a plurality of soldering projections; And remove this fractal film.
After described this fractal film removes, this wafer is carried out a dry etch process clean this wafer surface.
After described this fractal film removes, this wafer is carried out a reflow process.
Description of drawings
Figure 1A shows the assembly encapsulation structure before a soldering projection forms;
Figure 1B shows the result of formation one photoresist layer on the assembly encapsulation structure shown in Figure 1A;
Fig. 1 C shows that the exposure imaging photoresist layer is to expose the result of soldering projection lower metal layer;
Fig. 1 D shows the result of formation one soldering projection on the soldering projection lower metal layer;
Fig. 1 E shows the result who removes photoresist layer;
Fig. 1 F shows that etching soldering projection lower metal layer is to expose the result of protective layer;
Fig. 1 G shows the result of soldering projection through reflow;
Fig. 2 A shows the wafer part assembly encapsulation structure that comprises integrated circuit (IC) chip;
Fig. 2 B is presented at the result who covers a dielectric layer on the structure shown in Fig. 2 A;
Fig. 2 C shows that dielectric layer is etched to expose the result of soldering projection lower metal layer;
Fig. 2 D shows the result that the soldering paste inserting soldering paste or tiny soldered balls in the opening that exposes the soldering projection lower metal layer and will overflow or tiny soldered balls remove;
Soldering paste shown in Fig. 2 E displayed map 2D or tiny soldered balls form the result of soldering projection through reflow process;
Fig. 2 F demonstration removes the result of dielectric layer with dielectric layer;
Fig. 2 G carries out reflow process result with the kenel shown in the formation figure again;
Fig. 3 A shows the wafer part assembly encapsulation structure that comprises integrated circuit (IC) chip;
It is etched to expose the result of soldering projection lower metal layer that Fig. 3 B is presented at two non-photosensitive dielectric layers shown in Fig. 3 A;
Fig. 3 C shows soldering paste or tiny soldered balls inserted in the opening that exposes the soldering projection lower metal layer, and the result that removes of the soldering paste that will overflow or tiny soldered balls;
Soldering paste shown in Fig. 3 D displayed map 3C or tiny soldered balls form the result of soldering projection through reflow process;
Fig. 3 E shows the result that the fractal film dielectric layer is removed;
Fig. 3 F shows the result who carries out a reflow process again.
Symbol description among the figure
100 assemblies
102 weld pads
104 protective layers
106 soldering projection lower metal layers
The welding of 108 photoresist layers
110 projections
200 chips
202 weld pads
204 protective layers
206 soldering projection lower metal layers
208 dielectric layers
210 soldering paste or tiny soldered balls
212 soldering projections
300 chips
302 weld pads
304 protective layers
306 soldering projection lower metal layers
308 dielectric layers
309 dielectric layers
310 soldering paste or tiny soldered balls
312 soldering projections
Embodiment
In this mandatory declaration is that processing step described below and structure do not comprise complete technology.The present invention can implement by various processes, only mentions at this and understands process required for the present invention.
Below will be described in detail by appended icon, and please note that icon will be simple form and, and size all is beneficial to understand the present invention by exaggerative not according to scaling according to the present invention.
In preferred embodiment of the present invention, projection formation method is applied on chip package (FlipChip Package) technology.Fig. 2 A to Fig. 2 G shows the wafer technology partly about comprising integrated circuit (IC) chip.
Fig. 2 A to Fig. 2 G shows the wafer that the comprises integrated circuit (IC) chip technology partly in the preferred embodiment of the present invention.Shown in figure 2A; show that the present invention comprises the wafer part assembly encapsulation structure of integrated circuit (IC) chip before soldering projection forms, this wafer partly assembly encapsulation structure comprises chip 200, weld pad 202 (Metal Pad), protective layer 204 (Passivation Layer) and soldering projection lower metal layer 206 (Under Bump Metal).Weld pad 202 comprises aluminium welding pad, but other material weld pad also should not be excluded.Weld pad 202 can be traditional deposition, little shadow and etch process form.Protective layer 204 can be formed by conventional method.Protective layer 204 is etched with the formation opening and exposes weld pad 202 by traditional little shadow and etch process.Soldering projection lower metal layer 206 is formed in the opening with traditional deposition, little shadow and etch process and reaches on the weld pad 202.Then with reference to shown in the figure 2B, cover a dielectric layer 208 on the structure shown in Fig. 2 A, this dielectric layer 208 is preferable with a fractal film (Release Film).And fractal film is the used dielectric film of general packaging technology, can be stripped from easily.After through together easy cleaning step, can fully be removed.Fractal film then is used to define the formation position of soldering projection.
Then with reference to shown in the figure 2C, dielectric layer 208 by perforate to expose soldering projection lower metal layer 206, dielectric layer 208 is a fractal film, the mode that then can laser beam drilling (Laser) or the technology of plasma etching (Plasma Etching) remove fractal film and are positioned at part on the soldering projection lower metal layer 206, to form opening.Utilize laser beam drilling or plasma etching can reach the opening that high-resolution is accurately aimed at, make soldering projection can accurately be formed on the soldering projection lower metal layer, simultaneously can further dwindle the spacing of soldering projection, and successfully form the soldering projection of high aspect ratio (HighAspect Ratio) the highly dense intensity of thin space.Then, soldering paste or tiny soldered balls (Solder Paste/Solder Powder) 210 are inserted in the opening that exposes soldering projection lower metal layer 206, and the soldering paste that will overflow or tiny soldered balls remove with reference to shown in the figure 2D.Soldering paste is by many tiny soldered balls or welding powder (Solder Powder), solvent and help weldering (melting) agent (Flux) to constitute, and soldered ball is generally the leypewter of eutectic composition.
Shown in figure 2E, the soldering projection 212 of the soldering paste 210 shown in Fig. 2 D in reflow and cleaning formation figure.When using tiny soldered balls then must after printing, add scaling powder again before the reflow, so the soldered ball bubble can be reduced to minimum.In Fig. 2 F, if dielectric layer 208 is a fractal film, then can be with dielectric layer 208 easy removal (can optionally not removing) yet, but if dielectric layer 208 is other dielectric material, then remove or divest, and can use dry-etching or electricity slurry clean surface with chemical liquids with plasma etching.As shown in Fig. 2 G, can carry out a reflow process more then with the kenel shown in the formation figure.
Fig. 3 A to Fig. 3 F shows the wafer that the comprises integrated circuit (IC) chip technology partly in the preferred embodiment of the present invention.Shown in figure 3A; show that the present invention comprises the wafer part assembly encapsulation structure of integrated circuit (IC) chip before soldering projection forms, this wafer partly assembly encapsulation structure comprises chip 300, weld pad 302, protective layer 304, soldering projection lower metal layer 306, dielectric layer 308 and 309. Dielectric layer 308 and 309 is used to define the formation position of soldering projection, and this two dielectric layer 308 and 309 comprises the non-photosensitive dielectric layer, and dielectric layer 309 is preferable with fractal film.In addition, optionally add a stickiness glued membrane between the dielectric layer 308 and 309.Weld pad 302 comprises aluminium welding pad, but other material weld pad also should not be excluded.Weld pad 302 can be traditional deposition, little shadow and etch process form.Protective layer 304 can be formed by conventional method.Protective layer 304 is etched with the formation opening and exposes weld pad 302 by traditional little shadow and etch process.Soldering projection lower metal layer 306 is formed in the opening with traditional deposition, little shadow and etch process and reaches on the weld pad 302.
Then with reference to shown in the figure 3B, dielectric layer 308 and 309 etched exposing soldering projection lower metal layer 306, etching dielectric layer 308 and 309 mode can be traditional vertical direction perforate method for processing, for example anisotropic etching method.Dielectric layer 309 is a fractal film, and the mode that then can laser beam drilling or the technology of plasma etching remove dielectric layer 308 and fractal film and is positioned at part on the soldering projection lower metal layer 306, to form opening.Utilize the technology of plasma etching to form opening and must on fractal film, use etch shield.Utilize laser beam drilling or plasma etching can reach the opening that high-resolution is accurately aimed at, soldering projection can accurately be formed on the convex pads, simultaneously can further dwindle the spacing of soldering projection, and successfully form the soldering projection of the highly dense intensity of high aspect ratio thin space.
Then, soldering paste or tiny soldered balls 310 are inserted in the opening that exposes soldering projection lower metal layer 306, and the soldering paste that will overflow or tiny soldered balls remove in the mode of scraper printing with reference to shown in the figure 3C.Soldering paste is by many tiny soldered balls or welding powder (Solder Powder), solvent and help weldering (melting) agent (Flux) to constitute, and soldered ball is generally the leypewter of eutectic composition.
Then with reference to shown in the figure 3D, the soldering paste 310 shown in Fig. 3 C forms the soldering projection 312 among the figure through reflow, cleaning.When using tiny soldered balls then must after printing, add scaling powder again before the reflow, so the soldered ball bubble can be reduced to minimum.With reference to shown in the figure 3E, dielectric layer 309 is removed then, and can be used in formula etching or electricity slurry clean surface.As shown in Fig. 3 F, can carry out a reflow process more then with the kenel shown in the formation figure.
In a preferred embodiment of the present invention, utilize dielectric layer particularly fractal film and the mode of laser beam drilling or the formation position that the technology of plasma etching is come the soldering projection on the accurate positions wafer, can in dielectric layer, form the opening that high-resolution is accurately aimed at, soldering projection can accurately be formed on the soldering projection lower metal layer on the wafer, the spacing that simultaneously can further dwindle soldering projection, and successfully form the soldering projection of high aspect ratio (High Aspect Ratio) the highly dense intensity of thin space, can overcome simultaneously and use steel version (Stencil Mask) to form the aligning that soldering projection caused to be difficult for and the expensive problem of steel version (Stencil Mask), and printing (the Photo Film Defined Printing) mode that solves traditional photoresistance film definition is subject to the resolution of photoresistance film (PhotoFilm) and is difficult to form high aspect ratio (high Aspect Ratio) soldering projection of thin space or the problem of weld pad.In addition, utilize soldering paste or tiny soldered balls to insert in high aspect ratio highly dense intensity of (highAspect Ratio) thin space and the accurate opening of aiming at of high-resolution and can solve tradition with the consuming time and expensive problem of galvanoplastic formation soldering projection to form soldering projection.
Above-mentioned relevant detailed description of the invention only is an example and unrestricted.Other equivalence that does not break away from spirit of the present invention changes or modifies within the scope of the claims of the present invention that all should be included in.
Claims (10)
1. a high resolution welding lug formation method is characterized in that, this method comprises:
One wafer is provided, wherein has a plurality of weld pads, on this wafer and have protective layer and a plurality of soldering projection lower conductor layer (UBM) that be positioned at this weld pad on of a plurality of openings to expose this weld pad;
Form a non-photosensitive dielectric layer and cover this wafer;
The pattern that shifts a plurality of soldering projections by a vertical direction perforate method for processing enters this dielectric layer to form a plurality of openings and to expose this soldering projection lower conductor layer;
Scolder is inserted this opening;
This wafer is carried out a reflow process to form a plurality of soldering projections; And
Remove this dielectric layer.
2. high resolution welding lug formation method as claimed in claim 1 is characterized in that, this above-mentioned non-photosensitive dielectric layer comprises a fractal film.
3. high resolution welding lug formation method as claimed in claim 1 is characterized in that, this above-mentioned vertical direction perforate method for processing comprises the laser beam drilling method.
4. high resolution welding lug formation method as claimed in claim 1 is characterized in that, this above-mentioned vertical direction perforate method for processing comprises plasma etching method.
5. high resolution welding lug formation method as claimed in claim 1 is characterized in that, above-mentioned this soldering paste or tiny soldered balls are inserted in the mode of scraper printing.
6. high resolution welding lug formation method as claimed in claim 1 is characterized in that, after this above-mentioned dielectric layer removes, this wafer is carried out a dry etch process clean this wafer surface.
7. high resolution welding lug formation method as claimed in claim 1 is characterized in that, after this above-mentioned dielectric layer removes, this wafer is carried out a reflow process.
8. a high resolution welding lug formation method is characterized in that, this method comprises:
One wafer is provided, wherein has a plurality of weld pads, on this wafer and have protective layer and a plurality of soldering projection lower conductor layer that be positioned at this weld pad on of a plurality of openings to expose this weld pad;
Form in regular turn that a non-photosensitive dielectric layer covers this wafer and a fractal film covers this non-photosensitive dielectric layer;
The pattern that shifts a plurality of soldering projections with a vertical direction perforate method for processing enters this fractal film and non-photosensitive dielectric layer to form a plurality of openings and to expose this soldering projection lower conductor layer;
Scolder is inserted this opening;
This wafer is carried out reflow process to form a plurality of soldering projections; And remove this fractal film.
9. high resolution welding lug formation method as claimed in claim 8 is characterized in that, after this above-mentioned fractal film removes, this wafer is carried out a dry etch process clean this wafer surface.
10. high resolution welding lug formation method as claimed in claim 8 is characterized in that, after this above-mentioned fractal film removes, this wafer is carried out a reflow process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021244790A CN1166481C (en) | 2002-06-28 | 2002-06-28 | Forming method for high resolution welding lug |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021244790A CN1166481C (en) | 2002-06-28 | 2002-06-28 | Forming method for high resolution welding lug |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1392025A CN1392025A (en) | 2003-01-22 |
| CN1166481C true CN1166481C (en) | 2004-09-15 |
Family
ID=4745402
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021244790A Expired - Lifetime CN1166481C (en) | 2002-06-28 | 2002-06-28 | Forming method for high resolution welding lug |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1166481C (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101241866B (en) * | 2007-02-05 | 2010-12-01 | 南茂科技股份有限公司 | Making method of protrusion block structure with reinforced object |
| CN101615584B (en) * | 2008-06-25 | 2011-06-15 | 南茂科技股份有限公司 | Packaging method of chip reconfiguration structure |
| CN101636041B (en) * | 2008-07-24 | 2011-05-11 | 富葵精密组件(深圳)有限公司 | Substrate plane planarization system and method thereof |
| CN102487049B (en) * | 2010-12-02 | 2014-10-15 | 矽品精密工业股份有限公司 | Semiconductor substrate and preparation method thereof |
| JP5664392B2 (en) * | 2011-03-23 | 2015-02-04 | ソニー株式会社 | Semiconductor device, method for manufacturing semiconductor device, and method for manufacturing wiring board |
| CN102931145B (en) * | 2011-08-09 | 2015-12-09 | 中芯国际集成电路制造(上海)有限公司 | The formation method of bonding pad structure |
| CN102371410A (en) * | 2011-09-07 | 2012-03-14 | 中国航天科技集团公司第九研究院第七七一研究所 | Process for making non-void high-reliability convex points in wafer by vacuum brazing |
| TWI483362B (en) * | 2012-05-07 | 2015-05-01 | Chipmos Technologies Inc | Conductive structure and mehtod for forming the same |
| US9023727B2 (en) * | 2012-06-27 | 2015-05-05 | Chipmos Technologies Inc. | Method of manufacturing semiconductor packaging |
| CN113471061A (en) * | 2021-06-30 | 2021-10-01 | 颀中科技（苏州）有限公司 | Preparation method of wafer surface dielectric layer, wafer structure and forming method of bump |
-
2002
- 2002-06-28 CN CNB021244790A patent/CN1166481C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CN1392025A (en) | 2003-01-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1296981C (en) | Method for producing semiconductor device | |
| CN1166481C (en) | Forming method for high resolution welding lug | |
| US7820479B2 (en) | Conductive ball mounting method | |
| CN2585416Y (en) | Semiconductor chip and wiring substrate, semiconductor wafer, semiconductor device, wire substrate and electronic machine | |
| CN1377215A (en) | Manufacturing method for circuit device | |
| CN1942057A (en) | Method of forming metal plate pattern and circuit board | |
| JP2005322915A (en) | Surface-mounting attachment of component | |
| CN1674758A (en) | Circuit device and manufacturing method thereof | |
| CN1574324A (en) | Semiconductor device and manufacturing method thereof | |
| KR20100132823A (en) | Substrate of flip chip and fabricating method of the same | |
| CN1166480C (en) | Forming method for high resolution welding lug | |
| CN1128486A (en) | Method for forming solder bump in IC mounted board | |
| CN1211835C (en) | Method for forming buffer pad, semiconductor device and making method, circuit substrate and electronic equipment | |
| CN1172358C (en) | Overlapped chip binding structure and generating method | |
| CN1728341A (en) | Method of manufacturing semiconductor device | |
| US20110299259A1 (en) | Circuit board with conductor post structure | |
| CN1301542C (en) | Semiconductor wafer, semiconductor device and its producing method, circuit base board and electronic machine | |
| JP2007220870A (en) | Semiconductor board and method for manufacturing semiconductor element | |
| CN1191618C (en) | Method for producing circuit device | |
| CN1171300C (en) | Method for making wiring circuit board with convex point and method for forming convex point | |
| CN1301543C (en) | Semiconductor wafer, semiconductor device and its producing method, circuit base baord and electronic machine | |
| CN1684240A (en) | Semiconductor device, method for producing the same, circuit board, and electronic apparatus | |
| CN100350581C (en) | Integrated wiring and inverse packaged chip structure and process | |
| CN1245751C (en) | Method for producing semiconductor device and semiconductor device thereof | |
| CN1768428A (en) | Photodiode array and production method thereof, and radiation detector |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20040915 |