CN116647222A - Driving circuit and driving chip - Google Patents
Driving circuit and driving chip Download PDFInfo
- Publication number
- CN116647222A CN116647222A CN202310438809.1A CN202310438809A CN116647222A CN 116647222 A CN116647222 A CN 116647222A CN 202310438809 A CN202310438809 A CN 202310438809A CN 116647222 A CN116647222 A CN 116647222A
- Authority
- CN
- China
- Prior art keywords
- power device
- unit
- resistor
- diode
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001105 regulatory effect Effects 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 10
- 230000003321 amplification Effects 0.000 claims abstract description 5
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 5
- 230000000740 bleeding effect Effects 0.000 claims abstract description 4
- 239000003990 capacitor Substances 0.000 claims description 24
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 5
- 238000011084 recovery Methods 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000007599 discharging Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
Abstract
The application provides a driving circuit and a driving chip, which are used for improving the on-off efficiency of a power device, and at least comprise the following components: the device comprises a first adjusting module, a second adjusting module and a control module, wherein: the control module is used for carrying out push-pull amplification on an input signal; the first adjusting module is connected between the power device and the output end of the control module, adjusts the opening speed of the power device by setting a threshold value, and adjusts the turn-off current of the power device based on the turn-off process of the power device; the second regulating module is connected between the power device and the first regulating module, and further regulates the turn-off current of the power device by providing a bleeding path. On the premise of ensuring the reliability and stability of the power device, the on-off efficiency of the power device is greatly improved through preliminary adjustment of the first adjusting module and further adjustment of the second adjusting module. Simple structure, strong portability and great practical value.
Description
Technical Field
The present application relates to the field of integrated circuit design and application technology, and in particular, to a driving circuit and a driving chip.
Background
The on and off efficiency of the power device (including MOS transistor, insulated gate bipolar transistor, silicon carbide, etc.) is absolutely affected by the driving circuit. The higher the on and off efficiency of the power device is, the smaller the switching loss of the power device is, the slower the temperature rise is, but the power device generates extremely high dv/dt (i.e. voltage abrupt change) and di/dt (i.e. current abrupt change), so that the power device generates waveform oscillation, and Vds (i.e. voltage drop between drain and source) and Vgs (i.e. voltage drop between gate and source) of the power device are severely fluctuated, so that the power device is more likely to fail. Therefore, how to improve the on-off efficiency of the power device under the premise of ensuring the reliability and stability of the power device is a technical problem to be solved urgently.
It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present application and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the application section.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present application is to provide a driving circuit and a driving chip, which are used for solving the problem that it is difficult to improve the on-off efficiency of a power device under the premise of ensuring the reliability and stability of the power device in the prior art.
To achieve the above and other related objects, the present application provides a driving circuit for improving on and off efficiency of a power device, the driving circuit at least comprising: the device comprises a first adjusting module, a second adjusting module and a control module, wherein:
the control module is used for carrying out push-pull amplification on an input signal;
the first adjusting module is connected between the power device and the output end of the control module, adjusts the opening speed of the power device by setting a threshold value, and adjusts the turn-off current of the power device based on the turn-off process of the power device;
the second regulating module is connected between the power device and the first regulating module, and further regulates the turn-off current of the power device by providing a bleeding path.
Optionally, the control module includes: the first NMOS tube, the first PMOS tube and the first resistor, wherein: the first end of the first resistor is connected with an input signal; the drain electrode of the first NMOS tube is connected with a first signal, and the grid electrode of the first NMOS tube is connected with the second end of the first resistor; the source electrode of the first PMOS tube is connected with the source electrode of the first NMOS tube, the grid electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube, and the drain electrode of the first PMOS tube is connected with the second signal.
Optionally, the polarity of the voltage of the first signal is opposite to the polarity of the voltage of the second signal.
Optionally, the first adjustment module includes: the second resistor, the third resistor and the first diode, wherein: the negative electrode of the first diode is connected with the output end of the control module; the second resistor is connected with the first diode in parallel; the third resistor is connected with the positive electrode of the first diode.
Optionally, the second adjustment module includes: a first unit, a second unit, and a third unit, wherein: the first end of the first unit is connected with the working voltage; the first end of the second unit is connected with the first adjusting module; the first end of the third unit is connected with the second end of the first unit and the second end of the second unit, and the second end of the third unit is connected with power ground.
Optionally, the second adjustment module further comprises a fourth unit, wherein the fourth unit is connected between the first end of the second unit and the second end of the third unit.
Optionally, the first unit includes a first capacitor and a fourth resistor, wherein: the first end of the first capacitor is connected with the working voltage; the first end of the fourth resistor is connected with the second end of the first capacitor.
Optionally, the second unit includes a second capacitor and a fifth resistor, wherein: the first end of the second capacitor is connected with the first adjusting module; the fifth resistor is connected in parallel with the second capacitor.
Optionally, the third unit includes: the third NMOS tube, the second diode and the sixth resistor, wherein: the drain electrode of the third NMOS tube is connected with the second end of the second unit, the grid electrode of the third NMOS tube is connected with the second end of the first unit, and the source electrode of the third NMOS tube is connected with power ground; the cathode of the second diode is connected with the grid electrode of the third NMOS tube, and the anode of the second diode is connected with power ground; the sixth resistor is connected in parallel with the second diode.
Optionally, the fourth unit includes a seventh resistor.
To achieve the above and other related objects, the present application provides a driving chip, which includes the driving circuit, and the driving chip is used for improving the on and off efficiency of a power device.
As described above, the driving circuit and the driving chip have the following beneficial effects:
1) According to the driving circuit and the driving chip, on the premise of ensuring the reliability and the stability of the power device, the on-off efficiency of the power device is greatly improved through preliminary adjustment of the first adjusting module and further adjustment of the second adjusting module.
2) The driving circuit and the driving chip have the advantages of simple structure, strong portability and high practical value.
Drawings
Fig. 1 is a schematic diagram of a driving circuit according to the present application.
Description of the reference numerals
1. Driving circuit
11. First adjusting module
12. Second adjusting module
121. First unit
122. Second unit
123. Third unit
124. Fourth unit
13. Control module
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application.
Please refer to fig. 1. It should be noted that the illustrations provided in the present embodiment merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
As shown in fig. 1, the present embodiment provides a driving circuit 1 for improving the on and off efficiency of a power device N4, the driving circuit 1 including: the first adjusting module 11, the second adjusting module 12, i.e., the control module 13, it should be noted that the power device N4 includes: insulated gate bipolar transistors (i.e., IGBTs), silicon carbide (SiC), and the like, wherein the IGBTs are composite fully-controlled-voltage-driven-power semiconductor devices composed of BJTs (bipolar junction transistors) and MOS (insulated gate field effect transistors), have the characteristic of self-turn-off, are non-on and off switches, have no voltage amplifying function, can be regarded as wires when turned on, and can be regarded as open circuits when turned off. The IGBT combines the advantages of the BJT and the MOS devices, such as small driving power, reduced saturation voltage and the like. The withstand voltage value and the withstand current value are two criteria of IGBT classification, for example, the withstand voltage class of an IGBT generally has: 600 volts, 1200 volts, 1700 volts, 2500 volts, 3300 volts, 4500 volts, 6500 volts. The current resistance value of the IGBT is related to the packaging type, and if the current resistance value is low, single tube packaging (namely, only the IGBT) is adopted; if the withstand current value is large, a module package is adopted, namely, a mode that an IGBT and an FRD (fast recovery diode or free wheeling diode) are packaged together in parallel. Low current modes of IGBTs, e.g. 1200 volts, single tube package class, are: 15 amperes, 20 amperes and 25 amperes; and the 1200 volt IGBT packaged by the module is adopted, and the current modes are as follows: 75 amps, 100 amps, 300 amps, 400 amps, 600 amps, 800 amps, 1200 amps, 2400 amps, 3600 amps, etc. It should be further explained that the IGBT and the application system are closely related, and the IGBT is burned by overcurrent, overvoltage, overfrequency, high temperature, large parasitic inductance, etc.
Silicon carbide (SiC) is a compound semiconductor material composed of silicon (Si) and carbon (C), and has a very strong binding force, is very stable in terms of heat, chemistry and machinery, and has a basic structural unit of si—c tetrahedron, belonging to a close-packed structure. Because of the difference of unidirectional stacking modes, various different crystal forms are generated, the different crystal forms show respective characteristics in the aspect of semiconductor characteristics, and by utilizing the characteristics of silicon carbide, heterogeneous composite structures and superlattices with completely matched crystal lattices among different polytypes of silicon carbide can be manufactured, so that devices with excellent performance can be obtained, for example, silicon carbide with certain crystal lattices has a withstand voltage value of 600 volts to thousands of volts, and on-resistance is only equivalent to 1/200 of that of silicon, and the silicon carbide can be used as the setting form of a power device N4.
Therefore, it is important to improve the on/off efficiency of the power device N4 for the driving circuit.
As shown in fig. 1, the control module 13 is configured to push-pull amplify the input signal Vin. Specifically, as an example, the control module 13 includes: the first NMOS tube N1, the first PMOS tube P1 and the first resistor R1, wherein: the first end of the first resistor R1 is connected with the input signal Vin; the drain electrode of the first NMOS tube N1 is connected with a first signal V1, and the grid electrode of the first NMOS tube N1 is connected with the second end of the first resistor R1; the source electrode of the first PMOS tube P1 is connected with the source electrode of the first NMOS tube N1, the grid electrode of the first PMOS tube P1 is connected with the grid electrode of the first NMOS tube N1, and the drain electrode of the first PMOS tube P1 is connected with the second signal V2. More specifically, the polarity of the voltage of the first signal V1 is opposite to the polarity of the voltage of the second signal V2. It should be noted that, the first NMOS transistor N1 and the first PMOS transistor P1 form a push-pull circuit structure, and the push-pull circuit is an output circuit formed by connecting two transistors with different polarities. The push-pull circuit adopts two power BJT (bipolar junction transistor) or MOS (metal oxide semiconductor) transistors with the same parameters, the power BJT or the MOS transistors exist in the circuit in a push-pull mode, each power transistor is responsible for the waveform amplification task of positive and negative half cycles, and when the circuit works, only one symmetrical power transistor is conducted at a time, so that the conduction loss is small and the efficiency is high. The push-pull circuit is used for providing a driving signal for switching on or off the power device N4. In this embodiment, the voltage of the first signal V1 is +15 volts, the voltage of the second signal V2 is-6 volts, and the opening speed of the power device N4 is adjusted by combining the voltage of the first signal V1 and the threshold value set by the first adjusting module. When analyzing the turn-on process of the power device N4, vds is the voltage between the drain and the source of the power device N4, vgs is the driving voltage between the gate and the source of the power device N4, ids is the turn-on current of the power device N4, and the product of Vds and Ids is expressed as the turn-on loss of the power device N4. When Vgs increases gradually and exceeds the threshold vth_n4 of the power device N4, ids reaches a peak (a peak represents a reverse recovery phenomenon of a parasitic diode in the power device N4, wherein the reverse recovery phenomenon refers to a switching process that the diode passes from forward conduction to reverse cut-off), the turn-on speed of the power device N4 increases, but the higher the Vgs or the higher the peak of Ids, the circuit oscillation is easily caused, and the risk of failure of the power device N4 increases.
Therefore, shortening the reverse recovery process of the power device N4 as much as possible is helpful to improve the turn-on efficiency of the power device N4, and further, the turn-on speed of the power device N4 becomes adjustable, which is helpful to improve the turn-on efficiency of the power device N4; when the power device N4 is turned off, ids of the power device N4 is reduced to zero as soon as possible, and the turn-off efficiency of the power device N4 is improved.
As shown in fig. 1, the first adjusting module 11 is connected between the power device N4 and the output end of the control module 13, adjusts the turn-on speed of the power device N4 by setting a threshold value, and adjusts the turn-off current of the power device based on the turn-off process of the power device N4.
Specifically, as an example, as shown in fig. 1, the first adjustment module 11 module includes: the second resistor R2, the third resistor R3 and the first diode D1, wherein: the cathode of the first diode D1 is connected with the output end of the control module 13, wherein the cathode of the first diode D1 is connected with the source electrode of the first NMOS tube N1; the second resistor R2 is connected with the first diode D1 in parallel; the third resistor is connected with the anode of the first diode D1.
It should be noted that, as an example, the driving voltage Vgs of the power device N4 is 15 volts, the reverse breakdown voltage of the first diode D1 is set to 5 volts, when the Vgs of the power device N4 rises between 0 and 10 volts, ids rises faster, and at this time, the turn-on speed of the power device N4 is fast, and the turn-on loss is lower; when Vgs of the power device N4 rises between 10 and 15 volts, if the rising speed of Ids is reduced, the value of reverse recovery current of the power device N4 is reduced, so that the power device N4 is turned on slowly, the turning-on speed of the power device N4 is considered, and oscillation is avoided, wherein the voltage of the first signal V1 is +15 volts, the voltage of the second signal V2 is-6 volts, the reverse breakdown voltage of the first diode D1 is 5 volts, and when Vgs rises between 0 and 10 volts (i.e. the difference between the voltage value of V1 and the reverse breakdown voltage of the first diode D1 is equal to 10 volts), the first diode D1 is in a breakdown state, the main circulation path of current in the stage is the first diode D1 and the third resistor R3, and the current of the first diode D1 is relatively large, so that the rising speed of Ids of the power device N4 is relatively fast; when Vgs of the power device N4 rises slowly between 10 and 15 volts, the first diode D1 is not broken down, no current flows in the first diode D1, and current at this stage can only pass through the path of the second resistor R2 and the third resistor R3, and by setting appropriate resistance values of the second resistor R2 and the third resistor R3, the rising speed of Ids of the power device N4 can be controlled by controlling the circulating current of the second resistor R2 and the third resistor R3. When the power device N4 is turned off, the third resistor R3 and the first diode D1 control the falling speed of Ids of the power device N4, at this time, the second resistor R2 is hardly active, and the early stage of the turn-off is mainly regulated by the third resistor R3, and the second regulating module 12 provides a further regulating operation for the turn-off efficiency of the power device N4.
As shown in fig. 1, the second adjusting module 12 is connected between the power device N4 and the first adjusting module 11, that is, the second adjusting module 12 is connected between the gate of the power device N4 and the second end of the third resistor R3, and further adjusts the off current of the power device N4 by providing a bleed path.
Specifically, as an example, as shown in fig. 1, the second adjustment module 12 includes: a first unit 121, a second unit 122, and a third unit 123, wherein: a first end of the first unit 121 is connected to an operating voltage VDD; the first end of the second unit 122 is connected to the output end of the first adjusting module 11, i.e. the first end of the second unit 122 is connected to the second end of the third resistor R3; the first end of the third cell 123 is connected to the second end of the first cell 121 and the second end of the second cell 122, and the second end of the third cell 123 is connected to the power ground PGND. More specifically, the second adjustment module 12 further includes a fourth unit 124, wherein the fourth unit 124 is connected between the first end of the second unit 122 and the second end of the third unit 123. The first unit 121 includes a first capacitor C1 and a fourth resistor R4, wherein: the first end of the first capacitor C1 is connected with the working voltage VDD; the first end of the fourth resistor R4 is connected to the second end of the first capacitor C1. The second unit 122 includes a second capacitor C2 and a fifth resistor R5, wherein: the first end of the second capacitor C2 is connected with the first adjusting module 11; the fifth resistor R5 is connected in parallel with the second capacitor C2. The third unit 123 includes: a third NMOS transistor N3, a second diode D2, and a sixth resistor R6, wherein: the drain electrode of the third NMOS transistor N3 is connected to the second end of the second unit 122, that is, the drain electrode of the third NMOS transistor N3 is connected to the second end of the second capacitor C2, the gate electrode of the third NMOS transistor N3 is connected to the second end of the first unit 121, that is, the gate electrode of the third NMOS transistor N3 is connected to the second end of the fourth resistor R4, and the source electrode of the third NMOS transistor N3 is connected to the power ground PGND; the cathode of the second diode D2 is connected with the grid electrode of the third NMOS tube N3, and the anode of the second diode D2 is connected with the power ground PGND; the sixth resistor R6 is connected in parallel with the second diode D2. The fourth cell 124 includes a seventh resistor R7.
It should be noted that, as shown in fig. 1, when the power device N4 is turned off, ids of the power device N4 is mainly controlled by the third resistor R3 in the early stage of the turn-off, and once the turn-off operation enters the late stage of the miller stage (the miller stage is also called a miller effect stage, the basic principle of which includes Vgs vs. powerGate-source capacitance C of device N4 GS Is a charging and discharging process of (a); when the gate-source capacitance C of the power device N4 GS After the threshold voltage is reached, the power device N4 enters an on state; when the power device N4 is started, vds of the power device N4 starts to decline, ids of the power device N4 starts to rise, and the power device N4 enters a saturation region; however, due to the miller effect, vgs will not rise for a while, ids has reached its maximum, while Vds continues to decrease until the miller capacitance, i.e., the gate-drain capacitance C of the power device N4, is fully charged GD The method comprises the steps of carrying out a first treatment on the surface of the When Vgs rises to a certain extent, vds drops thoroughly when the power device N4 enters the linear resistance region, and the on phase ends, since the miller capacitance prevents Vgs from rising, vds is prevented from falling, so that the loss time of the power device N4 is prolonged, that is, vgs rises, the on resistance of the power device N4 drops, vds drops), that is, after Vds of the power device N4 rises, the first capacitor C1 in the first unit 121 performs charging operation, the charged current charges the gate of the third NMOS transistor N3 in the third unit 123 through the fourth resistor R4, and the second diode D2 and the sixth resistor R6 are connected between the gate and the source of the third NMOS transistor N3, and the second diode D2 clamps the gate of the third NMOS transistor N3, wherein the reverse breakdown voltage of the second diode D2 is usually 5 volts; when the charged current causes the gate voltage of the third NMOS transistor N3 to exceed the threshold voltage Vth_N3 of the third NMOS transistor N3, the third NMOS transistor N3 is turned on, and the gate-source capacitance C of the power device N4 GS While charging the second capacitor C2 (i.e., C) in the second cell 122 GS The third resistor R3 in the first regulating module 11 discharges, and the second capacitor C2 discharges in a charging mode, so that the voltage of the Vgs of the power device N4 can be quickly reduced, the Ids can be quickly reduced, and the power device N4 can be quickly turned off. The fifth resistor R5 in the second unit 122 is used for discharging the second capacitor C2, and the sixth resistor R6 in the third unit 123 is used for discharging the gate parasitic capacitor of the third NMOS transistor N3; while the fourth cell 124 may provide the gate-source capacitance C of the power device N4 GS Providing a further discharge path, which may or may not be provided, according to the needTaking into account the scene.
It should be noted that, the first adjusting module 11 and the second adjusting module 12 may also be configured in the form of a gate control circuit, an application specific integrated circuit (Application Specific Integrated Circuit, abbreviated as ASIC, refer to an integrated circuit designed and manufactured according to the requirements of a specific user and the requirements of a specific electronic system, and the ASIC design is one of the most popular ways to implement the CPLD-complex programmable logic device and the FPGA-field programmable logic gate array, which have the characteristics of all having the user field programmable characteristics and all supporting the boundary scan technology, and the ASIC is characterized by facing the requirements of the specific user, and the ASIC has the advantages of smaller volume, lower power consumption, improved reliability, improved performance, enhanced confidentiality, reduced cost, etc. compared with the general integrated circuit during mass production, so long as the first adjusting module 11 can adjust the on speed and the off speed of the power device N4, and the second adjusting module 12 can further adjust the off current of the power device 12, thereby improving the on and off efficiency of the power device N4, and the configuration modes of the first adjusting module 11 and the second adjusting module 12 are not limited by this embodiment.
The embodiment also provides a driving chip, which comprises the driving circuit of the embodiment, and is used for improving the on-off efficiency of the power device. It should be noted that, the chip may be set by an ASIC (application specific integrated circuit ASIC), or may be set by an IP core (IP core, commonly known as intellectual property core, commonly known as intellectual property core, is a reusable module provided by a certain party in a reusable design methodology of an integrated circuit and having a form of a logic unit and a chip design.
In summary, the driving circuit and the driving chip of the present application are used for improving the on and off efficiency of the power device, and at least include: the device comprises a first adjusting module, a second adjusting module and a control module, wherein: the control module is used for carrying out push-pull amplification on an input signal; the first adjusting module is connected between the power device and the output end of the control module, adjusts the opening speed of the power device by setting a threshold value, and adjusts the turn-off current of the power device based on the turn-off process of the power device; the second regulating module is connected between the power device and the first regulating module, and further regulates the turn-off current of the power device by providing a bleeding path. According to the driving circuit and the driving chip, on the premise of ensuring the reliability and the stability of the power device, the on-off efficiency of the power device is greatly improved through preliminary adjustment of the first adjusting module and further adjustment of the second adjusting module. The driving circuit and the driving chip have the advantages of simple structure, strong portability and high practical value. Therefore, the application effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (11)
1. A driving circuit for improving the on and off efficiency of a power device, the driving circuit comprising at least: the device comprises a first adjusting module, a second adjusting module and a control module, wherein:
the control module is used for carrying out push-pull amplification on an input signal;
the first adjusting module is connected between the power device and the output end of the control module, adjusts the opening speed of the power device by setting a threshold value, and adjusts the turn-off current of the power device based on the turn-off process of the power device;
the second regulating module is connected between the power device and the first regulating module, and further regulates the turn-off current of the power device by providing a bleeding path.
2. The drive circuit according to claim 1, wherein: the control module includes: the first NMOS tube, the first PMOS tube and the first resistor, wherein: the first end of the first resistor is connected with an input signal; the drain electrode of the first NMOS tube is connected with a first signal, and the grid electrode of the first NMOS tube is connected with the second end of the first resistor; the source electrode of the first PMOS tube is connected with the source electrode of the first NMOS tube, the grid electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube, and the drain electrode of the first PMOS tube is connected with the second signal.
3. The drive circuit according to claim 2, wherein: the polarity of the voltage of the first signal is opposite to the polarity of the voltage of the second signal.
4. The drive circuit according to claim 1, wherein: the first adjustment module includes: the second resistor, the third resistor and the first diode, wherein: the negative electrode of the first diode is connected with the output end of the control module; the second resistor is connected with the first diode in parallel; the third resistor is connected with the positive electrode of the first diode.
5. The drive circuit according to claim 1, wherein: the second adjustment module includes: a first unit, a second unit, and a third unit, wherein: the first end of the first unit is connected with the working voltage; the first end of the second unit is connected with the first adjusting module; the first end of the third unit is connected with the second end of the first unit and the second end of the second unit, and the second end of the third unit is connected with power ground.
6. The drive circuit according to claim 5, wherein: the second adjustment module further includes a fourth unit, wherein the fourth unit is connected between the first end of the second unit and the second end of the third unit.
7. The drive circuit according to claim 6, wherein: the first unit comprises a first capacitor and a fourth resistor, wherein: the first end of the first capacitor is connected with the working voltage; the first end of the fourth resistor is connected with the second end of the first capacitor.
8. The drive circuit according to claim 6, wherein: the second unit comprises a second capacitor and a fifth resistor, wherein: the first end of the second capacitor is connected with the first adjusting module; the fifth resistor is connected in parallel with the second capacitor.
9. The drive circuit according to claim 6, wherein: the third unit includes: the third NMOS tube, the second diode and the sixth resistor, wherein: the drain electrode of the third NMOS tube is connected with the second end of the second unit, the grid electrode of the third NMOS tube is connected with the second end of the first unit, and the source electrode of the third NMOS tube is connected with power ground; the cathode of the second diode is connected with the grid electrode of the third NMOS tube, and the anode of the second diode is connected with power ground; the sixth resistor is connected in parallel with the second diode.
10. The drive circuit according to claim 6, wherein: the fourth cell includes a seventh resistor.
11. A driver chip, characterized in that: the driving chip includes: the driving circuit as claimed in any one of claims 1 to 10, wherein the driving chip is used for improving on and off efficiency of the power device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310438809.1A CN116647222B (en) | 2023-04-21 | 2023-04-21 | Driving circuit and driving chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310438809.1A CN116647222B (en) | 2023-04-21 | 2023-04-21 | Driving circuit and driving chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116647222A true CN116647222A (en) | 2023-08-25 |
| CN116647222B CN116647222B (en) | 2024-02-23 |
Family
ID=87622006
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310438809.1A Active CN116647222B (en) | 2023-04-21 | 2023-04-21 | Driving circuit and driving chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116647222B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112737554A (en) * | 2021-01-13 | 2021-04-30 | 深圳市汇川技术股份有限公司 | Power tube gate drive circuit and motor controller |
| CN113315499A (en) * | 2021-06-25 | 2021-08-27 | 阳光电源股份有限公司 | Driving method, driving circuit and controller of power device |
| CN214315220U (en) * | 2021-01-13 | 2021-09-28 | 深圳市汇川技术股份有限公司 | Power tube gate drive circuit and motor controller |
-
2023
- 2023-04-21 CN CN202310438809.1A patent/CN116647222B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112737554A (en) * | 2021-01-13 | 2021-04-30 | 深圳市汇川技术股份有限公司 | Power tube gate drive circuit and motor controller |
| CN214315220U (en) * | 2021-01-13 | 2021-09-28 | 深圳市汇川技术股份有限公司 | Power tube gate drive circuit and motor controller |
| CN113315499A (en) * | 2021-06-25 | 2021-08-27 | 阳光电源股份有限公司 | Driving method, driving circuit and controller of power device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116647222B (en) | 2024-02-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9083343B1 (en) | Cascode switching circuit | |
| US8723591B2 (en) | Method for driving IGBT | |
| US20120199875A1 (en) | Cascode scheme for improved device switching behavior | |
| US7737737B2 (en) | Drive circuit for voltage driven electronic element | |
| US20130062626A1 (en) | Power semiconductor module | |
| US9515649B2 (en) | Cascode circuit | |
| JP2004215458A (en) | Drive circuit of semiconductor switching element | |
| TW201340579A (en) | Semiconductor switch and power conversion device | |
| CN111211762A (en) | SiC MOSFET drive circuit with high turn-on performance | |
| US20140132312A1 (en) | Efficiency optimized driver circuit | |
| JP5582123B2 (en) | Semiconductor device | |
| JP5832845B2 (en) | Semiconductor module and power conversion module | |
| CN116647222B (en) | Driving circuit and driving chip | |
| JP4830829B2 (en) | Insulated gate transistor drive circuit | |
| JP2013062965A (en) | Semiconductor module | |
| JP5704105B2 (en) | Semiconductor device | |
| CN115001249A (en) | Digital variable current source power switching device gate driver | |
| US11394372B2 (en) | Wide band gap power semiconductor system and driving method thereof | |
| JP2007288094A (en) | Igbt, and gate drive circuit for driving it | |
| JP2018098849A (en) | Power module | |
| JP6400098B2 (en) | Power semiconductor device drive circuit | |
| EP2811648A1 (en) | Method and arrangement for controlling semiconductor switch | |
| CN115967388A (en) | Circuit structure for realizing function of controlling current change | |
| KR102253146B1 (en) | A Circuit For Eliminating Residual Current of Driving Transistor Using JFET | |
| CN109861503B (en) | Driving circuit for power device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |