CN116644020A - Serial communication method and electronic equipment - Google Patents

Serial communication method and electronic equipment Download PDF

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Publication number
CN116644020A
CN116644020A CN202310568046.2A CN202310568046A CN116644020A CN 116644020 A CN116644020 A CN 116644020A CN 202310568046 A CN202310568046 A CN 202310568046A CN 116644020 A CN116644020 A CN 116644020A
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China
Prior art keywords
data
state
receiving end
data receiving
back pressure
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CN202310568046.2A
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Chinese (zh)
Inventor
魏天博
黄杨国
湛厚超
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Rockchip Electronics Co Ltd
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Rockchip Electronics Co Ltd
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Priority to CN202310568046.2A priority Critical patent/CN116644020A/en
Publication of CN116644020A publication Critical patent/CN116644020A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)

Abstract

The present disclosure provides a serial communication method and an electronic device. The serial communication method comprises the following steps: receiving a back pressure signal sent by a data receiving end, wherein the back pressure signal indicates the buffer status of the data receiving end; and if the state of the buffer memory of the data receiving end meets the communication condition, sending data to the data receiving end. The serial communication method can reduce protocol overhead.

Description

Serial communication method and electronic equipment
Technical Field
The disclosure belongs to the technical field of communication, and in particular relates to a serial communication method and electronic equipment.
Background
Serial communication is a communication scheme widely used in data communication. Serial communication requires only a small number of transmission lines compared to parallel communication, and thus can reduce cost and complexity. Serial communication can be classified into synchronous serial communication and asynchronous serial communication. In synchronous serial communication, a common clock signal is used by a transmitting end and a receiving end to synchronize data transmission. In asynchronous serial communication, a transmitting end and a receiving end use a start bit and a stop bit to identify the start and end of data, and a clock signal is not required to synchronize data transmission.
Disclosure of Invention
The present disclosure provides a serial communication method and an electronic device for reducing additional protocol overhead.
In a first aspect, an embodiment of the present disclosure provides a serial communication method, including: receiving a back pressure signal sent by a data receiving end, wherein the back pressure signal indicates the buffer status of the data receiving end; and if the state of the buffer memory of the data receiving end meets the communication condition, sending data to the data receiving end.
In an implementation manner of the first aspect, sending data to the data receiving end includes: and sending the write data to a cache of the data receiving end, so that the data receiving end writes the write data from the cache into a memory of the data receiving end.
In an implementation manner of the first aspect, if a state of the buffer memory of the data receiving end meets a communication condition, sending data to the data receiving end includes: and in the instruction stage and/or the address stage, if the back pressure signal indicates that the buffer memory of the data receiving end is empty, the data is sent to the buffer memory of the data receiving end.
In an implementation manner of the first aspect, if a state of the buffer memory of the data receiving end meets a communication condition, sending data to the data receiving end includes: and in a data stage, if the back pressure signal indicates that the residual capacity of the buffer memory of the data receiving end is larger than the data quantity to be sent to the data receiving end, sending the data to the buffer memory of the data receiving end.
In an implementation manner of the first aspect, the serial communication method further includes: and in the instruction stage and/or the address stage, if the state of the cache of the data receiving end does not meet the communication condition, not entering the data stage.
In an implementation manner of the first aspect, in the instruction stage and/or the address stage, if the backpressure signal indicates that the buffered data sent to the data receiving end in the previous cycle has not been completely written into the memory of the data receiving end, the data stage is not entered.
In an implementation manner of the first aspect, the serial communication method further includes: and judging whether the state of the buffer memory of the data receiving end meets the communication condition according to the back pressure signal in the last clock period of the first clock period, wherein the first clock period is the clock period of the data sending end which is about to enter the data stage.
In an implementation manner of the first aspect, the serial communication method further includes: in the data stage, if the state of the buffer memory of the data receiving end does not meet the communication condition, suspending sending data to the data receiving end; and after the state of the buffer memory of the data receiving end meets the communication condition, sending data to the data receiving end.
In an implementation manner of the first aspect, the data receiving end is in an enabled state when sending data to the data receiving end is suspended.
In an implementation manner of the first aspect, sending data to the data receiving end includes: and if at least two burst transmissions are continuous in the storage address space, combining the at least two burst transmissions continuous in the storage address space into one instruction and sending the instruction to the data receiving end.
In a second aspect, embodiments of the present disclosure provide another serial communication method, the serial communication method including: configuring a back pressure signal according to the state of the cache, wherein the back pressure signal indicates the state of the cache; transmitting the back pressure signal to a data transmitting end; and receiving data transmitted by the data transmitting end, wherein the data is transmitted by the data transmitting end when the cached state meets the communication condition.
In an implementation manner of the second aspect, configuring the backpressure signal according to the cached state includes: in the non-enabled state, if the state of the buffer is empty, the back pressure signal enters a first state, otherwise, the back pressure signal enters a second state, the first state indicates that the state of the buffer meets the communication condition, and the second state indicates that the state of the buffer does not meet the communication condition.
In an implementation manner of the second aspect, configuring the backpressure signal according to the cached state includes: in the data stage, if the residual capacity of the buffer memory is larger than a threshold value, the back pressure signal enters a first state, otherwise, the back pressure signal enters a second state, the first state indicates that the state of the buffer memory meets the communication condition, and the second state indicates that the state of the buffer memory does not meet the communication condition.
In an implementation manner of the second aspect, configuring the backpressure signal according to the cached state includes: in the instruction stage and/or the address stage, if the state of the cache is empty, the back pressure signal enters a first state, otherwise, the back pressure signal enters a second state, the first state indicates that the state of the cache meets the communication condition, and the second state indicates that the state of the cache does not meet the communication condition.
In one implementation manner of the second aspect, the sending the backpressure signal to the data sending end includes: and in an enabling state, the back pressure signal is sent to the data receiving end through a back pressure signal interface.
In a third aspect, embodiments of the present disclosure provide yet another serial communication method, the serial communication method including: configuring a back pressure signal by a data receiving end according to the cached state, and sending the back pressure signal to a data sending end; receiving the back pressure signal by the data transmitting end; if the state of the buffer memory of the data receiving end meets the communication condition, the data sending end sends data to the data receiving end; and receiving, by the data receiving end, the data transmitted from the data transmitting end.
In an implementation manner of the third aspect, the data transmitting end includes a controller, and the data receiving end includes an external device separate from the controller.
In a fourth aspect, an embodiment of the present disclosure provides an electronic device, including: a memory configured to store a processor executable program; and a processor configured to invoke the program to perform the serial communication method according to any of the embodiments of the present disclosure.
Drawings
Fig. 1A is a schematic diagram of a communication system according to an embodiment of the disclosure.
FIG. 1B is a schematic diagram of a connection between a host and a device according to one embodiment of the disclosure.
FIG. 1C is a flow chart of a serial communication method according to an embodiment of the disclosure.
Fig. 2 is a schematic diagram showing signal states in an embodiment of the disclosure.
Fig. 3 is a schematic diagram illustrating data packet merging in an embodiment of the present disclosure.
Fig. 4 is a flow chart illustrating a serial communication method in an embodiment of the present disclosure.
Fig. 5 is a schematic diagram showing signal states in an embodiment of the disclosure.
Fig. 6 is a schematic diagram showing signal states in an embodiment of the disclosure.
Fig. 7 is a flow chart of a serial communication method according to an embodiment of the disclosure.
Fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the disclosure.
Detailed Description
Other advantages and effects of the present disclosure will become readily apparent to those skilled in the art from the following disclosure, which describes embodiments of the present disclosure by way of specific examples. The disclosure may be embodied or practiced in other different specific embodiments, and details within the subject specification may be modified or changed from various points of view and applications without departing from the spirit of the disclosure. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concepts of the disclosure by way of illustration, and only the components related to the disclosure are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Some communication systems include a host (host) and a plurality of devices (devices). The host and the device may interact with each other using a serial interaction protocol such as a high-speed bus (Hyperbus) protocol or an extensible serial peripheral interface (xSPI) protocol, so as to implement asynchronous communication between the host and the slave device. However, when the serial interactive protocol is used, the instruction structure of each data transmission is composed of three phases of an instruction phase (command phase), an address phase (address phase), and a data phase (data phase). The host will convert each burst transmission (burst) received into an instruction and send it to the device. However, in the scenario of multiple consecutive small bursts, since each burst has an instruction structure and a data address, this approach may increase the overhead of the transmission protocol and reduce the transmission efficiency.
In addition, when the host writes data to the device, the host cannot acquire the data storage condition of the device side, such as the buffer status of the device side, whether the data that has been transferred before is successfully transferred to the memory of the corresponding address, and the like. Therefore, additional protocol overhead must be added to query the device's cache state to ensure that the device-side cache can receive the data for subsequent transmission.
At least in view of the foregoing, an embodiment of the present disclosure provides a serial communication method. In the serial communication method, the device, as a data receiving end, actively transmits a back pressure signal indicating a buffer status thereof to the host. The host computer is used as a data sending end and can determine the cache state of the equipment according to the received back pressure signal and send data to the equipment when the cache state of the equipment meets the communication condition. In this way, the host does not need to add extra protocol overhead to query the cache state of the device, and the extra protocol overhead can be reduced.
Fig. 1A is a schematic diagram showing the structure of a communication system 1 in an embodiment according to the present disclosure. As shown in fig. 1A, the communication system 1 includes a host and n devices, where n is a positive integer. The serial communication method provided by some embodiments of the present disclosure is applicable to a host in the communication system 1. Other embodiments of the present disclosure provide serial communication methods applicable to devices in communication system 1. Still other embodiments of the present disclosure provide serial communication methods applicable to the communication system 1.
The host, as a master in the communication system 1, has control and communication initiation capabilities. In the communication system 1, the host controls the behavior of the devices 1 to n by transmitting instructions and data, and receives response data returned from the devices.
Devices 1 to n are slave devices in the communication system 1, which perform respective operations according to instructions and controls of the master device in response to the control of the master device.
Fig. 1B is a schematic diagram illustrating a connection relationship between a host and any device according to an embodiment of the present disclosure. As shown in fig. 1B, the host and the device are connected to each other through a data bus. In addition, the device sends backpressure signals to the host through a dedicated Input/Output interface (I/O). The device includes a buffer (buffer) and the backpressure signal is used to indicate a buffer status of the device to implement data backpressure for the write transfer.
Fig. 1C is a flowchart illustrating a serial communication method provided in an embodiment according to the present disclosure. The serial communication method provided by the embodiment of the present disclosure may be applied to, for example, the host shown in fig. 1A, that is, the host is used as the data transmitting end. As shown in fig. 1C, the serial communication method provided by the embodiment of the present disclosure includes the following steps S11 and S12.
In step S11, a backpressure signal transmitted by the data receiving end is received. The data receiving end may be any device in the communication system 1 shown in fig. 1A, but the disclosure is not limited thereto. In the embodiment of the disclosure, the back pressure signal is a feedback signal from the data receiving end to the host, and is used for indicating the buffer status of the data receiving end.
In some possible implementations, the backpressure signal includes a first state and a second state. The first state indicates that the state of the buffer memory of the data receiving end meets the communication condition, and the second state indicates that the state of the buffer memory of the data receiving end does not meet the communication condition. The first state is, for example, a high state, and the second state is, for example, a low state, but the disclosure is not limited thereto.
In some possible implementations, the backpressure signal may also include a third state. The third state is an intermediate state, indicating that the backpressure signal is in a non-driving state. The third state may be, for example, a high-resistance state, but the disclosure is not limited thereto.
In step S12, if the buffered state of the data receiving end meets the communication condition, the data is sent to the data receiving end.
According to an embodiment of the present disclosure, transmitting data to a data receiving end includes: and sending the write data to a cache of the data receiving end, so that the data receiving end writes the write data from the cache into a memory of the data receiving end.
According to an embodiment of the present disclosure, if the state of the buffer memory of the data receiving end meets the communication condition, sending the data to the data receiving end includes: in the instruction stage and/or the address stage, if the back pressure signal indicates that the buffer memory of the data receiving end is empty, the data is sent to the buffer memory of the data receiving end.
According to an embodiment of the present disclosure, if the state of the buffer memory of the data receiving end meets the communication condition, sending the data to the data receiving end includes: in the data stage, if the back pressure signal indicates that the remaining capacity of the buffer memory of the data receiving end is larger than the data amount to be sent to the data receiving end, the data is sent to the buffer memory of the data receiving end.
In accordance with an embodiment of the present disclosure, the serial communication method may further include: the data receiving end is determined by the enable signal cs_n. As shown in fig. 1A, a host is communicatively coupled to a plurality of devices. The host can determine one of the plurality of devices as a data receiving end by the enable signal cs_n. For example, a device may be selected as a data receiving end by pulling down an enable signal cs_n of the device, and after the data transmission is completed, the enable signal cs_n of the device is pulled up to terminate the data transmission.
The serial communication method provided according to an embodiment of the present disclosure may further include: in the instruction stage and/or the address stage, if the state of the cache of the data receiving end does not meet the communication condition, the data stage is not entered.
Specifically, the host sends a piece of data to the data receiving end, including an instruction phase, an address phase and a data phase. In the instruction phase, the host sends instructions or commands to the data receiving end to determine the type or operation of the subsequent communication. In the address stage, the host sends an address to the data receiving end to determine the transmission destination of the data. In the data stage, the host computer sends data to the data receiving end. However, in the instruction stage and/or the address stage, since the data of the last instruction may still be stored in the cache of the data receiving end, a data error may be caused if the host directly transmits the data to the data receiving end. At least in response to this problem, in embodiments of the present disclosure, the host determines the state of the cache at the data receiving end according to the backpressure signal during the instruction phase and/or the address phase. And when the state of the buffer memory of the data receiving end does not meet the communication condition, the data stage is not entered. And when the state of the buffer memory of the data receiving end meets the communication condition, entering a data stage and sending data to the data receiving end. By the method, data errors caused by indistinguishable data of the front instruction and the rear instruction can be effectively avoided.
According to an embodiment of the present disclosure, in the instruction stage and/or the address stage, if the backpressure signal indicates that the buffered data sent to the data receiving end in the previous cycle has not been completely written into the memory of the data receiving end, the data stage is not entered.
In accordance with an embodiment of the present disclosure, the serial communication method may further include: and judging whether the state of the buffer memory of the data receiving end meets the communication condition according to the back pressure signal in the last clock period of the first clock period, wherein the first clock period is the clock period of the data sending end which is about to enter the data stage.
In particular, since there is a delay between the host transmitting data and the data receiving data, the delay includes, but is not limited to, a path delay (path delay). In order to ensure that the host can determine that the state of the buffer memory of the data receiving end is empty according to the back pressure signal in the instruction stage and/or the address stage, that is, the buffer memory of the data receiving end does not have the data of the previous instruction, in the embodiment of the present disclosure, the host determines whether the state of the buffer memory of the data receiving end meets the communication condition according to the back pressure signal only in the last clock cycle (that is, the last clock cycle of the first clock cycle) before entering the data stage. If the state of the buffer memory of the data receiving end is judged to meet the communication condition in the clock period, the host enters a data stage; otherwise, the host computer does not enter the data stage, and continues to judge whether the state of the buffer memory of the data receiving end meets the communication condition in the next clock period.
In some possible implementations, there is a time difference between the enable signal cs_n being a disable state and the instruction phase/address phase of several cycles, which can cover the path delay of the backpressure signal transmission. Thus, as long as the host is delayed as much as possible to determine the backpressure signal in the instruction stage/address stage, for example, in the last clock cycle of the first clock cycle, an accurate backpressure signal can be sampled without sampling the backpressure signal of the third state or the previous instruction.
In accordance with an embodiment of the present disclosure, the serial communication method may further include: in the data stage, if the state of the buffer memory of the data receiving end does not meet the communication condition, suspending sending data to the data receiving end; and after the state of the buffer memory of the data receiving end meets the communication condition, continuing to send the data to the data receiving end.
Referring to fig. 2, in some possible implementations, when the host pauses sending data to the data receiving end, the data synchronizing clock signals clk of both parties are not flipped any more, and the data receiving end is in an enabled state. For example, in some embodiments it may be ensured that the data receiving end is continuously in the enabled state by keeping the enable signal cs_n of the data receiving end low.
According to an embodiment of the present disclosure, transmitting data to a data receiving end includes: if at least two bursts are continuous in the storage address space, combining the at least two bursts continuous in the storage address space into one instruction and sending the instruction to the data receiving end.
Specifically, when using a serial interaction protocol, the instruction structure of each data transfer includes an instruction phase, an address phase, and a data phase. For the scenario of multiple consecutive small bursts, since each burst has an instruction structure and a data address, this increases the overhead of the transmission protocol and reduces the transmission efficiency. At least to this problem, in the embodiments of the present disclosure, the host merges at least two bursts that are consecutive in the storage address space into one instruction and sends the instruction to the data receiving end. FIG. 3 is an exemplary diagram illustrating merging three small bursts into one instruction in accordance with an embodiment of the present disclosure. Wherein burst1, burst2, and burst3 are 3 bursts contiguous in memory address space. As shown in fig. 3, after the burst1, burst2 and burst3 are combined into one instruction, the protocol overhead of the instruction stage and the address stage when a plurality of instructions are sent can be saved, and the effect of improving the transmission bandwidth is achieved.
In some possible implementations, the host makes a determination of the address and length of the currently received burst to determine whether the currently received burst is contiguous with the instruction being transferred or about to be transferred on the memory address space. If continuous, the currently received burst and the instruction which is being transmitted or is to be transmitted are combined and then transmitted to the data receiving end.
Fig. 4 is a flowchart illustrating another serial communication method provided in an embodiment according to the present disclosure. The serial communication method provided by the embodiment of the present disclosure may be applied to any device shown in fig. 1A, for example, that is, any device is used as a data receiving end. As shown in fig. 4, the serial communication method provided by the embodiment of the present disclosure includes the following steps S41 to S43.
In step S41, the backpressure signal is configured according to the buffered state. The backpressure signal indicates the status of the buffer at the data receiving end.
In step S42, the back pressure signal is sent to the data transmitting end.
In step S43, data transmitted by the data transmitting end is received. And the data sending end sends data to the data receiving end when the cached state meets the communication condition.
Figure 5 is a schematic diagram illustrating configuring backpressure signals according to the state of a cache in an embodiment of the present disclosure. As shown in fig. 5, in the embodiment of the present disclosure, when the enable signal cs_n of the data receiving end is in the non-enabled state, if the state of the buffer is empty, that is, the buffer does not include the data of the last instruction, the back pressure signal enters the first state; otherwise, the backpressure signal enters the second state. The first state indicates that the state of the cache satisfies the communication condition and the second state indicates that the state of the cache does not satisfy the communication condition.
According to an embodiment of the present disclosure, when the enable signal cs_n of the data receiving end is in an enable state, configuring the backpressure signal according to the state of the cache in the instruction stage and/or the address stage includes: if the buffered state is empty, the backpressure signal enters the first state, otherwise the backpressure signal enters the second state.
Specifically, the data of two instructions cannot be cached in the cache of the data receiving end at the same time, because the cache cannot acquire the length of the instruction transmission in advance. When the data of two instructions are stored in the cache at the same time, this may cause the data to be written to the memory of the wrong address because there is no boundary between the data. At least in view of this technical problem, in embodiments of the present disclosure, the backpressure signal is configured in the instruction stage and/or the address stage according to whether the state of the cache is empty. After the data receiving end writes the data of the last instruction into the memory from the buffer memory, the buffer memory state is empty, and after that, the back pressure signal of the data receiving end enters the first state, and the host can enter the data stage.
According to an embodiment of the present disclosure, when the enable signal cs_n of the data receiving end is in an enable state, during a data phase, configuring the backpressure signal according to the buffered state includes: if the remaining capacity of the buffer is greater than the threshold, the back pressure signal enters a first state, otherwise the back pressure signal enters a second state.
Specifically, due to the path delay between the host and the data receiving end, part of the data sent by the host can be received by the data receiving end after a period of delay. Therefore, the backpressure signal cannot enter the second state until the buffer at the data receiving end is full. At least in response to this problem, in embodiments of the present disclosure, the backpressure signal is configured during the data phase according to whether the remaining capacity in the buffer is greater than a threshold. Wherein the threshold may be an advance determined based on a path delay between the host and the data receiver, also referred to as a watermark. The waterline of the data receiving end is used for caching part of data which is sent out by the host but not received by the data receiving end yet. And when the advance is met, the back pressure signal enters a second state to inform the host to stop sending data continuously.
As can be seen from the above description, in the serial communication method provided by the embodiments of the present disclosure, when the enable signal cs_n is in the enable state, in the instruction stage and/or the address stage, the data receiving end configures the back pressure signal by using whether the buffered state is empty; in the data phase, the data receiving end uses the waterline to configure the backpressure signal. After the data phase of one transmission is completed, the enabling signal cs_n enters a non-enabling state, and the data receiving end switches to configure the back pressure signal according to whether the buffered state is empty.
In accordance with an embodiment of the present disclosure, transmitting the backpressure signal to the data transmitting end includes: in the enabling state, the back pressure signal is sent to the data receiving end through the back pressure signal interface.
Specifically, in a multi-device scenario, in order to avoid causing collisions between multi-device backpressure signals, a device is to control the backpressure signals at the output instants of the backpressure signal interface. In some possible implementations, the device is only allowed to output the backpressure signal to the backpressure signal interface after the enabling signal cs_n of the device has changed to an enabling state, i.e. only when the device is selected as the data receiving end.
Fig. 6 is an example diagram illustrating an enable signal cs_n and a backpressure signal in an embodiment according to the present disclosure. As shown in fig. 6, at time t1, the data bus is in an idle phase, and the enable signal cs_n of the data receiving end is pulled up to enter a disabled state, in which the backpressure signal is not allowed to be output to the backpressure signal interface. Due to the path delay etc., the back-pressure signal will enter the third state after a delay from the back-pressure signal interface point of view. Wherein the third state is a non-driving state in which no actuation is given. At time t2, the enable signal cs_n of the data receiving end is pulled down to enter an enable state, and the back pressure signal enters a second state after a period of delay. the state of the buffer memory of the data receiving end at the time t3 meets the communication condition, the back pressure signal enters the first state, and the host enters the data stage and transmits data after a period of delay.
Fig. 7 is a flowchart illustrating yet another serial communication method provided in an embodiment according to the present disclosure. This serial communication method is applicable to, for example, the communication system 1 shown in fig. 1A. As shown in fig. 7, the serial communication method includes the following steps S71 to S74.
In step S71, the data receiving end configures a back pressure signal according to the buffered state, and sends the back pressure signal to the data sending end.
In step S72, the backpressure signal is received by the data transmitting end.
In step S73, if the buffered state of the data receiving end satisfies the communication condition, the data transmitting end transmits data to the data receiving end.
In step S74, the data receiving end receives the data transmitted from the data transmitting end.
It should be understood that, in the serial communication method provided in the embodiment of the present disclosure, the communication process of the data transmitting end is similar to the serial communication method shown in fig. 1C, and the communication process of the data receiving end is similar to the serial communication method shown in fig. 4, which is not repeated here.
According to an embodiment of the present disclosure, the data transmitting end includes a controller, and the data receiving end includes an external device separate from the controller.
Fig. 8 is a schematic diagram showing the structure of the electronic device 8 in an embodiment according to the present disclosure. As shown in fig. 8, the electronic device 8 in the embodiment of the present disclosure includes a memory 81 and a processor 82.
The memory 81 is configured to store a processor executable program. In some possible implementations, the memory 81 may include a ROM, RAM, magnetic disk, U-disk, memory card, or optical disk, etc. various media that can store program code.
In particular, memory 81 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM) and/or cache memory. The electronic device 8 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. Memory 81 may include at least one program product having a set (e.g., at least one) of program modules configured to carry out the functions of the various embodiments of the disclosure.
The processor 82 is connected to the memory 81 and is configured to invoke a program to perform the serial communication method provided according to any of the embodiments of the present disclosure.
In some embodiments, the processor 82 may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), or the like. In other embodiments, the processor 82 may also be a digital signal processor (Digital Signal Processor, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components.
In some possible implementations, the electronic device 8 in this embodiment may also include a display 83. The display 83 is communicatively coupled to the memory 81 and the processor 82 and is configured to display a graphical user interface (Graphical User Interface, GUI) associated with the serial communication method.
In summary, in the serial communication method provided in the embodiments of the present disclosure, the data receiving end actively transmits the back pressure signal indicating the buffered state to the data transmitting end. The data sending terminal can determine the buffer status of the data receiving terminal according to the received back pressure signal, and send data to the data receiving terminal when the buffer status of the data receiving terminal meets the communication condition. By the method, the data sending end does not need to increase extra protocol overhead to inquire the state of the buffer memory of the data receiving end, and the extra protocol overhead can be reduced.
In addition, according to the serial communication method provided by some embodiments of the present disclosure, by merging at least two bursts that are consecutive in the memory address space into one instruction for transmission, the protocol overhead of the instruction phase and the address phase can be reduced.
Accordingly, the present disclosure is highly industrial in value, effectively overcoming various drawbacks in the prior art.
The above embodiments are merely illustrative of the principles of the present disclosure and its efficacy, and are not intended to limit the disclosure. Modifications and variations may be made to the above-described embodiments by those of ordinary skill in the art without departing from the spirit and scope of the present disclosure. Accordingly, it is intended that all equivalent modifications and variations which a person having ordinary skill in the art would accomplish without departing from the spirit and technical spirit of the present disclosure be covered by the claims of the present disclosure.

Claims (18)

1. A serial communication method, comprising:
receiving a back pressure signal sent by a data receiving end, wherein the back pressure signal indicates the buffer status of the data receiving end; and
and if the state of the buffer memory of the data receiving end meets the communication condition, sending data to the data receiving end.
2. The serial communication method according to claim 1, wherein transmitting data to the data receiving end comprises:
and sending the write data to a cache of the data receiving end, so that the data receiving end writes the write data from the cache into a memory of the data receiving end.
3. The serial communication method according to claim 1, wherein transmitting data to the data receiving terminal if the state of the buffer memory of the data receiving terminal satisfies a communication condition comprises:
and in the instruction stage and/or the address stage, if the back pressure signal indicates that the buffer memory of the data receiving end is empty, the data is sent to the buffer memory of the data receiving end.
4. The serial communication method according to claim 1, wherein transmitting data to the data receiving terminal if the state of the buffer memory of the data receiving terminal satisfies a communication condition comprises:
and in a data stage, if the back pressure signal indicates that the residual capacity of the buffer memory of the data receiving end is larger than the data quantity to be sent to the data receiving end, sending the data to the buffer memory of the data receiving end.
5. The serial communication method according to claim 1, further comprising:
and in the instruction stage and/or the address stage, if the state of the cache of the data receiving end does not meet the communication condition, not entering the data stage.
6. The serial communication method according to claim 5, wherein during the instruction phase and/or the address phase, the data phase is not entered if the backpressure signal indicates that the buffered data sent to the data receiving end in the previous cycle has not been written to the memory of the data receiving end in its entirety.
7. The serial communication method according to claim 5, further comprising:
and judging whether the state of the buffer memory of the data receiving end meets the communication condition according to the back pressure signal in the last clock period of the first clock period, wherein the first clock period is the clock period of the data sending end which is about to enter the data stage.
8. The serial communication method according to claim 1, further comprising:
in the data stage, if the state of the buffer memory of the data receiving end does not meet the communication condition, suspending sending data to the data receiving end; and
and after the state of the buffer memory of the data receiving end meets the communication condition, sending data to the data receiving end.
9. The serial communication method according to claim 8, wherein the data receiving terminal is in an enabled state while suspending transmission of data to the data receiving terminal.
10. The serial communication method according to claim 1, wherein transmitting data to the data receiving end comprises:
and if at least two burst transmissions are continuous in the storage address space, combining the at least two burst transmissions continuous in the storage address space into one instruction and sending the instruction to the data receiving end.
11. A serial communication method, comprising:
configuring a back pressure signal according to the state of the cache, wherein the back pressure signal indicates the state of the cache;
transmitting the back pressure signal to a data transmitting end; and
and receiving the data sent by the data sending end, wherein the data is sent by the data sending end when the cached state meets the communication condition.
12. The serial communication method of claim 7, wherein configuring the backpressure signal based on the buffered state comprises:
in the non-enabled state, if the state of the buffer is empty, the back pressure signal enters a first state, otherwise, the back pressure signal enters a second state, the first state indicates that the state of the buffer meets the communication condition, and the second state indicates that the state of the buffer does not meet the communication condition.
13. The serial communication method of claim 7, wherein configuring the backpressure signal based on the buffered state comprises:
in the data stage, if the residual capacity of the buffer memory is larger than a threshold value, the back pressure signal enters a first state, otherwise, the back pressure signal enters a second state, the first state indicates that the state of the buffer memory meets the communication condition, and the second state indicates that the state of the buffer memory does not meet the communication condition.
14. The serial communication method of claim 7, wherein configuring the backpressure signal based on the buffered state comprises:
in the instruction stage and/or the address stage, if the state of the cache is empty, the back pressure signal enters a first state, otherwise, the back pressure signal enters a second state, the first state indicates that the state of the cache meets the communication condition, and the second state indicates that the state of the cache does not meet the communication condition.
15. The serial communication method of claim 7, wherein transmitting the backpressure signal to the data transmitting terminal comprises:
and in an enabling state, the back pressure signal is sent to the data receiving end through a back pressure signal interface.
16. A serial communication method, comprising:
configuring a back pressure signal by a data receiving end according to the cached state, and sending the back pressure signal to a data sending end;
receiving the back pressure signal by the data transmitting end;
if the state of the buffer memory of the data receiving end meets the communication condition, the data sending end sends data to the data receiving end; and
and the data receiving end receives the data sent from the data sending end.
17. The serial communication method according to claim 16, wherein the data transmitting end includes a controller, and the data receiving end includes an external device separate from the controller.
18. An electronic device, comprising:
a memory configured to store a processor executable program; and
a processor configured to call the program to perform the serial communication method according to any one of claims 1 to 17.
CN202310568046.2A 2023-05-18 2023-05-18 Serial communication method and electronic equipment Pending CN116644020A (en)

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CN202310568046.2A CN116644020A (en) 2023-05-18 2023-05-18 Serial communication method and electronic equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310568046.2A CN116644020A (en) 2023-05-18 2023-05-18 Serial communication method and electronic equipment

Publications (1)

Publication Number Publication Date
CN116644020A true CN116644020A (en) 2023-08-25

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