CN116633277A - Low-noise amplifier applied to front end of Internet of things - Google Patents
Low-noise amplifier applied to front end of Internet of things Download PDFInfo
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- CN116633277A CN116633277A CN202310576876.XA CN202310576876A CN116633277A CN 116633277 A CN116633277 A CN 116633277A CN 202310576876 A CN202310576876 A CN 202310576876A CN 116633277 A CN116633277 A CN 116633277A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The application relates to a low-noise amplifier applied to the front end of the Internet of things. The low noise amplifier includes: the substrate of the first PMOS tube is connected with the source of the first PMOS tube, the substrate of the second PMOS tube is connected with the source of the second PMOS tube, the grid of the first PMOS tube is connected with the ground through a first resistor, the third inductor is connected with the drain of the NMOS tube through a second capacitor, the third inductor is connected with a fourth inductor, a fifth inductor and the third capacitor, the fourth inductor is connected with the drain of the first PMOS tube and the fourth capacitor, the fourth capacitor is respectively connected with the grid of the second PMOS tube and the second resistor, the drain of the second PMOS tube is connected with the output end, the drain of the second PMOS tube is connected with the fifth inductor, the grid of the NMOS tube is connected with a sixth inductor and a fifth capacitor, the sixth inductor is connected with the source of the seventh inductor, the seventh capacitor and the NMOS tube, and the substrate of the NMOS tube is connected with forward bias voltage through the fourth resistor, so that ultralow direct current power consumption of the low-noise amplifier is realized.
Description
Technical Field
The application relates to the technical field of electronic communication, in particular to a low-noise amplifier applied to the front end of the Internet of things.
Background
The low noise amplifier (low noise amplifier, LNA) is a front end module of the RF receiver or a noise selection component of a low noise amplifier in the receiver. For a very good receiver, minimum noise and maximum gain are required.
On the premise of ensuring the performance, the maximum reduction of the power consumption of the circuit becomes an important point in the research of the current radio frequency integrated circuits, various radio frequency circuit architectures are not separated from a radio frequency receiving and transmitting link part, a radio frequency receiving front end part in the radio frequency receiving and transmitting link comprises a low noise amplifier and a down-conversion mixer, and radio frequency signals received by an antenna are primarily amplified and down-converted into intermediate frequency signals and are transmitted to a next stage of circuit for further signal processing. Because the rf signal received by the antenna needs to be processed, in order to ensure the sensitivity of the system, that is, the minimum signal that the system can receive and process, it needs to ensure that the rf receiving front end keeps extremely low input equivalent noise, so in the whole receiving link, the power consumption of the rf receiving front end occupies a significant part, the pursuit of low power consumption firstly requires the reduction of the power consumption of the rf receiving front end, the influence of the noise and gain of the low noise amplifier in the rf front end on the post-stage circuit is extremely critical, and the low power consumption rf front end always has extremely important position in the engineering technical field, which is one of the key points and hot spots of people's research.
The low noise amplifier (low noise amplifier, LNA) is used as a first stage active amplifying circuit of the radio frequency receiving front end, and is important to the overall performance of the communication system. The noise of the low noise amplifier is considered first, and in the multistage cascade circuit, the noise coefficient of the low noise amplifier at the front end has the greatest influence on the noise performance of the whole receiver. Second, the gain of the low noise amplifier must be large enough to reduce the effect of post-stage circuit noise on the overall system noise performance. In addition, the low-noise amplifier is used as the most main power consumption module of the radio frequency receiving front end, and the design of the low-power consumption low-noise amplifier plays a vital role in reducing the power consumption of the whole radio frequency receiving front end. In the design of radio frequency integrated circuits, the requirement for low power consumption often limits other performance of the radio frequency circuit, such as high gain, low noise, high linearity, and large dynamic range. Different performance indexes often have the characteristics of mutual restriction and mutual contradiction, so that the design of the ultra-low power consumption radio frequency integrated circuit is a process of searching the optimal comprehensive performance folding point.
With the growth of the wireless communication market, there is an increasing demand for low power consumption, low cost and high performance receivers. Radios for multi-standard applications are emerging, ultimately working on cognitive radio solutions. Whether these systems are implemented as flexible radios or follow digital RF methods, low noise amplifiers are an inevitable critical circuit. In a circuit of a low noise amplifier, such as a common source LNA, has a low noise figure and a high level gain. It can achieve perfect input matching, but at the cost of power consumption and chip area. Therefore, the current low noise amplifier consumes much power.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a low noise amplifier applied to the front end of the internet of things that can reduce the power consumption of the low noise amplifier.
A low noise amplifier for use in an internet of things front end, the low noise amplifier comprising: the first PMOS transistor, the second PMOS transistor, the NMOS transistor, the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, the sixth capacitor, the seventh capacitor, the first inductor, the second inductor, the third inductor, the fourth inductor, the fifth inductor, the sixth inductor, the seventh inductor, the first resistor, the second resistor, the third resistor and the fourth resistor;
the power supply is connected with the ground through the first capacitor, one end of the first inductor and one end of the second inductor are connected with the power supply, the other end of the first inductor is connected with the source electrode of the first PMOS tube, the other end of the second inductor is connected with the source electrode of the second PMOS tube, the substrate of the first PMOS tube is connected with the source electrode of the first PMOS tube, the substrate of the second PMOS tube is connected with the source electrode of the second PMOS tube, the grid electrode of the first PMOS tube is connected with the ground through the first resistor and is connected with one end of the third inductor and the drain electrode of the NMOS tube through the second capacitor, the other end of the third inductor is respectively connected with one end of the fourth inductor, one end of the fifth inductor and one end of the third capacitor, the other end of the third capacitor is grounded, the other end of the fourth inductor is respectively connected with the drain electrode of the first PMOS tube and one end of the fourth capacitor, the other end of the fourth capacitor is respectively connected to the grid electrode of the second PMOS tube and one end of the second resistor, the other end of the second resistor is grounded, the drain electrode of the second PMOS tube is connected to the output end of the low noise amplifier, meanwhile, the drain electrode of the second PMOS tube is connected to the other end of the fifth inductor, the grid electrode of the NMOS tube is connected to one end of the sixth inductor and one end of the fifth capacitor, the other end of the sixth inductor is connected to one end of the third resistor and one end of the sixth capacitor, the other end of the third resistor is connected with bias voltage, the other end of the sixth capacitor is grounded, the other end of the fifth capacitor is connected to one end of the seventh inductor, one end of the seventh capacitor and the source electrode of the NMOS tube, the other end of the seventh capacitor is connected with input voltage, and the substrate of the NMOS tube is connected with a forward body bias voltage through a fourth resistor.
In one embodiment, the first inductor and the second inductor are source degeneration inductors.
The low noise amplifier applied to the front end of the Internet of things is connected to a power supply through one end of a first inductor and one end of a second inductor, the other end of the first inductor is connected to a source electrode of a first PMOS tube, the other end of the second inductor is connected to a source electrode of a second PMOS tube, a substrate of the first PMOS tube is connected to the source electrode of the first PMOS tube, a substrate of the second PMOS tube is connected to the source electrode of the second PMOS tube, forward body bias technology is realized, the power consumption is reduced, a grid electrode of the first PMOS tube is connected to the ground through a first resistor and is connected to one end of a third inductor and the drain electrode of an NMOS tube through a second capacitor, the other end of the third inductor is respectively connected to one end of a fourth inductor, one end of a fifth inductor and one end of a third capacitor, the other end of the third capacitor is grounded, the other end of the fourth inductor is respectively connected to the drain electrode of the first PMOS tube and one end of the fourth capacitor, the other end of the fourth capacitor is respectively connected to the grid electrode of the second PMOS tube and one end of the second resistor, the other end of the second resistor is grounded, a current multiplexing framework is established, the drain electrode of the second PMOS tube is connected to the output end of the low noise amplifier, meanwhile, the drain electrode of the second PMOS tube is connected to the other end of the fifth inductor, the grid electrode of the NMOS tube is connected to one end of the sixth inductor and one end of the fifth capacitor, the other end of the sixth inductor is connected to one end of the third resistor and one end of the sixth capacitor, the other end of the third resistor is connected to the ground, the other end of the sixth capacitor is connected to one end of the seventh inductor, one end of the seventh capacitor and the source electrode of the NMOS tube, the other end of the seventh capacitor is connected to the input voltage, the substrate of the NMOS tube is connected to the forward body bias voltage through the fourth resistor, and mutual inductance feedback is formed for amplifying the gain, thereby, ultra-low direct current power consumption of the low noise amplifier is realized, but also has optimized gain performance, noise figure and compact size.
Drawings
Fig. 1 is a schematic structural diagram of a low noise amplifier applied to a front end of an internet of things in an embodiment.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
In one embodiment, as shown in fig. 1, there is provided a low noise amplifier applied to a front end of an internet of things, the low noise amplifier comprising: the first PMOS transistor M1, the second PMOS transistor M2, the NMOS transistor M3, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, the first inductor L1, the second inductor L2, the third inductor L3, the fourth inductor L4, the fifth inductor L5, the sixth inductor L6, the seventh inductor L7, the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4;
the power supply VDD is connected with the ground through a first capacitor C1, one end of a first inductor L1 and one end of a second inductor L2 are connected to the power supply VDD, the other end of the first inductor L1 is connected with the source electrode of a first PMOS tube M1, the other end of the second inductor L2 is connected with the source electrode of a second PMOS tube M2, the substrate of the first PMOS tube M1 is connected with the source electrode of the first PMOS tube M1, the substrate of the second PMOS tube M2 is connected with the source electrode of the second PMOS tube M2, the grid electrode of the first PMOS tube M1 is connected with the ground through a first resistor R1 and is connected with one end of a third inductor L3 and the drain electrode of an NMOS tube M3 through a second capacitor C2, the other end of the third inductor L3 is respectively connected with one end of a fourth inductor L4, one end of a fifth inductor L5 and one end of the third capacitor C3, the other end of the third capacitor C3 is grounded, the other end of the fourth inductor L4 is respectively connected with the drain electrode of the first PMOS tube M1 and one end of the fourth capacitor C4, the other end of the fourth capacitor C4 is respectively connected to the grid electrode of the second PMOS tube M2 and one end of the second resistor R2, the other end of the second resistor R2 is grounded, the drain electrode of the second PMOS tube M2 is connected to the output end RFOUT of the low noise amplifier, meanwhile, the drain electrode of the second PMOS tube M2 is connected to the other end of the fifth inductor L5, the grid electrode of the NMOS tube M3 is connected to one end of the sixth inductor L6 and one end of the fifth capacitor C5, the other end of the sixth inductor L6 is connected to one end of the third resistor R3 and one end of the sixth capacitor C6, the other end of the third resistor R3 is connected to the bias voltage VE, the other end of the sixth capacitor C6 is grounded, the other end of the fifth capacitor C5 is connected to one end of the seventh inductor L7, one end of the seventh capacitor C7 and the source electrode of the NMOS tube M3, the other end of the seventh capacitor C7 is connected to the input voltage RFIN, and the substrate of the NMOS tube M3 is connected to the forward body bias voltage VB through the fourth resistor R4.
The substrates of the first PMOS tube M1 and the second PMOS tube M2 are respectively connected to the respective sources, so that a forward body bias technology can be realized, and the power consumption is reduced.
The current multiplexing architecture is established by the ac ground provided by the drain inductance (i.e., the third inductance L3, the fourth inductance L4, and the fifth inductance L5) and the bypass capacitance (i.e., the third capacitance C3 and the fourth capacitance C4), so that the dc power consumption is reduced.
The NMOS transistor M3, the sixth inductor L6, the seventh inductor L7, and the fifth capacitor C5 form a common gate with transformer coupling, so as to improve the small signal transconductance, and the sixth inductor L6 and the seventh inductor L7 form mutual inductance feedback for amplifying the gain.
The substrate of the NMOS transistor M3 is connected to the forward body bias voltage VB through a fourth resistor R4, and noise and gain are reduced through a forward body bias technique.
The first capacitor C1 is a blocking capacitor, so that noise can be reduced.
It should be understood that the third resistor R3, the sixth inductor L6, the sixth capacitor C6 and the fifth capacitor C5 form a bias circuit of the NMOS transistor NM3, the bias circuit, the NMOS transistor M3, the seventh inductor L7 and the fourth resistor R4 form a first stage amplifying module, the first PMOS transistor M1, the second capacitor C2, the first resistor R1, the fourth inductor L4 and the third inductor L3 form a second stage amplifying module of the circuit, the second capacitor C2 is a blocking capacitor, and the fourth inductor L4, the fourth capacitor C4 and the second resistor R2 form an inter-stage matching circuit between the first PMOS transistor M1 and the second PMOS transistor M2, and the second PMOS transistor M2 and the fifth inductor L5 are third stage amplifying modules.
In one embodiment, the first inductor L1 and the second inductor L2 are source degeneration inductors.
It should be appreciated that the first inductance L1 and the second inductance L2 are source degeneration inductances that can be gain and noise matched simultaneously.
The low noise amplifier applied to the front end of the internet of things is characterized in that one end of a first inductor L1 and one end of a second inductor L2 are connected to a power supply VDD, the other end of the first inductor L1 is connected to the source of a first PMOS tube M1, the other end of the second inductor L2 is connected to the source of a second PMOS tube M2, the substrate of the first PMOS tube M1 is connected to the source of the first PMOS tube M1, the substrate of the second PMOS tube M2 is connected to the source of the second PMOS tube M2, the forward body bias technology is realized, the power consumption is reduced, the grid electrode of the first PMOS tube M1 is connected to the ground through a first resistor R1 and is connected to one end of a third inductor L3 and the drain of an NMOS tube M3 through a second capacitor C2, the other end of the third inductor L3 is respectively connected to one end of a fourth inductor L4, one end of a fifth inductor L5 and one end of a third capacitor C3 are grounded, the other end of the fourth inductor L4 is respectively connected to the drain of the first PMOS tube M1 and one end of the fourth capacitor C4, the other end of the fourth capacitor C4 is respectively connected to the grid electrode of the second PMOS tube M2 and one end of the second resistor R2, the other end of the second resistor R2 is grounded, a current multiplexing architecture is established, the drain electrode of the second PMOS tube M2 is connected to the output end RFOUT of the low noise amplifier, meanwhile, the drain electrode of the second PMOS tube M2 is connected to the other end of the fifth inductor L5, the grid electrode of the NMOS tube M3 is connected to one end of the sixth inductor L6 and one end of the fifth capacitor C5, the other end of the sixth inductor L6 is connected to one end of the third resistor R3 and one end of the sixth capacitor C6, the other end of the third resistor R3 is connected to the bias voltage VE, the other end of the sixth capacitor C6 is grounded, the other end of the fifth capacitor C5 is connected to one end of the seventh inductor L7, one end of the seventh capacitor C7, the source electrode of the NMOS tube M3, the other end of the seventh capacitor C7 is connected to the input voltage RFIN, the substrate of the NMOS tube M3 is connected with the forward body bias voltage VB through the fourth resistor R4 to form mutual inductance feedback for amplifying the gain, so that the ultralow direct current power consumption of the low-noise amplifier is realized, and the low-noise amplifier has optimized gain performance, noise coefficient and compact size. Has great application potential in ultra-low power wireless systems.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (2)
1. Be applied to low noise amplifier of thing networking front end, its characterized in that, low noise amplifier includes: the first PMOS transistor, the second PMOS transistor, the NMOS transistor, the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, the sixth capacitor, the seventh capacitor, the first inductor, the second inductor, the third inductor, the fourth inductor, the fifth inductor, the sixth inductor, the seventh inductor, the first resistor, the second resistor, the third resistor and the fourth resistor;
the power supply is connected with the ground through the first capacitor, one end of the first inductor and one end of the second inductor are connected with the power supply, the other end of the first inductor is connected with the source electrode of the first PMOS tube, the other end of the second inductor is connected with the source electrode of the second PMOS tube, the substrate of the first PMOS tube is connected with the source electrode of the first PMOS tube, the substrate of the second PMOS tube is connected with the source electrode of the second PMOS tube, the grid electrode of the first PMOS tube is connected with the ground through the first resistor and is connected with one end of the third inductor and the drain electrode of the NMOS tube through the second capacitor, the other end of the third inductor is respectively connected with one end of the fourth inductor, one end of the fifth inductor and one end of the third capacitor, the other end of the third capacitor is grounded, the other end of the fourth inductor is respectively connected with the drain electrode of the first PMOS tube and one end of the fourth capacitor, the other end of the fourth capacitor is respectively connected to the grid electrode of the second PMOS tube and one end of the second resistor, the other end of the second resistor is grounded, the drain electrode of the second PMOS tube is connected to the output end of the low noise amplifier, meanwhile, the drain electrode of the second PMOS tube is connected to the other end of the fifth inductor, the grid electrode of the NMOS tube is connected to one end of the sixth inductor and one end of the fifth capacitor, the other end of the sixth inductor is connected to one end of the third resistor and one end of the sixth capacitor, the other end of the third resistor is connected with bias voltage, the other end of the sixth capacitor is grounded, the other end of the fifth capacitor is connected to one end of the seventh inductor, one end of the seventh capacitor and the source electrode of the NMOS tube, the other end of the seventh capacitor is connected with input voltage, and the substrate of the NMOS tube is connected with a forward body bias voltage through a fourth resistor.
2. The low noise amplifier of claim 1, wherein the first inductance and the second inductance are source degeneration inductances.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310576876.XA CN116633277A (en) | 2023-05-22 | 2023-05-22 | Low-noise amplifier applied to front end of Internet of things |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310576876.XA CN116633277A (en) | 2023-05-22 | 2023-05-22 | Low-noise amplifier applied to front end of Internet of things |
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| CN116633277A true CN116633277A (en) | 2023-08-22 |
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| CN202310576876.XA Pending CN116633277A (en) | 2023-05-22 | 2023-05-22 | Low-noise amplifier applied to front end of Internet of things |
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- 2023-05-22 CN CN202310576876.XA patent/CN116633277A/en active Pending
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