CN111987998B - Noise cancellation low noise amplifier - Google Patents
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- CN111987998B CN111987998B CN202010836506.1A CN202010836506A CN111987998B CN 111987998 B CN111987998 B CN 111987998B CN 202010836506 A CN202010836506 A CN 202010836506A CN 111987998 B CN111987998 B CN 111987998B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
- H03F1/083—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers
- H03F1/086—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers with FET's
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/42—Modifications of amplifiers to extend the bandwidth
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Abstract
The application belongs to the field of radio frequency integrated circuits, and particularly relates to a noise cancellation low-noise amplifier based on passive voltage gain of a transformer, which comprises a first transistor and a second transistor, wherein a source electrode of the first transistor in a common-gate structure working state sequentially passes through the transformer and a capacitor and then is connected with a grid electrode of the second transistor in the common-source structure working state, the transformer couples an input signal with the second transistor to amplify the voltage, and the capacitor plays a role in isolating direct current and coupling signals; the transformer coupling structure is introduced, and a passive voltage amplification function is provided, so that the requirements on transconductance and gain of transistors with a common source structure in the design of the inverting amplifier are reduced, the difficulty in circuit design is reduced, and the low-noise amplifier with the noise cancellation structure can be applied to higher frequency bands, such as millimeter wave frequency bands.
Description
Technical Field
The application belongs to the field of radio frequency integrated circuits, and particularly relates to a noise cancellation low-noise amplifier based on passive voltage gain of a transformer.
Background
In communication systems and other electronic systems, it is often desirable to amplify signals in a certain Radio Frequency (RF) band with low noise using a circuit called a Low Noise Amplifier (LNA). The low-noise amplifier is a first-stage active circuit module of the receiving link, and is used for amplifying weak radio frequency signals received by the antenna on the premise of introducing less noise, so that the subsequent-stage circuit module contributes to the noise of the whole receiver link, and the overall performance of the receiver is ensured. The design needs to consider the compromise of a plurality of indexes such as gain, noise coefficient, bandwidth, linearity, power consumption and the like.
According to different application scenarios, the requirements and emphasis on LNA indicators are different, so to meet different application requirements, LNA circuits may have different architectures, and common architectures include: common-gate low noise amplifier, common-source common-gate low noise amplifier, distributed low noise amplifier, feedback low noise amplifier, noise cancellation structure low noise amplifier, and the like.
The circuit structures of the common-gate low-noise amplifier, the common-source common-gate low-noise amplifier, the distributed low-noise amplifier, the feedback low-noise amplifier and the like can be seen: THE DESIGN OF CMOS RADIO-FREQUENCY INTEGRADE CIRCUITS: section 9 HIGH-FREQUENCY AMPLIFIER DESIGN and Section 12 LNA DESIGN, thomas Lee, 2nd Edition; CMOS radio frequency integrated circuit design for analysis: chapter 8 Low noise amplifiers, chi Baoyong, et al. In order to obtain more excellent noise characteristics, a low noise amplifier circuit of a noise canceling structure is proposed by Federico Bruccoleri, eric a.m. klumprina and Bram Nauta in IEEE JSSC 2004, pages 275 to 281, "Wideband CMOS Low to Noise Amplifier Exploiting Thermal Noise Canceling". Noise cancellation techniques are widely recognized as one approach to improving low noise amplifiers. The principle of the noise cancellation technique is shown in fig. 1, noise current inoise inside the transistor M1 generates noise voltage signals with opposite phases at the drain and the source of the transistor M1, wherein the noise signal of the drain reaches the positive output port 12, the noise signal of the source reaches the negative output port 13 after passing through the negative amplifier 60, the phase is reversed, and the amplitude is amplified by AV times. The noise signal amplitudes at the normal phase output terminal 12 and the reverse phase output terminal 13 can be made equal as long as the amplification AV of the direction amplifier 60 is properly designed. In a differential circuit, signals of the same phase and equal amplitude will be cancelled out. The required signal enters the circuit from the input port 11 and is also divided into two paths, one path of the signal is amplified in phase by the common-gate structure transistor M1 and then reaches the positive-phase output port 12, and the other path of the signal reaches the negative-phase output port 13 after passing through the negative-phase amplifier 60, so that the phase is reversed and the amplitude is amplified by AV times. Thus, after the required signal is input by the input port 11, the amplification of the signal is obtained, and the conversion from single end to differential is realized. In the prior art, common source structure transistors are commonly used to implement the function of the inverting amplifier 60, as shown in fig. 2. The circuit structure in fig. 2 has its own limitation, and the amplification of the input signal and the noise signal both put high requirements on the span and gain of the inverting amplifying transistor M2, so that the practical circuit is difficult to implement and is not suitable for high-frequency application.
In the prior art, the invention patent numbers CN201310095232, CN201310095543 and CN201410431317 are that the source of the main common gate amplifier is directly coupled to the gate of the common source amplifier, and the comparison documents are differential input and differential output structures, and the input end of the structure needs to be added with a balun to realize the conversion from single end to differential signal, which introduces additional noise.
As shown in fig. 3, the proposed implementation manner of noise cancellation in the low noise amplifier (201310747466.3) based on the noise cancellation structure of the invention is that on the basis of fig. 1, positive feedback is implemented by transformer coupling at the source and drain of the common gate M1 and the common source M2, respectively, so that the effects of gain, noise reduction and cancellation of the miller effect of the MOS transistor can be provided. This configuration does not address the above-mentioned limitation of the relatively high transconductance and gain requirements of the cascode transistor M2. Meanwhile, the positive feedback structure has potential instability risks, and particularly in working occasions with higher frequency, no corresponding measures are given in the patent on how to prevent the risks.
Disclosure of Invention
In view of the above-mentioned shortcomings in the prior art, the present invention aims to reduce the requirements on transconductance and gain of a common source transistor in the design of a low noise amplifier with an existing noise cancellation structure, and at the same time, does not introduce unstable factors, so as to propose a noise cancellation low noise amplifier which can make the noise cancellation structure applicable to a wireless system with a higher frequency band.
In order to achieve the technical effects, the technical scheme of the application is as follows:
a noise canceling low noise amplifier, characterized by: the source electrode of the first transistor in the working state of the common-gate structure sequentially passes through a transformer and a capacitor and then is connected with the grid electrode of the second transistor in the working state of the common-source structure, the transformer couples an input signal with the second transistor and amplifies the voltage, and the capacitor plays a role in isolating direct current and coupling signals; thereby achieving biasing of the cascode transistors.
The transformer comprises a first inductor and a second inductor which are overlapped, one end of the first inductor and one end of the second inductor are connected to the ground, and the other end of the first inductor and the other end of the second inductor are used as input and output ports of the transformer.
Further, one end of the first inductor is connected to the source of the first transistor, one end of the second inductor is connected to one end of the capacitor, and the other end of the capacitor is connected to the gate of the second transistor.
Further, a signal input port of the circuit is connected with a source of the first transistor and a port of a first inductor in the transformer.
Further, the drain of the first transistor is connected to the first power supply bias and serves as a signal non-inverting output terminal of the circuit; the drain electrode of the second transistor is connected to the second power bias and is used as a signal inverting output end of the circuit; the signal normal phase output end and the signal reverse phase output end form a differential output port of the circuit structure together; the first power supply bias and the second power supply bias are used for isolating high-frequency signals and providing a direct current path, and the first power supply bias and the second power supply bias are formed by resistors, inductors or parallel connection of the resistors and the inductors; the other ends of the first power bias and the second power bias are connected to a power supply.
Further, the first transistor and the second transistor are Field Effect Transistors (FETs) including a drain, a source, and a gate.
Further, the drains of the first transistor and the second transistor are respectively connected with a third transistor with a common gate structure and a fourth transistor with a common gate structure, the signal normal phase output end of the differential output port is connected with the drain of the third transistor, and the signal reverse phase output end of the differential output port is connected with the drain of the fourth transistor with the common gate structure.
Further, a first gate bias port of the first transistor is connected to the bias circuit to obtain a bias voltage Vg1, and a second gate bias port of the second transistor is connected to the bias circuit to obtain a bias voltage Vg2.
Further, a third gate bias port of the third transistor is connected to the bias circuit to obtain a bias voltage Vg3, and a fourth gate bias port of the fourth transistor is connected to the bias circuit to obtain a bias voltage Vg4.
The invention has the beneficial effects that:
1. the transformer coupling structure is introduced, and a passive voltage amplification function is provided, so that the requirements on transconductance and gain of transistors with a common source structure in the design of the inverting amplifier are reduced, the difficulty in circuit design is reduced, and the low-noise amplifier with the noise cancellation structure can be applied to higher frequency bands, such as millimeter wave frequency bands.
2. According to the method and the device, on the implementation of the noise cancellation inverting amplifier-Av, the characteristic that the transformer structure brings passive voltage gain is utilized to better realize noise cancellation, so that the requirement on the common source stage amplifier is reduced.
3. The reduction of the transconductance of the transistor with the common source structure means the reduction of the power consumption, and the power consumption of the circuit can be reduced by adopting the structure provided by the invention.
4. When the transformer structure is realized on a chip, the area of the chip is not increased. The transformer is realized by superposition of two inductors, and when the transformer is realized on a chip, the occupied chip area of the transformer is almost the same as the occupied area of one inductor, so the occupied chip area is hardly increased.
5. The low noise amplifier realizing noise cancellation can be applied to amplification of low, medium and high frequency signals and has good matching and noise performance at the same time.
Drawings
Fig. 1 is a schematic diagram of a noise cancellation technique.
Fig. 2 is a drawing of the prior art.
Fig. 3 is a prior art drawing.
Figure 4 is a drawing of an embodiment of the present invention.
Fig. 5 is a diagram of an embodiment of the present invention.
In the accompanying drawings:
11-signal input port, 12-signal positive output, 13-signal negative output, 14-first gate bias port, 15-second gate bias port, 16-power supply, 17-ground, 18-third gate bias port, 19-fourth gate bias port, 31-capacitor, 41-first power supply bias, 42-second power supply bias, 51-first transistor, 52-second transistor, 53-third transistor, 54-fourth transistor, 70-transformer, 71-first inductor, 72-second inductor.
Detailed Description
The invention is capable of other embodiments and of being practiced or being carried out in various ways, apart from the preferred embodiment or embodiments disclosed below. It is therefore to be understood that the invention is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the drawings. If only one embodiment is described herein, the claims hereof are not to be limited to that embodiment. Furthermore, the claims hereof are not to be read restrictively unless there is clear and convincing evidence manifesting a certain exclusion, restriction, or disclaimer.
Fig. 1 shows the principle of a noise cancellation structure low noise amplifier, consisting of a noise current i inside a transistor M1 noise Will generate noise voltage signals with opposite phases at the drain and source of the transistor M1, wherein the noise signal of the drain reaches the signal positive output port 12, the noise signal of the source reaches the signal negative output port 13 after passing through the inverting amplifier 60, the phase is inverted, and the amplitude is amplified by A V Multiple times. As long as the amplification factor a of the direction amplifier 60 is properly designed V The noise signal amplitudes at the non-inverting output 12 and the inverting output 13 can be made equal. In a differential circuit, signals of the same phase and equal amplitude will be cancelled out. The required signal enters the circuit from the input port 11 and is also divided into two paths, one path of the signal is amplified in phase by the common-gate structure transistor M1 and then reaches the normal-phase output port 12, and the other path of the signal is amplified in phase by the reverse-phase amplifier 60 and then reaches the reverse-phase output port 13, so that the phase occursReverse, amplitude is amplified by A V Multiple times. Thus, after the required signal is input by the input port 11, the amplification of the signal is obtained, and the conversion from single end to differential is realized.
Fig. 2 shows a method of implementing a prior art noise cancellation structure low noise amplifier, using a common source structure transistor M2 to implement the function of the inverting amplifier 60 of fig. 1.
Fig. 3 shows an implementation method of a noise cancellation structure low noise amplifier in the prior art, and the function of the inverting amplifier 60 in fig. 1 is implemented by using a common-source structure transistor M2, which is different in that in this circuit, positive feedback is implemented by coupling with transformers at the source and drain of the common-gate transistor M1 and the common-source transistor M2, respectively.
Fig. 4 shows an embodiment of the invention in which a transformer 70 provides coupling between the input signal and the second transistor 52 of the common source structure and provides a voltage amplification. This reduces the requirements on the second transistor 52 of the common source structure, thereby reducing the difficulty of implementing the circuit on a chip and reducing power consumption. When implemented on a chip, the transformer 70 is formed by overlapping and combining the first inductor 71 and the second inductor 72, and the occupied chip area is almost the same as that of a single inductor, so that the area of the chip is not increased in the embodiment.
In the illustrated configuration, the first transistor 51 and the second transistor 52 are Field Effect Transistors (FETs) including a drain, a source, and a gate. The first transistor 51 is in a common gate operating state, i.e. a signal is input from the source and output from the drain. The second transistor 52 is in a common source operating state, i.e., a signal is input from the gate and output from the drain.
The transformer 70 is formed by overlapping and combining a first inductor 71 and a second inductor 72, and the ratio of the inductance of the two inductors and the mutual inductance between the two inductors determine the magnitude of the passive voltage gain of the transformer. One of the two inductors is connected to ground 17 at each end and the two outer ends serve as two input/output ports for transformer 70. The port of the first inductor 71 is connected to the source of the first transistor 51 and the port of the second inductor 72 is connected to one end of the capacitor 31. The capacitor 31 serves to isolate the direct current, couples the left and right of the signal, and has the other end connected to the gate of the second transistor 52.
The signal input port of the circuit is connected to the source of the first transistor 51 and to the port of the first inductor 71 in the transformer 70.
The drain of the first transistor 51 is connected to the first power supply bias 41 and serves as the signal non-inverting output 12 of the circuit. The drain of the second transistor 52 is connected to the second power supply bias 42 and serves as the signal inverting output 13 of the circuit. The outputs 12 and 13 together become a differential output port of the present circuit configuration. The first power supply bias 41 and 42 functions to isolate the high frequency signal while providing a direct current path, and once the first power supply bias 41 and 42 may consist of a resistor, an inductor, or a parallel connection of a resistor and an inductor. The other ends of the first power biases 41 and 42 are connected to the power supply 16.
Fig. 5 shows another embodiment, which differs from the embodiment of fig. 4 in that common-gate third transistors 53 and 54 are added to the drains of the first transistor 51 and the second transistor 52, respectively, and the differential output ports 12 and 13 are connected to the drains of the third transistors 53 and 54 instead. The embodiment of fig. 5 may increase the gain and output power of the circuit and optimize the output impedance characteristics compared to the embodiment of fig. 4, which has the disadvantage of requiring a higher supply voltage.
Examples the first gate bias ports 14, 15, 18, 19 of the transistors of fig. 4 and 5 are connected to bias circuits to obtain suitable bias voltages Vg1, vg2, vg3, vg4.
Example 2
The low noise amplifier of noise cancellation, including the first transistor 51 and second transistor 52, after passing through the transformer 70 and capacitor 31 sequentially, the source of the first transistor 51 in the operational state of the common gate structure is connected with gate of the second transistor 52 in the operational state of the common source structure, the transformer 70 couples the input signal and second transistor 52 and amplifies the voltage, the capacitor 31 plays the role of isolating direct current, coupled signal; thereby achieving biasing of the cascode transistors.
The transformer 70 includes a first inductor 71 and a second inductor 72 stacked together, one end of the first inductor 71 and one end of the second inductor 72 are both connected to the ground 17, and the other end of the first inductor 71 and the other end of the second inductor 72 serve as input and output ports of the transformer 70.
One end of the first inductor 71 is connected to the source of the first transistor 51, one end of the second inductor 72 is connected to one end of the capacitor 31, and the other end of the capacitor 31 is connected to the gate of the second transistor 52.
The signal input port 11 of the circuit is connected to the source of the first transistor 51 and to the port of the first inductor 71 in the transformer 70.
The drain of the first transistor 51 is connected to the first power supply bias 41 and serves as the signal non-inverting output 12 of the circuit; the drain of the second transistor 52 is connected to the second power supply bias 42 and serves as the signal inverting output 13 of the circuit; the signal normal phase output end 12 and the signal reverse phase output end 13 jointly form a differential output port of the circuit structure; the first power bias 41 and the second power bias 42 are used for isolating high-frequency signals and providing direct current paths, and the first power bias 41 and the second power bias 42 are composed of resistors, inductors or parallel connection of the resistors and the inductors; the other ends of the first power bias 41 and the second power bias 42 are connected to the power supply 16.
The first transistor 51 and the second transistor 52 are Field Effect Transistors (FETs) including a drain, a source, and a gate. The first gate bias port 14 of the first transistor 51 is connected to a bias circuit to obtain a bias voltage Vg1, and the second gate bias port 15 of the second transistor 52 is connected to the bias circuit to obtain a bias voltage Vg2.
Example 3
The low noise amplifier of noise cancellation, including the first transistor 51 and second transistor 52, after passing through the transformer 70 and capacitor 31 sequentially, the source of the first transistor 51 in the operational state of the common gate structure is connected with gate of the second transistor 52 in the operational state of the common source structure, the transformer 70 couples the input signal and second transistor 52 and amplifies the voltage, the capacitor 31 plays the role of isolating direct current, coupled signal; thereby achieving biasing of the cascode transistors.
The transformer 70 includes a first inductor 71 and a second inductor 72 stacked together, one end of the first inductor 71 and one end of the second inductor 72 are both connected to the ground 17, and the other end of the first inductor 71 and the other end of the second inductor 72 serve as input and output ports of the transformer 70.
One end of the first inductor 71 is connected to the source of the first transistor 51, one end of the second inductor 72 is connected to one end of the capacitor 31, and the other end of the capacitor 31 is connected to the gate of the second transistor 52. The signal input port 11 of the circuit is connected to the source of the first transistor 51 and to the port of the first inductor 71 in the transformer 70.
The drain of the first transistor 51 is connected to the first power supply bias 41 and serves as the signal non-inverting output 12 of the circuit; the drain of the second transistor 52 is connected to the second power supply bias 42 and serves as the signal inverting output 13 of the circuit; the signal normal phase output end 12 and the signal reverse phase output end 13 jointly form a differential output port of the circuit structure; the first power bias 41 and the second power bias 42 are used for isolating high-frequency signals and providing direct current paths, and the first power bias 41 and the second power bias 42 are composed of resistors, inductors or parallel connection of the resistors and the inductors; the other ends of the first power bias 41 and the second power bias 42 are connected to the power supply 16.
The first transistor 51 and the second transistor 52 are Field Effect Transistors (FETs) including a drain, a source, and a gate. The drains of the first transistor 51 and the second transistor 52 are respectively connected to a third transistor 53 having a common gate structure and a fourth transistor 54 having a common gate structure, the signal normal phase output terminal 12 of the differential output port is connected to the drain of the third transistor 53, and the signal reverse phase output terminal 13 of the differential output port is connected to the drain of the fourth transistor 54 having a common gate structure. The first gate bias port 14 of the first transistor 51 is connected to a bias circuit to obtain a bias voltage Vg1, and the second gate bias port 15 of the second transistor 52 is connected to the bias circuit to obtain a bias voltage Vg2. The third gate bias port 18 of the third transistor 53 is connected to the bias circuit to obtain the bias voltage Vg3, and the fourth gate bias port 19 of the fourth transistor 54 is connected to the bias circuit to obtain the bias voltage Vg4.
Claims (8)
1. A noise canceling low noise amplifier, characterized by: the high-voltage power supply comprises a first transistor (51) and a second transistor (52), wherein the source electrode of the first transistor (51) in a common-gate structure working state is connected with the grid electrode of the second transistor (52) in a common-source structure working state after passing through a transformer (70) and a capacitor (31) in sequence, the transformer (70) couples an input signal with the second transistor (52) and amplifies the voltage, and the capacitor (31) plays a role in isolating direct current and coupling signals; thereby realizing bias of the common source stage transistor;
the transformer (70) comprises a first inductor (71) and a second inductor (72) which are overlapped, and a signal input port (11) of the circuit is connected with a source stage of the first transistor (51) and a port of the first inductor (71) in the transformer (70);
the drain of the first transistor (51) is connected to the first power supply bias (41) and serves as a signal non-inverting output (12) of the circuit; the drain of the second transistor (52) is connected to the second power supply bias (42) and serves as a signal inverting output (13) of the circuit; the signal non-inverting output terminal (12) and the signal inverting output terminal (13) jointly form a differential output port of the circuit structure.
2. A noise canceling low noise amplifier according to claim 1, characterized in that: the transformer (70) comprises a first inductor (71) and a second inductor (72) which are overlapped, one end of the first inductor (71) and one end of the second inductor (72) are connected to the ground (17), and the other end of the first inductor (71) and the other end of the second inductor (72) serve as input and output ports of the transformer (70).
3. A noise canceling low noise amplifier according to claim 2, characterized in that: one end of the first inductor (71) is connected to the source of the first transistor (51), one end of the second inductor (72) is connected to one end of the capacitor (31), and the other end of the capacitor (31) is connected to the gate of the second transistor (52).
4. A noise canceling low noise amplifier according to claim 1, characterized in that: the first power supply bias (41) and the second power supply bias (42) are used for isolating high-frequency signals and providing a direct current path at the same time, and the first power supply bias (41) and the second power supply bias (42) are composed of resistors, inductors or parallel connection of the resistors and the inductors; the other ends of the first power supply bias (41) and the second power supply bias (42) are connected to the power supply (16).
5. A noise canceling low noise amplifier according to claim 1, characterized in that: the first transistor (51) and the second transistor (52) are field effect transistors comprising a transistor having a drain, a source and a gate.
6. A noise canceling low noise amplifier according to claim 1, characterized in that: the drains of the first transistor (51) and the second transistor (52) are respectively connected with a third transistor (53) with a common gate structure and a fourth transistor (54) with a common gate structure, a signal normal phase output end (12) of the differential output port is connected with the drain of the third transistor (53), and a signal reverse phase output end (13) of the differential output port is connected with the drain of the fourth transistor (54) with the common gate structure.
7. A noise canceling low noise amplifier according to claim 1, characterized in that: a first gate bias port (14) of the first transistor (51) is connected to the bias circuit to obtain a bias voltage Vg1, and a second gate bias port (15) of the second transistor (52) is connected to the bias circuit to obtain a bias voltage Vg2.
8. A noise canceling low noise amplifier according to claim 6, wherein: a third gate bias port (18) of the third transistor (53) is connected to the bias circuit to obtain a bias voltage Vg3, and a fourth gate bias port (19) of the fourth transistor (54) is connected to the bias circuit to obtain a bias voltage Vg4.
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| CN112383280B (en) * | 2020-11-27 | 2023-07-04 | 成都信息工程大学 | Ku-band low-power-consumption CMOS low-noise amplifier circuit |
| CN112968674B (en) * | 2021-01-28 | 2023-04-07 | 电子科技大学 | Double-path noise cancellation circuit of low-noise amplifier |
| CN117728776B (en) * | 2024-02-07 | 2024-04-30 | 深圳飞骧科技股份有限公司 | Differential low noise amplifier |
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| TWM307924U (en) * | 2006-06-14 | 2007-03-11 | Mao-Liang Liu | Amplifier with zero voltage gain |
| CN102651633A (en) * | 2012-05-15 | 2012-08-29 | 江苏科技大学 | Noise current feed-forward type noise cancellation circuit |
| WO2017166109A1 (en) * | 2016-03-30 | 2017-10-05 | 武汉芯泰科技有限公司 | Low noise amplifier |
| CN212695961U (en) * | 2020-08-19 | 2021-03-12 | 成都瑞迪威科技有限公司 | Noise-cancelling low-noise amplifier |
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| US8264276B2 (en) * | 2010-12-13 | 2012-09-11 | Texas Instruments Incorporated | Low-noise amplifier |
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|---|---|---|---|---|
| TWM307924U (en) * | 2006-06-14 | 2007-03-11 | Mao-Liang Liu | Amplifier with zero voltage gain |
| CN102651633A (en) * | 2012-05-15 | 2012-08-29 | 江苏科技大学 | Noise current feed-forward type noise cancellation circuit |
| WO2017166109A1 (en) * | 2016-03-30 | 2017-10-05 | 武汉芯泰科技有限公司 | Low noise amplifier |
| CN212695961U (en) * | 2020-08-19 | 2021-03-12 | 成都瑞迪威科技有限公司 | Noise-cancelling low-noise amplifier |
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