CN116632040B - Shielded gate trench field effect transistor structure and preparation method thereof - Google Patents

Shielded gate trench field effect transistor structure and preparation method thereof Download PDF

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CN116632040B
CN116632040B CN202310910193.3A CN202310910193A CN116632040B CN 116632040 B CN116632040 B CN 116632040B CN 202310910193 A CN202310910193 A CN 202310910193A CN 116632040 B CN116632040 B CN 116632040B
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schottky
dielectric layer
region
interlayer dielectric
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CN116632040A (en
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冯新
李敦然
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Suzhou Huatai Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
    • H01L29/782—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

The application discloses a shielded gate trench field effect transistor structure and a preparation method thereof. The structure comprises a top metal layer, an interlayer dielectric layer, an epitaxial layer and a substrate which are stacked along a first direction, wherein the top metal layer, the interlayer dielectric layer, the epitaxial layer and the substrate are divided into a cellular region and a Schottky region; the schottky region comprises a schottky metal region with a multi-layer step structure, and a first end and a second end of the schottky metal region are respectively in electric contact with the top metal layer and the isolation dielectric layer. According to the application, the electric field is leveled layer by layer through the multilayer step laminated structure, part of the electric field preferentially points to the zero potential position formed by the Schottky metal region, and a certain distance is kept between the second end and the epitaxial layer in the structure, so that the number of electric field lines pointing to the second end can be regulated and controlled through the structure, namely, the electric field intensity distribution is regulated, the electric field is gradually regulated to be close to the shape of a rectangular electric field, the electric field concentration phenomenon is improved, and the problem of serious electric leakage of the Schottky diode under the reverse blocking condition is solved.

Description

Shielded gate trench field effect transistor structure and preparation method thereof
Technical Field
The application relates to the technical field of semiconductor devices, in particular to a shielded gate trench field effect transistor structure and a preparation method thereof.
Background
In practical applications, the power loss of a synchronous rectifier MOSFET (Metal Oxide Semiconductor Field Effect Transistor-MOSFET) is mainly composed of conduction loss, switching loss, and body diode conduction loss. For example, in a DC-DC (direct current-direct current) conversion circuit, among the power losses of the low-side power switch, the on-loss of the body diode still affects the overall loss of the MOSFET. With the increasing demands for high frequencies and high currents in power switching applications, the need to reduce power losses has received increasing attention.
In order to solve the above problem, a prior art integrates a schottky diode with an SGT (Shielded Gate Transistor-shielded gate trench) structure, and the device structure is shown in fig. 1, and the implementation manner is as follows:
as shown in fig. 1, step 1, a partially shielded gate trench field effect transistor structure is completed using existing processes, including forming a trench 2, a shield electrode isolation dielectric layer 4, a shield electrode 3, an isolation dielectric layer 6 (2000-3000 angstroms) between the shield electrode 3 and the gate, a gate oxide film 12, and growing and etching gate polysilicon 5 to the surface of a substrate 1.
And 2, defining a Schottky region by using photoresist and a mask, and completely removing the grid polysilicon 5 in the Schottky region trench 2 by using a dry etching method, wherein an isolation medium layer 6 between the shielding electrode 3 and the grid is still required to be reserved.
Step 3, using a mask and a photoresist, forming a body implantation region 10 and a source implantation region 11 in a region other than the schottky region by using an ion implantation method.
And 4, forming 5300 angstrom boron phosphorus silicate glass serving as an interlayer dielectric layer 7 by using a chemical vapor deposition method.
And 5, defining a source electrode contact hole (or a contact groove) by using a mask plate and photoresist and a dry etching method.
And 6, etching the interlayer dielectric layer 7 and the gate oxide film 12 above the substrate 1 in the schottky region and in the groove 2 by using a mask and photoresist to expose the substrate 1 on the surface and the substrate 1 on the side wall of the groove 2. The trench 2 of the schottky region needs to be etched down to a certain depth, but at the same time, part of the interlayer dielectric layer 7 and the isolation dielectric layer 6 (the total thickness of both is 2000-3000 angstroms) must be reserved for the isolation of the shielding electrode 3 from the metal barrier layer 13.
In step 7, a titanium and titanium nitride composite film is grown by using a metal sputtering method to be used as the metal barrier layer 13.
In step 8, tungsten is grown on the metal barrier layer 13 to fill the contact hole (or contact groove) and the pit etched before in the trench 2 of the schottky region.
And 9, etching the whole surface of the substrate 1, removing tungsten on the surface of the substrate 1, and forming a tungsten plug 8 in the contact hole (or the contact groove).
Step 10, forming a metal layer 9.
However, the inventor finds that the problem of serious leakage of the schottky diode still exists in the integrated device structure under the reverse blocking condition, which greatly influences the practical application effect of the device structure.
Disclosure of Invention
Aiming at the defects of the prior art, the application aims to provide a shielded gate trench field effect transistor structure and a preparation method thereof.
In order to achieve the purpose of the application, the technical scheme adopted by the application comprises the following steps:
in a first aspect, the present application provides a shielded gate trench field effect transistor structure comprising: the semiconductor device comprises a top metal layer, an interlayer dielectric layer, an epitaxial layer, a substrate, a cell region and a Schottky region, wherein the top metal layer, the interlayer dielectric layer, the epitaxial layer and the substrate are stacked along a first direction, and the cell region and the Schottky region are distributed along a second direction, wherein the second direction is intersected with the first direction;
the Schottky region comprises a Schottky metal region, an isolation medium layer and a shielding gate which are sequentially arranged along a first direction, a first end, far away from the shielding gate, of the Schottky metal region is in electrical contact with the top metal layer, and a second end, far away from the first end, of the Schottky metal region is in ohmic contact with the isolation medium layer;
the Schottky metal region is provided with a multi-layer step structure arranged along a first direction, wherein the width of a plurality of steps is in a decreasing trend along the first direction, the width of each step is the dimension of the step along a second direction, and at least one layer of side wall of the step is in contact with the epitaxial layer.
Further, the schottky metal region includes first to nth steps stacked in sequence along the first direction, and widths of the first to nth steps decrease in sequence, wherein N is a natural number greater than 1.
Further, the first step is disposed in the interlayer dielectric layer or the top metal layer and has a first end face and a second end face opposite to each other, the first end face is in electrical contact with the top metal layer, the middle area of the second end face is connected with the second step, and the surrounding area forms ohmic contact with the epitaxial layer. Specifically, in the schottky region, as shown in the following example, the interlayer dielectric layer covers the schottky region, and the first step is inlaid in the interlayer dielectric layer of the schottky region; as in the above-described embodiments of the background art, there may be no interlayer dielectric layer around at least the first step of the schottky region, but the top metal layer extends to replace the interlayer dielectric layer, and both of the above-described possible embodiments do not significantly affect the electric field leveling effect of the multi-step.
Further, the nth step has opposite fifth and sixth end faces; when n=2, the fifth end face meets the middle region of the second end face; when N is more than 2, the M step is provided with a third end face and a fourth end face which are opposite, the third end face is connected with the second end face, and the middle area of the fourth end face is connected with the fifth end face, wherein M is a natural number, and M is more than 1 and less than N; and the sixth end surface is connected with the isolation medium layer or the shielding grid.
Further, the semiconductor device further comprises a side isolation layer, wherein the side isolation layer is at least arranged around the Nth step and is used for separating the Nth step from the epitaxial layer, one end of the side isolation layer in the first direction is connected with the surrounding area of the fourth end face, and the other end of the side isolation layer is connected with the isolation medium layer.
Further, the sixth end face is embedded in the isolation dielectric layer, and the second end and the shielding grid are at least separated by the isolation dielectric layer;
further, the material of the side isolation layer is the same as that of the interlayer dielectric layer.
Further, a first groove is formed in the epitaxial layer; the second step, the N step, the side isolation layer, the isolation medium layer and the shielding grid are all arranged in the first groove.
Further, the schottky metal region comprises a schottky contact metal region and a schottky barrier metal layer, and the schottky barrier metal layer is arranged around the schottky contact metal region and forms a core-sheath structure; a localized region of the schottky contact metal region at the first end is exposed from the schottky barrier metal layer and is in electrical contact with the top metal layer.
Further, the cell region is provided with a plurality of cell regions around the schottky region;
further, at least a shielding dielectric layer separates the shielding gate and the epitaxial layer.
The application also provides a preparation method of the shield gate trench field effect transistor structure, which comprises the following steps:
forming an epitaxial layer on the surface of a substrate, and forming a plurality of first grooves and second grooves in the epitaxial layer, wherein the first grooves correspond to Schottky areas, and the second grooves correspond to cellular areas;
forming a shielding gate and an isolation medium layer in sequence along a first direction in the first groove and the second groove;
forming an interlayer dielectric layer on the epitaxial layer;
constructing a multi-step hole structure at the upper part of the first groove and in a corresponding area of the interlayer dielectric layer;
filling the multi-step hole structure to form a Schottky metal region, wherein the Schottky metal region forms a multi-layer step laminated structure which is gradually narrowed along a first direction;
and forming a top metal layer on the interlayer dielectric layer.
Further, the method specifically comprises the following steps:
forming an interlayer dielectric layer, filling the interlayer dielectric layer into the upper part of the first groove, and contacting with the isolation dielectric layer;
etching the interlayer dielectric layer to the epitaxial layer to form a first contact hole, and continuing etching the interlayer dielectric layer to the upper part of the first groove to form a second contact hole;
and optionally continuing to etch the interlayer dielectric layer to an Mth contact hole, continuing to etch the interlayer dielectric layer and extending and etching the interlayer dielectric layer into the isolation dielectric layer to form an Nth contact hole, wherein the side wall of the Nth contact hole is formed by the interlayer dielectric layer and the isolation dielectric layer together, the end face is embedded into the isolation dielectric layer or exposes the shielding gate, the widths of the first contact hole to the Nth contact hole are sequentially decreased, at least the second contact hole exposes the side wall of the first groove, M is less than N, and M and N are natural numbers greater than 1;
depositing a Schottky barrier metal layer on the end face of the first contact hole and the side walls from the first contact hole to the N contact hole;
filling and forming a Schottky contact metal region in an opening space formed by surrounding the Schottky barrier metal layer;
and forming a top metal layer at least on the surface of the Schottky barrier metal layer.
Based on the technical scheme, compared with the prior art, the application has the beneficial effects that:
the shielding gate trench field effect transistor structure provided by the application levels the electric field layer by layer through the Schottky metal region of the multilayer step laminated structure, part of the electric field is preferentially directed to the zero potential position formed at the second end of the Schottky metal region, and a certain distance is kept between the second end and the epitaxial layer in the device structure.
The above description is only an overview of the technical solutions of the present application, and in order to enable those skilled in the art to more clearly understand the technical means of the present application, the present application may be implemented according to the content of the specification, and the following description is given of the preferred embodiments of the present application with reference to the detailed drawings.
Drawings
FIG. 1 is a schematic diagram of a prior art SGT device architecture provided in the background of the present application;
FIG. 2 is a graph of the electric field distribution of a prior art SGT device structure provided by the background of the present application;
FIG. 3 is a schematic diagram of the electric field concentration location of a prior art SGT device structure provided by the background of the present application;
FIG. 4 is a schematic diagram of the overall device architecture of an SGT device architecture provided by an exemplary embodiment of the present application;
FIG. 5 is a schematic diagram of a portion of an SGT device architecture according to an exemplary embodiment of the present application;
FIG. 6 is a graph comparing the electric field distribution curves of SGT device structures provided by an exemplary embodiment of the present application with those of prior art device structures;
FIG. 7a is a schematic illustration of a portion of a process for fabricating an SGT device structure according to an exemplary embodiment of the present application;
FIG. 7b is a schematic illustration of a portion of a process for fabricating an SGT device structure according to an exemplary embodiment of the present application;
FIG. 7c is a schematic illustration of a portion of a process for fabricating an SGT device structure according to an exemplary embodiment of the present application;
FIG. 7d is a schematic illustration of a portion of a process for fabricating an SGT device structure according to an exemplary embodiment of the present application;
FIG. 7e is a schematic illustration of a portion of a process for fabricating an SGT device structure according to an exemplary embodiment of the present application;
FIG. 7f is a schematic illustration of a portion of a process for fabricating an SGT device structure according to an exemplary embodiment of the present application.
Reference numerals illustrate:
10a/10b, a cell region; 20. a Schottky region;
01. a substrate; 02. an epitaxial layer; 03. an interlayer dielectric layer; 04. a top metal layer;
101. a source contact metal; 102. a source contact region; 103. a body region; 104. a gate oxide layer; 105. gate polysilicon; 106. a second isolation dielectric layer; 107. a second shielding gate; 108. a second shielding dielectric layer;
201. a schottky contact metal region; 202. a schottky barrier metal layer; 203. a first isolation dielectric layer; 204. a 0 potential field plate; 205. a first shielding grid; 206. a first shielding dielectric layer; 207. a schottky metal region; 208. a side isolation layer;
207a, a first step; 207b, a second step; 207c, third step.
Detailed Description
The present inventors have found that in the device structure provided in the prior art, the maximum electric field of the schottky diode is generally located at the interface between the schottky contact metal and the semiconductor, and the integrated schottky structure is a vertical structure, so that the electric field is concentrated at two corners of the schottky contact metal closest to the high potential, and the electric field distribution is shown in fig. 2.
Fig. 3 shows an illustration of the location of the electric field concentration of the above device structure, where avalanche breakdown occurs at the strongest electric field (grey circles), the shield grid does not perform a good electric field balancing function (ReSurF); the avalanche breakdown voltage of the Schottky diode in the region is lower than that of the intrinsic region, and under the condition of reverse blocking, the Schottky diode has serious electric leakage.
In view of the shortcomings in the prior art, the inventor of the present application has long studied and practiced in a large number of ways to propose the technical scheme of the present application. The technical scheme, the implementation process, the principle and the like are further explained as follows.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, however, the present application may be practiced otherwise than as described herein, and therefore the scope of the present application is not limited to the specific embodiments disclosed below.
Moreover, relational terms such as "first" and "second", and the like, may be used solely to distinguish one from another component or method step having the same name, without necessarily requiring or implying any actual such relationship or order between such components or method steps.
And it should be noted that, for example, as shown in fig. 4, in the embodiment of the present application, structures or units having the same functions and roles exist in the cell regions 10a and 10b and the schottky region 20, for example, shielding gates exist, and corresponding dielectric layers for isolation exist on the shielding gates, so that for convenience of distinction and description, corresponding units in the schottky region 20 are denoted by a "first" prefix, and corresponding units in the cell regions 10a and 10b are denoted by a "second" prefix. However, the terms "first" and "second" do not mean that the two units are different in function, material, and size, and in practical application, they may be identical or have a certain difference (for example, in size and material), and may each implement a corresponding function.
The embodiment of the application provides a shielded gate trench field effect transistor structure, which comprises a top metal layer 04, an interlayer dielectric layer 03, an epitaxial layer 02 and a substrate 01 which are stacked along a first direction, and is divided into a cell region 10a and a cell region 10b and a Schottky region 20 along a second direction. The first direction and the second direction are preferably perpendicular, which is a common way of designing a device, however, in some cases, for example, when the device trench is arranged obliquely, it is possible that the first direction and the second direction may have a certain non-perpendicular angle, which does not affect the implementation of the functions and effects in the present application, and it is within the scope of protection of the present application.
While, with respect to cell regions 10a and 10b, specifically, for example, cell regions 10a and 10b may form an SGT device structure, it is not limited thereto.
The schottky region 20 includes a schottky metal region 207, a first isolation dielectric layer 203, and a first shielding gate 205 sequentially arranged along the first direction, a first end of the schottky metal region 207 away from the first shielding gate 205 is in electrical contact with the top metal layer 04, a second end away from the first end is in ohmic contact with the first isolation dielectric layer 203, and the second end and the first shielding gate 205 are separated by at least the first isolation dielectric layer 203.
The schottky metal region 207 forms a multi-layered step stack structure that tapers in the first direction, and at least one sidewall of the step is in contact with the epitaxial layer 02.
Specifically, the technical solution provided by the present application may be a three-step method as shown in the following examples, or may be a more number of steps, and no matter what number of steps is adopted, the sidewall of one of the steps needs to be ensured to be in contact with the epitaxial layer 02.
The main inventive concept and the structural improvement point of the present application are all the schottky region 20, but the specific device structures of the cell regions 10a and 10b are not the focus of the present application, and the structures of the cell regions 10a and 10b may be the same as the various SGT device structures in the prior art, or may be adaptively changed, so that the same device functions can be generated, for example, those skilled in the art may use other device structures to realize the same functions of the SGT device structures, which is also considered to be within the scope of the present application. Specifically, the main function of the cellular regions 10a and 10b is to realize the field effect electrical characteristic, while the main function of the schottky region 20 matched with the cellular regions is to optimize the dead zone loss and the reverse recovery characteristic by using the low conduction voltage drop of the schottky junction, so as to improve the efficiency, and the characteristics of the materials, the dimensions, the preparation process and the like of each region and the specific structural unit are also adaptively adjustable to realize the same functions as the existing devices, and are not limited to the partial range of the specific examples of the embodiment of the present application.
As some specific application examples, the schematic structural diagrams of the above-mentioned shielded gate trench field effect transistor structure are shown in fig. 4 and 5, and include the following structures:
the lateral area division can be divided into a cell area and a schottky area 20, wherein the cell area exists on two sides of the schottky area 20 and is respectively 10a and 10b, and the cell area comprises a top metal layer 04, an interlayer dielectric layer 03, a source contact metal 101, a source contact area 102 with a first doping type, a body area 103 with a second doping type, a gate oxide layer 104, a gate polysilicon 105, a second isolation dielectric layer 106 between a second shielding gate 107 and a gate, a second isolation dielectric layer 106 between the second shielding gate 107 and an epitaxial layer 02, an epitaxial layer 02 and a substrate 01 from top to bottom; the source contact region 102 penetrates through the interlayer dielectric layer 03, the source contact region 102, the body region 103 and penetrates into the body region 103.
The schottky region comprises a top metal layer 04, an interlayer dielectric layer 03, a schottky metal region 207, a first isolation dielectric layer 203 between the schottky metal region 207 and the first shielding gate 205, and a first shielding dielectric layer 206 between the first shielding gate 205 and the epitaxial layer 02 from top to bottom, wherein the schottky metal region 207 is divided into a schottky contact metal region 201 and a schottky barrier metal layer 202 wrapped outside; the schottky contact areas sequentially form a plurality of steps with different widths and optionally different heights in the interlayer dielectric layer 03, the epitaxial layer 02 and the first isolation dielectric layer 203, and the widths gradually decrease from top to bottom to form a multi-layer step laminated structure.
In a specific embodiment, taking the value of N as 3 as an example, the schottky metal region 207 includes a first step 207a, a second step 207b and a third step 207c stacked in sequence from top to bottom (i.e., the first direction) in fig. 5, where the width of the first step 207a is greater than the second step 207b, and the width of the second step 207b is greater than the third step 207c. Specifically, the shapes of the first step 207a, the second step 207b, and the third step 207c may be selected from any one of a cylinder, a polygonal column, and a column having an irregular cross section, respectively, and preferably a cylinder or a polygonal column for convenience of preparation. The width of the first step 207a may be, for example, 0.4 μm or more, and the height is preferably equal to the height of the interlayer dielectric layer 03; the width of the second step 207b may be, for example, 0.3 to 0.4 μm, and the height thereof is preferably 0.2 to 0.3 μm, and the width of the third step 207c may be, for example, 0.1 to 0.2 μm, and the height thereof is preferably 0.4 to 2 μm, but is not limited thereto, and specific structural dimensions may be different from the ranges exemplified herein, and corresponding functions may be achieved.
The first step 207a is disposed in the interlayer dielectric layer 03, and has a first end face and a second end face opposite to each other, the first end face is in electrical contact with the top metal layer 04, a middle region of the second end face is in contact with the second step 207b, and a peripheral region is in ohmic contact with the epitaxial layer 02. The second step 207b and the third step 207c are both disposed in the epitaxial layer 02, the second step 207b has a third end face and a fourth end face that are opposite, the third step 207c has a fifth end face and a sixth end face that are opposite, the third end face is connected to the first step 207a, a middle area of the fourth end face is connected to the fifth end face, and the sixth end face is connected to the first isolation medium layer 203. A side surface of the third step 207c is surrounded and coated with a side isolation layer 208, one end of the side isolation layer 208 is connected with a surrounding area of the fourth end surface, the other end of the side isolation layer 208 is connected with the first isolation medium layer 203, and is used for separating the third step 207c from the epitaxial layer 02, and the sixth end surface is embedded in the first isolation medium layer 203; the material of the side isolation layer 208 is the same as that of the interlayer dielectric layer 03.
The second step 207b, the third step 207c, the side isolation layer 208, the first isolation dielectric layer 203, and the first shield gate 205 are disposed in the first trench formed in the schottky region 20.
Of course, the connection may be a direct contact or an indirect contact, for example, one or more steps may be further inserted between the first step 207a and the second step 207b, or one or more steps may be further inserted between the second step 207b and the third step 207c, so long as the above-summarized structural features are satisfied. This means that the value of N is not limited to 3, but other numbers such as 4 or 5 may be used, and the maximum value is generally not more than 7; the sequence names of the second step 207b and the third step 207c may also be changed adaptively when steps are inserted, for example, the original "second" should be called "third" and the original "third" should be called "fifth" after each step is inserted.
The reason for the above arrangement according to the embodiment of the present application should be that: the lower end surface edge of the first step 207a forms a first edge, the second step 207b has a second edge, the third step 207c has a third edge, and the thin layer of the first isolation medium layer 203 between the lower end surface and the shielding gate 205 forms a 0 potential field plate 204, in the electric field, the first edge, the second edge and the third edge are similar to the effect of "tip discharge", and can attract electric field lines to twist towards the edges, wherein the first edge guides part of the electric field lines to the cross section of the interlayer medium layer 03 and the epitaxial layer 02, the second edge guides part of the electric field lines to the side wall of the upper half part of the first trench, and the other part of the electric field is preferentially directed to the lowest 0 potential field plate 204, especially the first edge, but due to the physical isolation of the side isolation layer 208, the edge of the 0 potential field plate 204 is at a certain distance from the epitaxial layer 02, and the distance can be understood as the thickness of the side isolation layer 208, so that the number of electric field lines at the point can be controlled, i.e. the electric field strength can be adjusted, and the electric field is gradually adjusted to be closest to the optimized distribution of the rectangular electric field.
Of course, in some embodiments, the 0 potential field plate 204 may not exist, that is, the third step 207c is directly contacted with the shielding gate 205, and the 0 potential field plate 204 is no longer spaced, at this time, the end of the third step 207c replaces the position of the 0 potential field plate 204, and the edge of the end of the third step 207c is still a certain distance from the epitaxial layer 02, so that the same electric field adjustment effect can be achieved.
While for a specific distance setting, a highly preferred side spacer layer 208 thickness is 0.05-1 μm.
Corresponding to the device structure, the embodiment of the application also provides a preparation method of the device structure, which comprises the following steps:
an epitaxial layer 02 is formed on the surface of the substrate 01, and a plurality of first trenches corresponding to the schottky regions 20 and second trenches corresponding to the cell regions 10a and 10b are formed in the epitaxial layer 02.
A first shielding gate 205, a second shielding gate 107, a first isolation dielectric layer 203, and a second isolation dielectric layer 106 are sequentially formed at the lower parts of the first trench and the second trench.
An interlayer dielectric layer 03 is formed on the epitaxial layer 02.
And constructing a multi-step hole structure at the upper part of the first groove and the corresponding region of the interlayer dielectric layer 03.
The multi-step hole structure is filled with a schottky metal region 207, and the schottky metal region 207 forms a multi-step laminated structure which gradually narrows along a first direction.
A top metal layer 04 is formed on the interlayer dielectric layer 03.
In some embodiments, the method of making may further comprise: and forming SGT device structures in the cell regions 10a and 10b.
The preparation method provided by the application focuses on how to construct the schottky region 20 with the multilayer shape, and particularly how to form the SGT device structure in the cellular regions 10a and 10b, and the timing and steps of forming the SGT device structure are not limited, so that a device which meets the requirements of the structure can be finally obtained. Of course, the structure of the cell regions 10a and 10b that perform the same function is not limited to the SGT device structure, and those skilled in the art may adapt the fabrication process if they replace the SGT device structure with another device structure having the same function.
The preparation can be performed simultaneously with reference to the following examples, which can minimize the complexity of the preparation process, and of course, in extreme cases, it is even possible to prepare the cell regions 10a and 10b and the schottky region 20 separately, and such an embodiment is not impossible to achieve although the process is more complex, and still falls within the scope of the present application.
With particular reference to fig. 7 a-7 f and with continued reference to fig. 4, in a particular example the steps of manufacture thereof are as follows:
1) Epitaxial layer 02 is epitaxially grown on substrate 01 by the existing process, then first and second trenches are etched to form, isolation dielectric layers of shielding electrode (i.e., first and second shielding dielectric layers 206 and 108), shielding electrode (i.e., first and second shielding gates 205 and 107), isolation dielectric layer between shielding electrode and gate (i.e., first and second isolation dielectric layers 203 and 106), gate oxide layer 104 is grown, and gate polysilicon 105 is etched back to the surface of epitaxial layer 02 on substrate 01 to be planarized.
2) The gate polysilicon 105 in the first trench of the schottky region 20 is removed.
3) Body region 103 and source contact region 102 are formed and source contact metal 101 is established.
4) The interlayer dielectric layer 03 is usually an oxide layer, and the interlayer dielectric layer 03 not only covers the surface of the epitaxial layer 02 but also fills the first trench.
5) The schottky region 20 is defined, the interlayer dielectric layer 03 and the gate oxide film are etched, the surface of the epitaxial layer 02 and the first trench sidewall substrate 01 are exposed, and a first isolation dielectric layer 203 with a certain thickness is reserved on the polysilicon of the first shielding gate 205.
6) Defining a source electrode contact hole; (specifically, an oxide layer exists between the schottky region 20 contact hole width is smaller than the trench width, that is, the schottky region 20 source contact hole and the silicon substrate 01, that is, the interlayer dielectric layer 03 filled and grown in the first trench is etched, the interlayer dielectric layer 03 is etched to the epitaxial layer 02 to form a first contact hole, the interlayer dielectric layer 03 is continuously etched to the upper portion of the first trench to form a second contact hole, the second contact hole comprises the side wall of the first trench, the interlayer dielectric layer 03 is continuously etched and extends and etches into the first isolation dielectric layer 203 to form a third contact hole, the side wall of the third contact hole is formed by the interlayer dielectric layer 03 and the first isolation dielectric layer 203 together, the end face of the third contact hole is embedded in the first isolation dielectric layer 203, the width of the first contact hole is larger than that of the second contact hole, the width of the second contact hole is larger than that of the third contact hole, the second contact hole is etched to the upper portion of the interlayer dielectric layer 03 is filled first, and then the remaining part of the interlayer dielectric layer 03 is etched to surround the third isolation layer 208 c side of the third isolation layer 207.
7) The schottky region 20 is defined and a schottky barrier metal layer 202 is deposited to cover the sidewalls of the contact hole.
8) The space surrounded by the schottky barrier metal layer 202 is filled with metal tungsten, which is then used as the schottky contact metal region 201.
9) And etching the tungsten metal back to the surface of the interlayer dielectric layer 03 to make the surface flat.
10A top metal layer 04 is formed by blanket deposition on the surface.
In the above preparation process, there may be a first isolation dielectric layer 203 with different thickness before the schottky metal region 207 and the first shield gate 205 according to the actual etching depth.
It should be noted that the device structure provided by the embodiment of the present application is not limited to the above-mentioned preparation method, and any device structure with the same structure and functional characteristics obtained by adopting any preparation method different from the above-mentioned preparation method still falls within the protection scope of the present application.
The technical scheme of the application is further described in detail below through a plurality of embodiments and with reference to the accompanying drawings. However, the examples are chosen to illustrate the application only and are not intended to limit the scope of the application.
Example 1
The embodiment illustrates a preparation process of a shielded gate trench field effect transistor structure, which includes the following steps:
1) The epitaxial layer 02 is epitaxially grown on the substrate 01 by the prior art, silicon with the thickness of 2um is etched to form a first groove and a second groove with the groove depth of 1um and the width of 0.4um, silicon dioxide with the thickness of 0.1um for forming a shielding electrode in the groove is deposited to be used as an isolation medium layer, silicon dioxide with the thickness of 0.3um between a 5000A polysilicon shielding electrode, the shielding electrode and a grid is used as a gate oxide layer 104 with the thickness of 400A, 5000A grid polysilicon 105 is grown, and the surface of the epitaxial layer 02 on the substrate 01 is etched back to be flat.
2) The gate polysilicon 105 in the first trench of the schottky region 20 is etched away.
3) With 40KeV,5e13cm -2 The Boron implant forms body region 103 and 20KeV 1e15cm -2 Ar implantation forms the source contact region 102 and establishes the source contact metal 101 with tungsten metal.
4) An interlayer dielectric layer 03 is formed as a 6000 a oxide layer.
5) The schottky region 20 is defined, the interlayer dielectric layer 03 and the gate oxide film are etched, the surface of the epitaxial layer 02 and the first trench sidewall substrate 01 are exposed, a first isolation dielectric layer 203 with the thickness of 2000 a is reserved on the polysilicon of the first shielding gate 205, and a first contact hole with the width of 0.16 μm and the depth of the first contact hole being the same as that of the interlayer dielectric layer 03 is formed.
6) Defining other contact holes of the source electrode; specifically, in the step 5), a first contact hole is formed by etching the interlayer dielectric layer 03 to the epitaxial layer 02, a second contact hole is formed by continuing to etch the interlayer dielectric layer 03 to the upper portion of the first trench, the width of the second contact hole is 0.4um, the second contact hole includes the side wall of the first trench, a third contact hole is formed by continuing to etch the interlayer dielectric layer 03 and extend into the first isolation dielectric layer 203, the width is 0.6 um, the depth is the thickness of the interlayer dielectric layer, the side wall of the third contact hole is formed by the interlayer dielectric layer 03 and the first isolation dielectric layer 203 together, and the end face of the third contact hole is embedded in the first isolation dielectric layer 203.
7) The schottky region 20 is defined and a layer of schottky barrier metal 202 is deposited to a thickness of 300 a covering the sidewalls of the contact hole.
8) The space surrounded by the schottky barrier metal layer 202 is filled with metal tungsten, which is then used as the schottky contact metal region 201.
9) And etching the tungsten metal back to the surface of the interlayer dielectric layer 03 to make the surface flat.
10 And (3) performing surface covering deposition to form a top metal layer 04 aluminum copper with the thickness of 5 mu m.
After the SGT device structure is formed into a device, electric field distribution calculation is performed, and a comparison result between the SGT device structure and the existing device structure is shown in fig. 6, it can be seen that the electric field concentration phenomenon of the schottky contact area can be obviously improved, the avalanche breakdown voltage value of schottky can be improved by more than 50%, the avalanche breakdown withstand voltage value is 30V obtained by specific test, electric leakage under the reverse blocking condition is optimized, and further the operation efficiency of the device is improved.
In contrast, the avalanche breakdown voltage value was 19V using the step-less schottky structure of the prior art.
Comparative example 1
This comparative example shows a shielded gate trench field effect transistor structure which is substantially identical to the device structure of example 1, except that:
the second step 207b extends directly down along the sidewall of the first trench to the bottom end of the original third step 207c, and the third step 207c and the side isolation layer 208 are no longer present.
The voltage-withstanding performance of the device structure provided in this comparative example is substantially at the same level as that of the device structure in the prior art, and a breakdown phenomenon occurs in advance, which indicates that the three-step schottky structure and the arrangement of the side isolation layer 208 in combination with the three-step schottky structure according to the embodiment of the present application are important for improving the avalanche breakdown voltage.
Comparative example 2
This comparative example shows a shielded gate trench field effect transistor structure which is substantially identical to the device structure of example 1, except that:
the first step 207a is eliminated so that the second step 207b extends directly to the top metal layer 04 maintaining the original width dimension.
The device structure provided in this comparative example does not have a significant drop in avalanche breakdown voltage compared to example 1, however, when the device is turned on in the forward direction, the on-voltage drop increases significantly, and eventually the loss of the device increases.
It is clear from this that the structure of the multi-step schottky region 20 in the present application is not only beneficial to improve the avalanche breakdown voltage, but also beneficial to reduce the device loss, and achieves the comprehensive improvement effect.
Based on the above embodiments and comparative examples, it can be clear that, in the SGT device structure provided by the embodiment of the present application, the electric field is leveled layer by the schottky metal region 207 of the multilayer step laminated structure, a part of the electric field preferentially points to the zero potential position formed at the second end of the schottky metal region 207, and a certain distance remains between the second end and the epitaxial layer 02 in the above SGT device structure, so that the number of electric field lines pointing to the second end can be regulated, i.e. the electric field intensity distribution is regulated, the electric field is gradually regulated to be close to the shape of a rectangular electric field, the electric field concentration phenomenon is improved, and the problem of serious electric leakage of the schottky diode under the reverse blocking condition is solved.
It should be understood that the above embodiments are merely for illustrating the technical concept and features of the present application, and are intended to enable those skilled in the art to understand the present application and implement the same according to the present application without limiting the scope of the present application. All equivalent changes or modifications made in accordance with the spirit of the present application should be construed to be included in the scope of the present application.

Claims (10)

1. A shielded gate trench field effect transistor structure comprising: the semiconductor device comprises a top metal layer, an interlayer dielectric layer, an epitaxial layer, a substrate, a cell region and a Schottky region, wherein the top metal layer, the interlayer dielectric layer, the epitaxial layer and the substrate are stacked along a first direction, and the cell region and the Schottky region are distributed along a second direction, wherein the second direction is intersected with the first direction;
the Schottky region comprises a Schottky metal region, an isolation medium layer and a shielding gate which are sequentially arranged along a first direction, a first end, far away from the shielding gate, of the Schottky metal region is in electrical contact with the top metal layer, and a second end, far away from the first end, of the Schottky metal region is in ohmic contact with the isolation medium layer;
the Schottky metal region is provided with a multi-layer step structure arranged along a first direction, the multi-layer step structure comprises a first step, a second step, a third step, a fourth step, a fifth step and a sixth step, wherein the first step to the fifth step are sequentially stacked along the first direction, the widths of the first step to the fifth step are sequentially decreased, N is a natural number larger than 1, the width of each step is the dimension of the step in the second direction, and the side wall of at least one layer of step is in contact with the epitaxial layer;
the shielded gate trench field effect transistor structure further includes a side isolation layer disposed at least around a side of the nth step for separating at least the nth step from the epitaxial layer.
2. The shielded gate trench fet structure of claim 1 wherein the first step is disposed in the interlayer dielectric layer or the top metal layer and has opposing first and second end surfaces, the first end surface being in electrical contact with the top metal layer, a middle region of the second end surface being in contact with the second step, and a surrounding region forming an ohmic contact with the epitaxial layer.
3. The shielded gate trench field effect transistor structure of claim 2 wherein the second step through the nth step are all disposed within the epitaxial layer;
the Nth step is provided with a fifth end face and a sixth end face which are opposite;
when n=2, the fifth end face meets the middle region of the second end face; when N is more than 2, the M step is provided with a third end face and a fourth end face which are opposite, the third end face is connected with the second end face, and the middle area of the fourth end face is connected with the fifth end face, wherein M is a natural number, and M is more than 1 and less than N;
and the sixth end surface is connected with the isolation medium layer or the shielding grid.
4. The shielded gate trench field effect transistor structure of claim 3 wherein one end of the side isolation layer in the first direction is contiguous with a surrounding region of the fourth end face and the other end is contiguous with the isolation dielectric layer.
5. The shielded gate trench fet structure of claim 4 wherein the sixth end face is embedded within the isolation dielectric layer and the second end and the shielded gate are separated by at least the isolation dielectric layer;
and/or the material of the side isolation layer is the same as that of the interlayer dielectric layer.
6. The shielded gate trench field effect transistor structure of claim 4 wherein a first trench is provided in the epitaxial layer;
the second step, the N step, the side isolation layer, the isolation medium layer and the shielding grid are all arranged in the first groove.
7. The shielded gate trench field effect transistor structure of claim 1 wherein the schottky metal region comprises a schottky contact metal region and a schottky barrier metal layer disposed around the schottky contact metal region and forming a core-sheath structure;
a localized region of the schottky contact metal region at the first end is exposed from the schottky barrier metal layer and is in electrical contact with the top metal layer.
8. The shielded gate trench field effect transistor structure of claim 1 wherein the schottky region is disposed between at least some adjacent cell regions;
the cell region is provided with a plurality of cells around the Schottky region;
and/or, at least a shielding dielectric layer separates the shielding grid and the epitaxial layer.
9. The preparation method of the shielded gate trench field effect transistor structure is characterized by comprising the following steps:
forming an epitaxial layer on the surface of a substrate, and forming a plurality of first grooves and second grooves in the epitaxial layer, wherein the first grooves correspond to Schottky areas, and the second grooves correspond to cellular areas;
forming a shielding gate and an isolation medium layer in sequence along a first direction in the first groove and the second groove;
forming an interlayer dielectric layer on the epitaxial layer, wherein the interlayer dielectric layer is filled into the first groove;
constructing a multi-step hole structure on the upper part of the first groove and the corresponding area of the interlayer dielectric layer, and reserving part of the interlayer dielectric layer to be used as a side isolation layer surrounding the multi-step hole structure;
filling the multi-step hole structure to form a Schottky metal region, wherein the Schottky metal region forms a multi-layer step laminated structure which is gradually narrowed along a first direction;
and forming a top metal layer on the interlayer dielectric layer.
10. The preparation method according to claim 9, characterized in that it comprises in particular:
forming an interlayer dielectric layer, filling the interlayer dielectric layer into the upper part of the first groove, and contacting with the isolation dielectric layer;
etching the interlayer dielectric layer to the epitaxial layer to form a first contact hole, and continuing etching the interlayer dielectric layer to the upper part of the first groove to form a second contact hole;
and optionally continuing to etch the interlayer dielectric layer to an Mth contact hole, continuing to etch the interlayer dielectric layer and extending and etching the interlayer dielectric layer into the isolation dielectric layer to form an Nth contact hole, wherein the side wall of the Nth contact hole is formed by the interlayer dielectric layer and the isolation dielectric layer together, the end face is embedded into the isolation dielectric layer or exposes the shielding gate, the widths of the first contact hole to the Nth contact hole are sequentially decreased, at least the second contact hole exposes the side wall of the first groove, M is less than N, and M and N are natural numbers greater than 1;
depositing a Schottky barrier metal layer on the end face of the first contact hole and the side walls from the first contact hole to the N contact hole;
filling and forming a Schottky contact metal region in an opening space formed by surrounding the Schottky barrier metal layer;
and forming a top metal layer at least on the surface of the Schottky barrier metal layer.
CN202310910193.3A 2023-07-24 2023-07-24 Shielded gate trench field effect transistor structure and preparation method thereof Active CN116632040B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104681448A (en) * 2013-11-29 2015-06-03 上海华虹宏力半导体制造有限公司 Structure and manufacturing method for schottky transistor
CN112736138A (en) * 2021-04-01 2021-04-30 江苏长晶科技有限公司 Structure of shielding grid-groove type MOSFET and manufacturing method thereof
CN114141885A (en) * 2021-12-30 2022-03-04 湖北九峰山实验室 Multi-stage groove Schottky diode and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104681448A (en) * 2013-11-29 2015-06-03 上海华虹宏力半导体制造有限公司 Structure and manufacturing method for schottky transistor
CN112736138A (en) * 2021-04-01 2021-04-30 江苏长晶科技有限公司 Structure of shielding grid-groove type MOSFET and manufacturing method thereof
CN114141885A (en) * 2021-12-30 2022-03-04 湖北九峰山实验室 Multi-stage groove Schottky diode and manufacturing method thereof

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