CN111180511A - Manufacturing method of integrated structure of insulated gate bipolar transistor and rectifier - Google Patents
Manufacturing method of integrated structure of insulated gate bipolar transistor and rectifier Download PDFInfo
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- CN111180511A CN111180511A CN202010008157.4A CN202010008157A CN111180511A CN 111180511 A CN111180511 A CN 111180511A CN 202010008157 A CN202010008157 A CN 202010008157A CN 111180511 A CN111180511 A CN 111180511A
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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- H—ELECTRICITY
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
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Abstract
A manufacturing method of an integrated structure of an insulated gate bipolar transistor and a rectifier is provided, a substrate doping area with a first conduction type is formed in a drift epitaxial layer with a second conduction type on any side of each gate insulation layer, the substrate doping area between adjacent gates is divided into two areas, and further the bottom of the substrate doping area and the PN junction area of the drift epitaxial layer are reduced, so that under the condition that an IGBT is maintained to have the same withstand voltage capability, the injection amount of excess minority carriers of the rectifier is reduced through concentration difference of different positions, the fast reverse recovery time of the rectifier formed by the substrate doping area and the drift epitaxial layer is further prolonged, and the design of the rectifier with the fast reverse recovery time is improved. A lightly doped region of the first conductivity type is disposed between the drift epitaxial layer and the contact doped region to avoid conduction caused by the contact of the drift epitaxial layer with high doping concentration in the contact doped region of the first conductivity type with high doping concentration due to the reduction of the area of the body doped region.
Description
Technical Field
The invention relates to the technical field of transistors, in particular to a manufacturing method of an integrated structure of an insulated gate bipolar transistor and a rectifier.
Background
An IGBT is considered to be a composite structure combining a metal-oxide-semiconductor field effect transistor (MOSFET) and a Bipolar Junction Transistor (BJT). Because the IGBT combines the characteristic that MOSET is easy to use gate control and the characteristic that BJT has low on-state voltage drop, the IGBT is widely applied to the application field of high voltage and high power.
Referring to fig. 1, fig. 1 is a schematic cross-sectional view of an IGBT. As shown in fig. 1, in a conventional IGBT 10, an N-type buffer layer 14 is formed on a P-type semiconductor substrate 12, and then an N-type epitaxial layer 16 is formed on the N-type buffer layer 14 as a drain of a parasitic MOSFET in the IGBT 10. Then, two gate structures 18 are formed in the N-type epitaxial layer 16. Each gate structure 18 includes a gate electrode 20 and a gate insulating layer 22 for electrically isolating the gate electrode 20 from the N-type epitaxial layer 16. Next, a P-type body doped region 24 is formed in the N-type epitaxial layer 16 between the gate structures 18, and then two N-type source doped regions 26 are formed in the P-type body doped region 24, respectively contacting the gate insulating layers 22 and serving as the source of the parasitic MOSFET in the IGBT 10. Then, a dielectric layer 28 is formed on the N-type epitaxial layer 16, and the P-type body doped region 24 between the N-type source doped regions 26 is exposed, and a P-type contact doped region 30 is formed in the exposed P-type body doped region 24. An emitter metal layer 32 is then formed overlying the dielectric layer 28, the P-type contact doping region 30 and the N-type source doping region 26. Finally, a collector metal layer 34 is formed under the P-type semiconductor substrate 12.
The conventional IGBT is formed on a substrate by using the aforementioned semiconductor process technology, and then is externally connected with a diode as a rectifier to provide a rectification function, so that the circuit component and the diode component of the IGBT can be packaged in the same package structure. However, the link structure externally connecting the diode to the IGBT requires high cost and complicated packaging method, and the link structure externally connecting the diode occupies a large space, which is not suitable for the trend of high precision of electronic components.
Therefore, in order to improve the precision of the electronic device, in the prior art, an N-type cathode doped region is formed in the P-type semiconductor substrate of the IGBT, and is electrically connected to the N-type epitaxial layer and the collector metal layer, so that the N-type epitaxial layer serves as the cathode of the diode, and the P-type body doped region serves as the anode of the diode, and parasitizes in the IGBT, and is further integrated in the same integrated circuit structure. A PN junction is formed between the parasitic diode formed by the P-type substrate doped region and the N-type epitaxial layer, electron carriers in the N-type epitaxial layer close to the P-type substrate doped region are injected into the P-type substrate doped region, and hole carriers in the P-type substrate doped region close to the N-type epitaxial layer are injected into the N-type epitaxial layer, so that a depletion region is formed between the P-type substrate doped region and the N-type epitaxial layer. However, when the diode is switched from the forward bias to the reverse bias, i.e. the IGBT enters the voltage-withstanding state, the depletion region of the PN junction becomes larger, i.e. the hole carriers injected into the N-type epitaxial layer are drained, i.e. excess minority carriers (process minor Carrier) in the depletion region are eliminated, and a reverse recovery time is required, thereby limiting the switching speed of the IGBT and diode integrated structure. Since the IGBT is a high voltage device with a voltage of 600 volts (V) or more, a very thick N-type epitaxial layer is required as a voltage-withstanding layer, and therefore, how to design a structure for reducing the excess minority carrier injection amount and increasing the switching speed of the integrated structure of the IGBT and the rectifier is the subject of the industrial efforts.
Disclosure of Invention
The present invention provides a method for manufacturing an integrated structure of an insulated gate bipolar transistor and a rectifier, which reduces the injection amount of excess minority carriers of the rectifier by means of concentration differences at different positions while maintaining the same voltage withstanding capability of an IGBT, thereby improving the design of a fast reverse recovery time rectifier.
According to a first aspect, an embodiment provides a method for manufacturing an integrated structure of an insulated gate bipolar transistor and a rectifier, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate has a first conductive type and comprises an upper surface and an opposite lower surface;
forming a cathode doped region in the semiconductor substrate, wherein the cathode doped region has a second conductive type;
forming a drift epitaxial layer on the upper surface of the semiconductor substrate, wherein the drift epitaxial layer has the second conduction type;
forming at least one gate insulating layer and at least one gate in the drift epitaxial layer, wherein the gate insulating layer is arranged between the drift epitaxial layer and the gate;
forming at least one substrate doping area in the drift epitaxial layer, wherein the substrate doping area has the first conduction type, and the substrate doping area has a bottom area designed according to preset parameters aiming at any substrate doping area, so that the area of a PN junction formed by the bottom of the substrate doping area and the drift epitaxial layer is reduced;
forming a source doped region in the body doped region, wherein the source doped region has the second conductivity type and is adjacent to the gate insulating layer;
forming a contact doped region in the substrate doped region and the drift epitaxial layer, wherein the contact doped region has the first conductive type and is adjacent to the source doped region;
forming an emitter metal layer on the contact doped region and the source doped region, so that the emitter metal layer is electrically connected with the source doped region and the contact doped region;
performing a thinning process on the lower surface of the semiconductor substrate to expose the cathode doped region;
and forming a collector metal layer on the lower surface of the semiconductor substrate, wherein the collector metal layer is electrically connected with the cathode doped region and the semiconductor substrate.
In one possible implementation, the forming at least one body doping region includes:
and forming substrate doped regions on two sides of the gate insulating layer, so that the substrate doped regions are adjacent to the gate insulating layer, and one side, far away from the gate insulating layer, of the substrate doped regions is adjacent to the drift epitaxial layer.
In one possible implementation manner, the forming of the body doped region on both sides of the gate insulating layer includes:
performing a photolithography process to form a first patterned photoresist layer on the drift epitaxial layer on one side of the gate insulating layer;
performing a first ion implantation process with the first conductivity type on the drift epitaxial layer on both sides of the gate insulating layer based on the first patterned photoresist layer;
removing the first patterned photoresist layer;
and performing a first drive-in process to form the body doped region in the drift epitaxial layer adjacent to both sides of the gate insulation layer.
In one possible implementation, the horizontal cross-sectional area of the doped region of the substrate is smaller as the depth of the doped region of the substrate is deeper.
In one possible implementation, forming a drift epitaxial layer includes:
forming an epitaxial layer on the upper surface of the semiconductor substrate;
and forming a heavily doped region in the epitaxial layer, wherein the doping concentration of the heavily doped region is greater than that of the epitaxial layer, and the epitaxial layer and the heavily doped region form the drift epitaxial layer.
In one possible implementation manner, the method further includes:
and forming a lightly doped region between the contact doped region and the heavily doped region, wherein the lightly doped region has the first conductivity type, and the doping concentration of the lightly doped region is less than that of the contact doped region.
In one possible implementation manner, the depth of the lightly doped region is smaller than that of the matrix doped region.
In one possible implementation manner, the doping concentration of the heavily doped region is less than that of the source doped region.
In one possible implementation, the forming of the contact doping region includes: a second ion implantation process and a second drive-in process are performed to form the contact doped region.
In one possible implementation, the forming the lightly doped region includes:
a third ion implantation process and a third drive-in process are performed to form the lightly doped region.
According to the manufacturing method of the integrated structure of the insulated gate bipolar transistor and the rectifier in the above embodiment, a body doping region having the first conductivity type is formed in the drift epitaxial layer of the second conductivity type on any side of each gate insulating layer, so that the body doping region between adjacent gates is divided into two regions, and further the bottom of the body doping region and the PN junction area of the drift epitaxial layer are reduced, thereby reducing the injection amount of excess minority carriers of the rectifier by means of concentration differences at different positions under the condition of maintaining the same voltage endurance capability of the IGBT, further improving the fast reverse recovery time of the rectifier formed by the body doping region and the drift epitaxial layer, and realizing the design of the rectifier with the fast reverse recovery time. In addition, in the present embodiment, a lightly doped region of the first conductivity type is further disposed between the drift epitaxial layer and the contact doped region to avoid conduction generated by the contact of the drift epitaxial layer with high doping concentration in the contact doped region of the first conductivity type with high doping concentration due to the reduction of the area of the body doped region.
Drawings
FIG. 1 is a schematic cross-sectional view of a conventional IGBT;
FIG. 2 is a schematic diagram illustrating a method for fabricating an integrated IGBT and rectifier structure according to an embodiment;
FIG. 3 is a schematic view of another embodiment of a method for fabricating an integrated IGBT and rectifier structure;
FIG. 4 is a schematic view of another embodiment of a method for fabricating an integrated IGBT and rectifier structure;
FIG. 5 is a schematic view of another embodiment of a method for fabricating an integrated IGBT and rectifier structure;
FIG. 6 is a schematic view of another embodiment of a method for fabricating an integrated IGBT and rectifier structure;
FIG. 7 is a schematic view of another embodiment of a method for fabricating an integrated IGBT and rectifier structure;
FIG. 8 is a schematic view of another embodiment of a method for fabricating an integrated IGBT and rectifier structure;
fig. 9 is a perspective sectional view of an integrated structure of an igbt and a rectifier according to an embodiment.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).
Example one
Referring to fig. 2, the present embodiment provides a flow chart illustrating a manufacturing method of an integrated structure of an igbt and a rectifier, including steps S10 to S100, which are described in detail below.
Step S10: a semiconductor substrate is provided, the semiconductor substrate has a first conductivity type, and the semiconductor substrate includes an upper surface and an opposite lower surface.
Step S20: and forming a cathode doped region in the semiconductor substrate, wherein the cathode doped region has a second conductivity type.
Step S30: and forming a drift epitaxial layer on the upper surface of the semiconductor substrate, wherein the drift epitaxial layer has the second conduction type.
Step S40: and forming at least one gate insulating layer and at least one gate in the drift epitaxial layer, wherein the gate insulating layer is arranged between the drift epitaxial layer and the gate.
Step S50: and forming at least one substrate doping area in the drift epitaxial layer, wherein the substrate doping area has the first conduction type, and the substrate doping area has a bottom area designed according to preset parameters aiming at any substrate doping area, so that the area of a PN junction formed by the bottom of the substrate doping area and the drift epitaxial layer is reduced.
Step S60: and forming a source doped region in the substrate doped region, wherein the source doped region has the second conductivity type and is adjacent to the gate insulating layer.
Step S70: and forming a contact doped region in the substrate doped region and the drift epitaxial layer, wherein the contact doped region has the first conduction type and is adjacent to the source doped region.
Step S80: and forming an emitter metal layer on the contact doped region and the source doped region, so that the emitter metal layer is electrically connected with the source doped region and the contact doped region.
Step S90: and performing a thinning process on the lower surface of the semiconductor substrate to expose the cathode doped region.
Step S100: and forming a collector metal layer on the lower surface of the semiconductor substrate, wherein the collector metal layer is electrically connected with the cathode doped region and the semiconductor substrate.
The present embodiment provides a method for fabricating an integrated structure of an igbt and a rectifier, so as to fabricate an integrated structure 100 of an igbt and a rectifier, which includes a collector metal layer 150, a semiconductor substrate 102, at least one cathode doped region 108, a drift epitaxial layer 116, at least one gate 122, at least one gate insulating layer 120, at least one body doped region 130, at least one contact doped region 144, at least one source doped region 134, a lightly doped region 146, and an emitter metal layer 148. Wherein the semiconductor substrate 102 has a first conductive type, is disposed on the collector metal layer 150 and electrically connected to the collector metal layer 150, the at least one cathode doped region 108 has a second conductive type, is disposed in the semiconductor substrate 102, the cathode doped region 108 is electrically connected to the collector metal layer 150, the drift epitaxial layer 116 has the second conductive type, is disposed on the semiconductor substrate 102 and electrically connected to the semiconductor substrate 102 and the cathode doped region 108, the at least one gate 122 is disposed in the drift epitaxial layer 116, the at least one gate insulating layer 120 is disposed between the drift epitaxial layer 116 and the gate 122, the at least one body doped region 130 has the first conductive type, is disposed in the drift epitaxial layer 116, and has a bottom area designed according to preset parameters for any body doped region 130, so that the area of the PN junction formed by the bottom of the body doped region 130 and the drift epitaxial layer 116 is reduced, at least one source doped region 134 having the second conductivity type disposed in the body doped region 130 and adjacent to the gate insulating layer 120, at least one contact doped region 144 having the first conductivity type disposed in the body doped region 130 and the drift epitaxial layer 116 and adjacent to the source doped region 134, and an emitter metal layer 148 disposed on the contact doped region 144 and the source doped region 134 and electrically connected to the source doped region 134 and the contact doped region 144.
Referring to fig. 3 to 8, fig. 3 to 8 are schematic diagrams illustrating a manufacturing method of an integrated structure of an insulated gate bipolar transistor IGBT and a fast reverse recovery time (reverse recovery time) rectifier according to the present embodiment. Fig. 8 is a cross-sectional view of the integrated structure of the igbt and the rectifier according to the present embodiment. As shown in fig. 3, a semiconductor substrate 102 having a first conductivity type, such as: the semiconductor substrate 102 is heavily doped P-type, and the semiconductor substrate 102 includes an upper surface 104 and an opposite lower surface 106. Furthermore, the semiconductor substrate 102 has at least one doped cathode region 108 doped therein with a second conductivity type, such as: and an N-type cathode doped region. In addition, the upper surface of the semiconductor substrate 102 of the present embodiment is provided with a buffer layer 110 and an epitaxial layer 112 disposed on the buffer layer 110, and the buffer layer 110 and the epitaxial layer 112 have a second conductivity type, for example: and (4) N type. The first conductivity type of the present embodiment is not limited to P-type, and the second conductivity type is not limited to N-type, but the first conductivity type and the second conductivity type of the present embodiment can be interchanged, for example: the first conductivity type may be N-type and the second conductivity type P-type. The present embodiment is described by taking the first conductive type as P-type and the second conductive type as N-type, but not limited thereto. In addition, the integrated structure of the IGBT and the fast reverse recovery time rectifier of the present embodiment is not limited to include the N-type buffer layer 110, that is, the N-type epitaxial layer 112 can be directly formed on the P-type semiconductor substrate 102, and the IGBT is a non-through IGBT. The present embodiment is described by taking the example that the IGBT includes the N-type buffer layer 110 and is a through-type IGBT, and the first conductivity type is a P-type, and the second conductivity type is an N-type, but the present embodiment is not limited thereto.
The steps of forming the N-type cathode doped region 108, the N-type buffer layer 110 and the N-type epitaxial layer 112 include: a photolithography process is performed to form a patterned photoresist layer (not shown) on the upper surface 104 of the P-type semiconductor substrate 102, and then a first N-type ion implantation process is performed using the patterned photoresist layer as a mask to implant N-type ions into the P-type semiconductor substrate 102. Then, the patterned photoresist layer is removed, and a drive-in process is performed to diffuse the N-type ions in the P-type semiconductor substrate 102 to form an N-type cathode doped region 108, such that the N-type cathode doped region 108 is electrically connected to the cathode of the rectifier. Next, an N-type buffer layer 110 is formed on the P-type semiconductor substrate 102 and the N-type cathode doped region 108. Then, an epitaxial process is performed to form an N-type epitaxial layer 112 on the N-type buffer layer 110. The integrated structure of IGBT and fast reverse recovery time rectifier can adjust the thickness of N-type epitaxial layer 112 according to the desired degree of withstand voltage.
Next, a second N-type ion implantation process and a drive-in process are performed on the N-type epitaxial layer 112 to form a heavily N-doped region 114 in the N-type epitaxial layer 112, wherein the heavily N-doped region 114 and the N-type epitaxial layer 112 not doped by the second N-type ion implantation process form an N-drift epitaxial layer 116, and the heavily N-doped region 114 is located on the N-type epitaxial layer 112 not doped by the second N-type ion implantation process. It is noted that the doping concentration of heavily doped N region 114 decreases as the epitaxial layer 112 approaches, for example, the doping concentration of heavily doped N region 114 adjacent to the epitaxial layer 112 is about 1015cm-3The doping concentration of the N-type doped region 114 gradually increases to about 1016cm with distance from the N-type epitaxial layer 112-3. Moreover, the doping concentration of heavily N-doped region 114 is greater than that of N-epitaxial layer 112, for example, the doping concentration of N-epitaxial layer 112 is approximately 1013To 1014cm-3However, the present embodiment is not limited thereto.
As shown in FIG. 4, a photolithography and etching process is then performed on the N-drift epitaxial layer 116 to form a plurality of trenches 118 in the N-drift epitaxial layer 116, wherein each trench 118 extends into the N-epitaxial layer 112 through the heavily doped N-doped region 114. A gate insulating layer 120 and a gate 122 are formed in each trench 118, wherein the gate insulating layer 120 is disposed between the gate 122 and the N-type drift epitaxial layer 116 for electrically isolating the gate 122 from the heavily doped N-type region 114 and electrically isolating the gate 122 from the N-type epitaxial layer 112. In addition, after the gate insulating layer 120 and the gate electrodes 122 are formed, another insulating layer 124 may be further covered on each gate electrode 122 to form the gate insulating layer 120, so as to prevent the gate electrodes 122 from being damaged in the subsequent processes, but the steps are not limited thereto.
As shown in fig. 5, a first mask (not shown) is used to perform a photolithography process to form a first patterned photoresist layer 126 on the heavily doped N-type region 114 between any two adjacent gate electrodes 122 and expose the heavily doped N-type region 114 adjacent to each gate insulating layer 120. Then, using the first patterned photoresist layer 126 as a mask, a first P-type ion implantation process 128 is performed to implant two P-type ion regions into the N-type doped regions 114 on both sides of each gate insulating layer 120, and adjacent to the gate insulating layer 120. Then, a drive-in process is performed after removing the first patterned photoresist layer 126 to diffuse each P-type ion region, so as to form two P-type body doped regions 130 in the N-type heavily doped regions 114 on both sides of each gate insulating layer 120, and a portion of the N-type heavily doped region 114 is located between two P-type body doped regions 130 between any two adjacent gate insulating layers 120. In the present embodiment, the horizontal cross-sectional area of the P-type body doped region 130 is smaller as the depth of the P-type body doped region 130 is deeper, i.e., the horizontal cross-sectional area of the N-type heavily doped region 114 is larger as the depth is deeper. However, the present embodiment is not limited thereto, and the horizontal cross-sectional area of the P-type body doping region 130 may not change with the depth. Furthermore, the area of the P-type body doped region 130 can be controlled by adjusting the parameters of the first patterned photoresist layer 126, the first P-type ion implantation process 128, and the drive-in process, so as to adjust the area of the PN junction between the bottom of the P-type body doped region 130 and the N-type heavily doped region 114, thereby controlling the size of the depletion region formed between the P-type body doped region 130 and the N-type heavily doped region 114.
It is noted that, compared to the area and depth of the PN junction formed by the P-type body doped region and the N-type epitaxial layer in the prior art, the present invention uses the first patterned photoresist layer 126 to vertically and downwardly reduce the horizontal cross-sectional area of each P-type body doped region 130, so as to reduce the area of the PN junction formed by the bottom of each P-type body doped region 130 and the N-type heavily doped region 114, thereby effectively reducing the area of the depletion region between the bottom of each P-type body doped region 130 and the N-type doped region 114, so as to reduce the hole carriers injected into the N-type heavily doped region 114, i.e. reduce the excess minority carriers in the depletion region, thereby reducing the required reverse recovery time and increasing the switching speed of the rectifier formed by each P-type body doped region 130 and the N-type heavily doped region 114. In addition, the doping concentration of the heavily doped N-type region 114 of the present embodiment is greater than that of the epitaxial layer 112, so that the depletion region formed by the bottom of each P-type body doped region 130 and the heavily doped N-type region 114 is reduced, and the switching speed of the rectifier formed by each P-type body doped region 130 and the heavily doped N-type region 114 can also be increased.
As shown in FIG. 6, a second patterned photoresist layer 132 having the same pattern as the first patterned photoresist layer 126 is formed by using the first mask to define the position of the N-type source doped region 134. Then, a third N-type ion implantation process 136 is performed to implant N-type ions into each P-type body doping region 130 by using the second patterned photoresist layer 132 as a mask. Then, the second patterned photoresist layer 132 is removed, and a drive-in process is performed to form an N-type source doped region 134 in each P-type body doped region 130, adjacent to the gate insulating layer 120, and used as the source of the IGBT, wherein the doping concentration of the N-type source doped region 134 is greater than that of the N-type doped region 114 to prevent the injection of hole carriers into the N-type doped region 114, such as: the doping concentration of the N-type source doping region 134 is 1019To 1020cm-3But is not limited thereto. In addition, the present embodiment is not limited to performing the drive-in process to form the P-type body doped regions 130 before performing the third N-type ion implantation process 136, but the same first patterned photoresist layer 126 may be used to perform the first P-type ion implantation process 128 and the third N-type ion implantation process 136, and then performing the drive-in process to simultaneously form the P-type body doped regions 130 and the N-type source doped regions 134.
As shown in fig. 7, an interlayer dielectric layer 138(LED layer), such as a dielectric layer formed of boron-phosphorus-silicon-glass (BPSG) or other materials, is formed on the N-drift epitaxial layer 116. The dielectric layer 138 is then etched to form a plurality of openings 140, which respectively expose the heavily doped N-type regions 114 and a portion of the P-type body doped regions 130 on the other side of the N-type source doped regions 134 opposite to the gates 122. Then, using the dielectric layer 138 as a mask, a second P-type ion implantation process and a drive-in process are performed to form a P-type contact doped region 144 in the heavily doped N-type region 114 and the two P-type body doped regions 130 between any two adjacent gates 122, and the P-type contact doped region 144 is adjacent to the two N-type source doped regions 134 in the two P-type body doped regions 130 and serves as an anode of the rectifier and the contact doped region 144 of the IGBT. Then, using the dielectric layer 138 as a mask, a third P-type ion implantation process and a drive-in process are performed to form a P-type lightly doped region 146 between each P-type contact doped region 144 and the heavily doped region 114 on the other side of each P-type body doped region 130 opposite to each gate 122, and the P-type lightly doped region 146 is in contact with the N-type heavily doped region 114, and each P-type lightly doped region 146 further extends between each P-type contact doped region 144 and each corresponding P-type body doped region 130.
It should be noted that the step of forming the P-type contact doping region 144 is not limited to be performed before the step of forming the P-type lightly doped region 146, but the P-type lightly doped region 146 may be formed first and then the P-type contact doping region 144 is formed. Alternatively, a second P-type ion implantation process and a third P-type ion implantation process are performed first, and then a drive-in process is performed to simultaneously form the P-type contact doping region 144 and the P-type lightly doped region 146.
In addition, the implantation concentration of the second P-type ion implantation process is greater than that of the third P-type ion implantation process, so that the doping concentration of the P-type lightly doped region 146 is less than that of the P-type contact doped region 144, and the doping concentration of the P-type lightly doped region 146 is approximately the same as that of the P-type body doped region 130, for example: the doping concentration of the P-type lightly doped region 146 and the P-type body doped region 130 is 1016To 1017cm-3And the doping concentration of the P-type contact doping region 144 is 1019cm-3But is not limited thereto.
It should be noted that, since the doping concentration of the P-type lightly doped region 146 is less than the doping concentration of the P-type contact doped region 144, and the doping concentration of the N-type heavily doped region 114 is greater as approaching the P-type contact doped region 144, the P-type lightly doped region 146 is disposed between each P-type contact doped region 144 and the N-type heavily doped region 114 in this embodiment, so as to avoid the conduction generated by the contact between the P-type contact doped region 144 with high doping concentration and the N-type heavily doped region 114 with high doping concentration due to the reduction of the area of the P-type body doped region 130. In addition, the vertical depth of the P-type lightly doped region 146 is smaller than the vertical depth of the P-type body doped region 130, so as to prevent the P-type lightly doped region 146 from extending to the bottom of the P-type body doped region 130 and causing the area of the PN junction located at the same depth as the N-type heavily doped region 114 to expand.
A deposition process is performed, as shown in fig. 8, to form an emitter metal layer 148 on the dielectric layer 138 and fill the openings 140 of the dielectric layer 138 to serve as contact plugs electrically connecting the N-type source doped regions 134 and the P-type contact doped regions 144. Then, a thinning process is performed on the lower surface 106 of the P-type semiconductor substrate 102 until the N-type cathode doped region 108 is exposed, and a collector metal layer 150 is formed on the lower surface 106 of the P-type semiconductor substrate 102 and electrically connected to the N-type cathode doped region 108 to connect with the P-type semiconductor substrate 102. Thus, the integrated structure 100 of the IGBT and the fast reverse recovery time rectifier is completed. The emitter metal layer 148 and the collector metal layer 150 may be, but not limited to, aluminum (Al), titanium nitride (TiN), tungsten (w), or the like.
In addition, the integrated structure of the IGBT and the fast reverse recovery time rectifier of the present embodiment is not limited to have a plurality of trenches, gates 122 and gate insulating layers, but may have only a single trench, gate 122 and gate insulating layer. At this time, the P-type body doping regions 130 are only disposed on two sides of the gate insulation layer 120, and the N-type heavily doped regions 114 are disposed on the other side of each P-type body doping region 130 opposite to the gate 122.
It should be noted that fig. 9 is a cross-sectional view of a three-dimensional structure of an integrated structure of an igbt and a rectifier according to this embodiment. As shown in fig. 9, a portion of inter-layer dielectric 138 and emitter metal layer 148 along an extension direction 152 are not shown to more clearly illustrate the structure of each element. The integrated structure 100 of the IGBT and the fast rectifier of the present embodiment is a strip structure formed by extending the cross-sectional view of fig. 2 along the extending direction 152, so that the PN junction area of the P-body doped region 130 and the N-type heavily doped region 114 is determined by the horizontal width of the bottom of the P-body doped region 130, and the horizontal cross-sectional area of the P-body doped region 130 is determined by the horizontal width of the P-body doped region 130. In the present embodiment, the horizontal width of the P-type body doping region 130 is approximately between 1 micron and 3 microns, and the horizontal width of the heavily doped region 114 located between the P-type body doping regions 130 is approximately between 1 micron and 5 microns, but not limited thereto.
In the present embodiment, a patterned photoresist layer is used as a mask to form a P-type body doped region 130 in the N-type heavily doped region 114 on either side of each gate insulating layer 120, so that the P-type body doped region 130 between adjacent gates 122 is divided into two regions, thereby reducing the PN junction area between the bottom of the P-type body doped region 130 and the N-type heavily doped region 114, so as to shorten the required reverse recovery time and increase the switching speed of the rectifier formed by each P-type body doped region 130 and N-type heavily doped region 114. In addition, the present embodiment further arranges a P-type lightly doped region 146 between the N-type heavily doped region and the P-type contact doped region 144 to avoid the conduction generated by the contact between the P-type contact doped region 144 with high doping concentration and the N-type heavily doped region 114 with high doping concentration caused by reducing the area of the P-type body doped region 130.
The implementation of the embodiment has the following characteristics:
forming a substrate doping region 130 with the first conductivity type in the heavily doped region 114 with the second conductivity type on either side of each gate insulating layer 120, so as to divide the substrate doping region 130 between two adjacent gates 122, and further reduce the PN junction area between the bottom of the substrate doping region 130 and the heavily doped region 114, thereby reducing the injection amount of excess minority carriers of the rectifier by means of concentration difference at different positions while maintaining the same voltage endurance capability of the IGBT, and further increasing the fast reverse recovery time of the rectifier composed of the substrate doping region 130 and the heavily doped region 114, thereby realizing the design of the rectifier with increased fast reverse recovery time. In addition, a lightly doped region 146 of the first conductivity type is further disposed between the heavily doped region 114 and the contact doped region 144 in this embodiment to avoid conduction caused by the contact between the contact doped region 144 of the first conductivity type with high doping concentration and the heavily doped region 114 with high doping concentration due to the reduced area of the body doped region 130.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.
Claims (10)
1. A method for manufacturing an integrated structure of an insulated gate bipolar transistor and a rectifier includes:
providing a semiconductor substrate, wherein the semiconductor substrate has a first conductive type and comprises an upper surface and an opposite lower surface;
forming a cathode doped region in the semiconductor substrate, wherein the cathode doped region has a second conductive type;
forming a drift epitaxial layer on the upper surface of the semiconductor substrate, wherein the drift epitaxial layer has the second conduction type;
forming at least one gate insulating layer and at least one gate in the drift epitaxial layer, wherein the gate insulating layer is arranged between the drift epitaxial layer and the gate;
forming at least one substrate doping area in the drift epitaxial layer, wherein the substrate doping area is provided with the first conduction type; any substrate doping region, which has a bottom area designed according to preset parameters, so that the area of a PN junction formed by the bottom of the substrate doping region and the drift epitaxial layer is reduced;
forming a source doped region in the body doped region, wherein the source doped region has the second conductivity type and is adjacent to the gate insulating layer;
forming a contact doped region in the substrate doped region and the drift epitaxial layer, wherein the contact doped region has the first conductive type and is adjacent to the source doped region;
forming an emitter metal layer on the contact doped region and the source doped region, so that the emitter metal layer is electrically connected with the source doped region and the contact doped region;
performing a thinning process on the lower surface of the semiconductor substrate to expose the cathode doped region;
and forming a collector metal layer on the lower surface of the semiconductor substrate, wherein the collector metal layer is electrically connected with the cathode doped region and the semiconductor substrate.
2. The method of claim 1 wherein said forming at least one body dopant region within said drift epitaxial layer comprises:
and forming substrate doped regions on two sides of the gate insulating layer, so that the substrate doped regions are adjacent to the gate insulating layer, and one side, far away from the gate insulating layer, of the substrate doped regions is adjacent to the drift epitaxial layer.
3. The method of claim 2, wherein forming body-doped regions on both sides of the gate insulating layer comprises:
performing a photolithography process to form a first patterned photoresist layer on the drift epitaxial layer on one side of the gate insulating layer;
performing a first ion implantation process with the first conductive type on the drift epitaxial layer on both sides of the gate insulating layer based on the first patterned photoresist layer;
removing the first patterned photoresist layer;
and performing a first drive-in process to form the substrate doped region in the drift epitaxial layer adjacent to the two sides of the gate insulating layer.
4. The method of claim 3, wherein the horizontal cross-sectional area of the body doped region decreases as the depth of the body doped region increases.
5. The method of any of claims 1-4, wherein said forming a drift epitaxial layer on said semiconductor substrate comprises:
forming an epitaxial layer on the upper surface of the semiconductor substrate;
and forming a heavily doped region in the epitaxial layer, wherein the doping concentration of the heavily doped region is greater than that of the epitaxial layer, and the epitaxial layer and the heavily doped region form the drift epitaxial layer.
6. The method of claim 5, further comprising:
and forming a lightly doped region between the contact doped region and the heavily doped region, wherein the lightly doped region has the first conductivity type, and the doping concentration of the lightly doped region is less than that of the contact doped region.
7. The method of claim 6, wherein a depth of the lightly doped region is less than a depth of the bulk doped region.
8. The method of claim 6, wherein forming a lightly doped region between the contact doped region and the heavily doped region comprises:
a third ion implantation process and a third drive-in process are performed to form the lightly doped region.
9. The method of claim 5, wherein a doping concentration of the heavily doped region is less than a doping concentration of the source doped region.
10. The method of claim 1 wherein said forming a contact doped region in said body doped region and said drift epitaxial layer comprises:
a second ion implantation process and a second drive-in process are performed to form the contact doped region.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201114029A (en) * | 2009-10-06 | 2011-04-16 | Anpec Electronics Corp | IGBT with fast reverse recovery time rectifier and manufacturing method thereof |
| US20120193676A1 (en) * | 2011-01-31 | 2012-08-02 | Alpha Omega Semiconductor Incorp. | Diode structures with controlled injection efficiency for fast switching |
| US20180204938A1 (en) * | 2017-01-18 | 2018-07-19 | Semiconductor Manufacturing International (Shanghai) Corporation | Insulated gate bipolar transistor and fabrication method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201114029A (en) * | 2009-10-06 | 2011-04-16 | Anpec Electronics Corp | IGBT with fast reverse recovery time rectifier and manufacturing method thereof |
| US20120193676A1 (en) * | 2011-01-31 | 2012-08-02 | Alpha Omega Semiconductor Incorp. | Diode structures with controlled injection efficiency for fast switching |
| US20180204938A1 (en) * | 2017-01-18 | 2018-07-19 | Semiconductor Manufacturing International (Shanghai) Corporation | Insulated gate bipolar transistor and fabrication method thereof |
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