CN116614215A - Data synchronization method, device, signal receiving terminal and storage medium - Google Patents
Data synchronization method, device, signal receiving terminal and storage medium Download PDFInfo
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Abstract
The application discloses a data synchronization method, a device, a signal receiving terminal and a storage medium, wherein the data synchronization method comprises the following steps: carrying out logic operation on the received data signal and a predetermined local synchronous sequence symbol to obtain a first logic operation result, carrying out accumulation summation on the first logic operation result to obtain a first operation result, carrying out shift processing on the data signal to obtain a shift processing result, carrying out logic operation on the data signal and the shift processing result to obtain a second logic operation result, and carrying out accumulation summation on the second logic operation result to obtain a second operation result; determining a ratio between the first operation result and the second operation result, determining a synchronization position according to the ratio and a preset threshold value, and performing data synchronization according to the synchronization position. The method adopts logic operation, reduces the operation amount, and ensures the stability and consistency of the synchronous system because the threshold value is stable.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a data synchronization method, a data synchronization device, a signal receiving terminal, and a storage medium.
Background
In digital communication systems, timing synchronization is a fundamental condition for the receiver to correctly recover the transmitted signal. Timing synchronization for digital communication systems is typically a sliding correlation algorithm based on a known synchronization sequence. As shown in fig. 1, firstly, the received oversampling signal is multiplied by a local known synchronization sequence, then the multiplied result is accumulated and summed, the accumulated and summed result is compared with a set threshold, if the accumulated and summed result is greater than or equal to the threshold, the synchronization point can be determined according to the correlation peak value, namely, the synchronization is considered to be realized; if the result of the accumulated summation is less than the threshold, the received signal is slid by one sampling point, and the above correlation process is continued.
However, since the above scheme is a point-by-point multiplication and summation, the calculation amount is large, taking the length of the known synchronization sequence as M and the oversampling multiple as N as an example, and the calculation amount of one correlation process is M times of multiplication and M times of addition (N-1); and the result of accumulation and summation is directly compared with a threshold, the determination of the threshold is realized according to the received signal, and when the amplitude of the received signal is unstable, the value of the threshold is also unstable, so that the stability of the synchronous system is reduced.
Disclosure of Invention
The present application aims to solve at least one of the technical problems in the related art to some extent. Therefore, a first object of the present application is to provide a data synchronization method, which reduces the calculation amount of data synchronization by adopting a logic operation mode, and ensures the stability of the threshold value by adopting a mode of comparing the ratio of the first operation result to the second operation result with a preset threshold value, wherein the threshold value is not affected by the amplitude, modulation mode, etc. of the received data signal, thereby ensuring the stability and consistency of the synchronization system.
A second object of the present application is to propose a computer readable storage medium.
A third object of the present application is to propose a signal receiving terminal.
A fourth object of the present application is to provide a data synchronization device.
To achieve the above object, according to an embodiment of the first aspect of the present application, a data synchronization method is provided, including: carrying out logic operation on the received data signal and a predetermined local synchronous sequence symbol to obtain a first logic operation result, carrying out accumulation summation on the first logic operation result to obtain a first operation result, carrying out shift processing on the data signal to obtain a shift processing result, carrying out logic operation on the data signal and the shift processing result to obtain a second logic operation result, and carrying out accumulation summation on the second logic operation result to obtain a second operation result; determining a ratio between the first operation result and the second operation result, determining a synchronization position according to the ratio and a preset threshold value, and performing data synchronization according to the synchronization position.
According to the data synchronization method of the embodiment of the application, the received data signal and the predetermined local synchronization sequence symbol are subjected to logic operation to obtain a first logic operation result, the first logic operation result is subjected to accumulation and summation to obtain a first operation result, the data signal is subjected to shift processing to obtain a shift processing result, the data signal and the shift processing result are subjected to logic operation to obtain a second logic operation result, the second logic operation result is subjected to accumulation and summation to obtain a second operation result, the synchronization position is determined according to the ratio of the first operation result to the second operation result and a preset threshold value, and the data synchronization is performed according to the synchronization position. Therefore, the data signal and the local synchronous sequence symbol are subjected to logic operation, so that the related technology is replaced by multiplying the data signal with the local known synchronous sequence, the complexity of logic operation is low, the calculated amount is small, the calculated power consumption of data synchronization is reduced, and the consistency of the data synchronization is further ensured; and by adopting a mode of comparing the ratio of the first operation result and the second operation result with a preset threshold value, the threshold value is not influenced by the amplitude, the modulation mode and the like of the received data signal, the stability of the threshold value is ensured, and the stability and the consistency of a synchronous system are ensured.
According to one embodiment of the present application, performing a logic operation on a received data signal and a predetermined local synchronization sequence symbol to obtain a first logic operation result includes: performing exclusive OR operation on the data signal and a local synchronous sequence symbol to obtain a first operation value, wherein the local synchronous sequence symbol is 0 or 1; and subtracting the local synchronous sequence symbol from the first operation value to obtain a first logic operation result.
According to one embodiment of the present application, a shift process is performed on a data signal, including: the data signal is shifted rightward by a preset number of bits, wherein the preset number of bits is the number of bits of the data signal minus 1.
According to one embodiment of the present application, performing a logic operation on a data signal and a shift processing result to obtain a second logic operation result includes: performing exclusive OR operation on the data signal and the shift processing result to obtain a second operation value; and subtracting the shift processing result from the second operation value to obtain a second logic operation result.
According to one embodiment of the application, determining the synchronization position according to the ratio and a preset threshold value comprises: and when the times of the ratio continuously being greater than or equal to the preset threshold value reach the preset times, taking the middle position of the continuously preset data signals as the synchronous position.
To achieve the above object, an embodiment according to a second aspect of the present application provides a computer-readable storage medium having stored thereon a data synchronization program which, when executed by a processor, implements the data synchronization method of any one of the foregoing embodiments.
According to the computer readable storage medium of the embodiment of the application, through executing the computer program of the data synchronization method, the calculated amount of data synchronization is reduced by adopting a logic operation mode, and the threshold value is not influenced by the amplitude, modulation mode and the like of the received data signal by adopting a mode of comparing the ratio of the first operation result to the second operation result with a preset threshold value, so that the stability of the threshold value is ensured, and the stability and consistency of a synchronization system are ensured.
In order to achieve the above object, according to a third aspect of the present application, a signal receiving terminal is provided, which includes a memory, a processor, and a data synchronization program stored in the memory and executable on the processor, wherein the processor implements the data synchronization method of any one of the foregoing embodiments when executing the data synchronization program.
According to the signal receiving terminal provided by the embodiment of the application, the computer program of the data synchronization method is executed by the processor, the calculated amount of data synchronization is reduced by adopting a logic operation mode, and the threshold value is not influenced by the amplitude, the modulation mode and the like of the received data signal by adopting a mode of comparing the ratio of the first operation result to the second operation result with the preset threshold value, so that the stability of the threshold value is ensured, and the stability and the consistency of a synchronization system are ensured.
To achieve the above object, according to a fourth aspect of the present application, there is provided a data synchronization device, including: the first logic operation module is used for carrying out logic operation on the received data signal and a predetermined local synchronous sequence symbol to obtain a first logic operation result; the first accumulator is used for accumulating and summing the first logic operation result to obtain a first operation result; the shift module is used for carrying out shift processing on the data signals to obtain a shift processing result; the second logic operation module is used for carrying out logic operation on the data signal and the shift processing result to obtain a second logic operation result; the second accumulator is used for accumulating and summing the second logic operation result to obtain a second operation result; and the synchronization module is used for determining the ratio between the first operation result and the second operation result, determining a synchronization position according to the ratio and a preset threshold value, and performing data synchronization according to the synchronization position.
According to the data synchronization device of the embodiment of the application, the first logic operation module carries out logic operation on the received data signal and a predetermined local synchronization sequence symbol to obtain a first logic operation result, the first logic operation result is accumulated and summed through the first accumulator to obtain the first operation result, the shift module carries out shift processing on the data signal to obtain a shift processing result, the second logic operation module carries out logic operation on the data signal and the shift processing result to obtain a second logic operation result, the second accumulator carries out accumulation and summed on the second logic operation result to obtain a second operation result, and the synchronization position is determined through the synchronization module according to the ratio of the first operation result to the second operation result and a preset threshold value, and data synchronization is carried out according to the synchronization position. Therefore, the data signal and the local synchronous sequence symbol are subjected to logic operation, so that the multiplication of the data signal and the local known synchronous sequence in the related technology is replaced, the calculated amount of the logic operation is small, the calculated power consumption of the data synchronization is reduced, and the consistency of the data synchronization is further ensured; and by adopting a mode of comparing the ratio of the first operation result and the second operation result with a preset threshold value, the threshold value is not influenced by the amplitude, the modulation mode and the like of the received data signal, the stability of the threshold value is ensured, and the stability and the consistency of a synchronous system are ensured.
According to an embodiment of the present application, the first operation module and the second operation module respectively include: an exclusive-or gate, configured to perform an exclusive-or operation on the data signal and the local synchronization sequence symbol to obtain a first operation value, where the local synchronization sequence symbol is 0 or 1, or perform an exclusive-or operation on the data signal and the shift processing result to obtain a second operation value; the subtracter is used for subtracting the local synchronous sequence symbol from the first operation value to obtain a first logic operation result or subtracting the shift processing result from the second operation value to obtain a second logic operation result.
According to one embodiment of the application, the shift module is further configured to: the data signal is shifted rightward by a preset number of bits, wherein the preset number of bits is the number of bits of the data signal minus 1.
Additional aspects and advantages of the application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the application.
Drawings
FIG. 1 is a flow chart of a data synchronization method in the related art;
FIG. 2 is a flow diagram of a data synchronization method according to one embodiment of the application;
FIG. 3 is a flow chart of a method of data synchronization according to one embodiment of the application;
FIG. 4 is a flow chart of a method of data synchronization according to one embodiment of the application;
fig. 5 is a system diagram of a signal receiving terminal according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a data synchronization device according to one embodiment of the application;
fig. 7 is a schematic structural diagram of a data synchronization device according to another embodiment of the present application.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present application and should not be construed as limiting the application.
The data synchronization method, apparatus, signal receiving terminal and storage medium according to the embodiments of the present application are described below with reference to the accompanying drawings.
Fig. 2 is a flow chart of a data synchronization method according to an embodiment of the present application. As shown in fig. 2, the data synchronization method includes the steps of:
s101, carrying out logic operation on a received data signal and a predetermined local synchronous sequence symbol to obtain a first logic operation result, carrying out accumulation summation on the first logic operation result to obtain the first operation result, carrying out shift processing on the data signal to obtain a shift processing result, carrying out logic operation on the data signal and the shift processing result to obtain a second logic operation result, and carrying out accumulation summation on the second logic operation result to obtain a second operation result.
Specifically, the data signal is obtained by sampling signals sent by the signal sending terminal at different sampling points and is N-bit binary data, wherein N is a positive integer greater than 1, and the first bit of the data signal is a sign bit. Each sampling point is provided with a corresponding local synchronization sequence symbol, for example, the local synchronization sequence symbol corresponding to the first sampling point is 0, and the local synchronization sequence symbol corresponding to the second sampling point is 1. Performing logic operation on the data signal and the local synchronous sequence symbol to obtain a first logic operation result, and then performing accumulation and summation on the first logic operation result to obtain a first operation result; and simultaneously, carrying out shift processing on the data signals to obtain shift processing results, carrying out operation on the data signals and the shift processing results to obtain second logic operation results, and then carrying out accumulation and summation on the second logic operation results to obtain second operation results.
In some embodiments, performing a logical operation on the received data signal and a predetermined local synchronization sequence symbol to obtain a first logical operation result includes: performing exclusive OR operation on the data signal and a local synchronous sequence symbol to obtain a first operation value, wherein the local synchronous sequence symbol is 0 or 1; and subtracting the local synchronous sequence symbol from the first operation value to obtain a first logic operation result.
Specifically, a logical operation including an exclusive-or operation and a subtraction operation is performed on the data signal and the local synchronization sequence symbol, to obtain a first logical operation result. When the symbol of the local synchronous sequence is 0, the first logic operation result is a data signal; when the symbol of the local synchronization sequence is 1, the first logic operation result is the inverse of the data signal. For example, when the data signal is 16-bit binary data, the range of the data signal is between-32768 and 32767, when the data signal is 0111 1111 11111111, i.e. 32767, the first logical operation result is 0111 1111 11111111, i.e. 32767, if the local sync sequence symbol is 0, and the first logical operation result is 11111111 11111111, i.e. -32767, if the local sync sequence symbol is 1. And then, accumulating and summing the first logic operation result and the last first operation result to obtain a first operation result.
For example, the data signal of the first sampling point is 0111 11111111 1111, i.e. 32767, and the local sync sequence symbol corresponding to the first sampling point is 0, so the first logic operation result is 0111 11111111 1111, i.e. 32767. Since the data signal of the first sampling point is logically operated for the first time, there is no last first operation result, and the first operation result is 0. Then, the data signal of the second sampling point is 0100 00000000 0000, namely 16384, and the local synchronization sequence symbol corresponding to the second sampling point is 1, so that the first logic operation result is 1100 00000000 0000, namely-16384, and then 1100 00000000 0000 and the last first operation result 0111 11111111 1111 are added to obtain a first operation result 0011 11111111 1111, namely 16383. Then sliding one sampling point to the right, calculating a first logical operation result of a third sampling point, and adding the first logical operation result to the last first operation result 0011 11111111 1111 to obtain a first operation result.
In the above embodiment, the exclusive-or operation and the subtraction operation are adopted to replace the multiplier in the related art, and the operand of the exclusive-or operation and the subtraction operation is negligible compared with the multiplier, so that the calculation power consumption of data synchronization is reduced, and the consistency of the data synchronization is further ensured.
In some embodiments, shifting the data signal includes: the data signal is shifted rightward by a preset number of bits, wherein the preset number of bits is the number of bits of the data signal minus 1.
Specifically, since the first bit of the data signal is a sign bit, the data signal is shifted rightward by a preset number of bits, wherein the preset number of bits is the number of bits of the data signal minus 1, the sign bit of the data signal can be reserved.
For example, if the data signal is 0111 11111111 1111, 32767, the data signal is 16 bits, the preset number of bits is 16-1=15, the data signal is shifted 15 bits to the right, i.e. the shift processing result bit 0. If the data signal is 11111111 11111111, i.e., -32767, the data signal is shifted 15 bits to the right, i.e., bit 1 of the shift process result.
In the above embodiment, the sign bit of the data signal is reserved by shifting the data signal rightward by a preset number of bits.
In some embodiments, performing a logic operation on the data signal and the shift processing result to obtain a second logic operation result includes: performing exclusive OR operation on the data signal and the shift processing result to obtain a second operation value; and subtracting the shift processing result from the second operation value to obtain a second logic operation result.
Specifically, the data signal and the shift processing result are subjected to a logical operation including an exclusive-or operation and a subtraction operation, and the shift processing result corresponds to the sign bit of the data signal and is subjected to an absolute value operation. For example, the data signal is 0111 11111111 1111, 32767, the shift result is 0, and the second logical operation result is 0111 11111111 1111, 32767; the data signal is 11111111 11111111, namely-32767, the shift processing result is 1, and the second logic operation result is 0111 11111111 1111, namely 32767. The manner of accumulating and summing the second logic operation result is the same as the manner of accumulating and summing the first logic operation result, and will not be described in detail here.
In the above embodiment, by performing shift operation on the data signal, the sign bit of the data signal is reserved, and then performing exclusive-or operation and subtraction operation on the sign bit and the data signal, the absolute value operation on the data signal is realized, so that the operation amount is further reduced, and further, the calculation power consumption of data synchronization is further reduced.
S102, determining a ratio between the first operation result and the second operation result, determining a synchronous position according to the ratio and a preset threshold value, and performing data synchronization according to the synchronous position.
Specifically, the ratio between the first operation result and the second operation result is calculated, and then the ratio is compared with a preset threshold value to determine the synchronous position, so that the threshold value is not influenced by the amplitude, modulation mode and the like of the received data signal, and the stability of the threshold value is ensured. After the synchronization position is determined, data synchronization is performed with the synchronization position as a start position.
In some embodiments, determining the synchronization position based on the ratio and a preset threshold value includes: and when the times of the ratio continuously being greater than or equal to the preset threshold value reach the preset times, taking the middle position of the continuously preset data signals as the synchronous position.
For example, as shown in fig. 3, the preset number k is 3, the first data signal is obtained by sampling at the first sampling point, the first data signal is subjected to logic operation, the first logic operation result and the second logic operation result of the first data signal are respectively determined, and the first data signal is the first received data signal, so that the first logic operation result and the second logic operation result are the first operation result and the second operation result, then the first ratio of the first operation result and the second operation result is calculated, the first ratio is compared with the preset threshold, and if the first ratio is greater than or equal to the preset threshold, the sample point is slid to the right. Receiving a second data signal obtained by sampling at a second sampling point, carrying out logic operation on the second data signal, respectively determining a first logic operation result and a second logic operation result of the second data signal, respectively adding the first logic operation result and the second logic operation result of the second data signal with the first operation result and the second operation result of the last time to obtain the first operation result and the second operation result of the second data signal, then calculating a second ratio of the first operation result and the second operation result, comparing the second ratio with a preset threshold, and sliding one sampling point to the right if the second ratio is larger than or equal to the preset threshold. Receiving a third data signal obtained by sampling at a third sampling point, respectively determining a first logic operation result and a second logic operation result of the third data signal, respectively adding the first logic operation result and the second logic operation result of the third data signal with the first operation result and the second operation result of the last time to obtain the first operation result and the second operation result of the third data signal, then calculating a third ratio of the first operation result and the second operation result, comparing the third ratio with a preset threshold value, and if the third ratio is greater than or equal to the preset threshold value, determining a second sampling point corresponding to the second data signal as a synchronous position. And if the first ratio, the second ratio or the third ratio is smaller than a preset threshold, sliding one sampling point to the right, and repeatedly calculating the ratio of the data signals of the next sampling point until the number of times that the ratio is continuously larger than or equal to the preset threshold reaches the preset number of times.
In the above embodiment, the multiplier in the related art is replaced by the exclusive-or operation and the subtraction operation, and the operand of the exclusive-or operation and the subtraction operation is negligible compared with the multiplier, so that the calculation power consumption of data synchronization is reduced; and by adopting a mode of comparing the ratio of the first operation result and the second operation result with a preset threshold value, the threshold value is not influenced by the amplitude, the modulation mode and the like of the received data signal, the stability of the threshold value is ensured, and the stability and the consistency of a synchronous system are ensured.
The technical scheme of the application will be further described in detail below with reference to specific embodiments:
as shown in fig. 4, the data synchronization method includes the steps of:
s201, performing logic operation on a received data signal and a local synchronous sequence symbol to obtain a first logic operation result, performing accumulation and summation on the first logic operation result to obtain a first operation result, shifting the data signal rightwards by N-1 bits to obtain a shift processing result, performing logic operation on the data signal and the shift processing result to obtain a second logic operation result, and performing accumulation and summation on the second logic operation result to obtain a second operation result, wherein the data signal is an N-bit binary data signal, and the local synchronous sequence symbol is 0 or 1.
S202, calculating the ratio of the first operation result to the second operation result.
S203, judging whether the ratio is larger than or equal to a preset threshold, if the ratio is smaller than the preset threshold, executing step S204, and if the ratio is larger than or equal to the preset threshold, executing step S205.
S204, sliding a sampling point, and returning to step S201.
S205, judging whether the times of the ratio continuously larger than or equal to the preset threshold value reach the preset times, if the times of the ratio not continuously larger than or equal to the preset threshold value reach the preset times, executing step S204, and if the times of the ratio continuously larger than or equal to the preset threshold value reach the preset times, executing step S206.
S206, taking the intermediate positions of the continuous preset data signals as synchronous positions.
S207, taking the synchronous position as a starting position, and performing data synchronization.
In the above embodiment, the calculated amount of data synchronization is reduced by adopting a logic operation mode, and the threshold value is not affected by the amplitude, modulation mode and the like of the received data signal by adopting a mode of comparing the ratio of the first operation result to the second operation result with a preset threshold value, so that the stability of the threshold value is ensured, and the stability and consistency of the synchronization system are ensured.
According to the data synchronization method of the embodiment of the application, the received data signal and the predetermined local synchronization sequence symbol are subjected to logic operation to obtain a first logic operation result, the first logic operation result is subjected to accumulation and summation to obtain a first operation result, the data signal is subjected to shift processing to obtain a shift processing result, the data signal and the shift processing result are subjected to logic operation to obtain a second logic operation result, the second logic operation result is subjected to accumulation and summation to obtain a second operation result, the synchronization position is determined according to the ratio of the first operation result to the second operation result and a preset threshold value, and the data synchronization is performed according to the synchronization position. Therefore, the data signal and the local synchronous sequence symbol are subjected to logic operation, so that the related technology is replaced by multiplying the data signal with the local known synchronous sequence, the complexity of logic operation is low, the calculated amount is small, the calculated power consumption of data synchronization is reduced, and the consistency of the data synchronization is further ensured; and by adopting a mode of comparing the ratio of the first operation result and the second operation result with a preset threshold value, the threshold value is not influenced by the amplitude, the modulation mode and the like of the received data signal, the stability of the threshold value is ensured, and the stability and the consistency of a synchronous system are ensured.
Corresponding to the above embodiments, the embodiments of the present application further provide a computer readable storage medium having stored thereon a data synchronization program, which when executed by a processor, implements the data synchronization method of any of the foregoing embodiments.
According to the computer readable storage medium of the embodiment of the application, through executing the computer program of the data synchronization method, the calculated amount of data synchronization is reduced by adopting a logic operation mode, and the threshold value is not influenced by the amplitude, modulation mode and the like of the received data signal by adopting a mode of comparing the ratio of the first operation result to the second operation result with a preset threshold value, so that the stability of the threshold value is ensured, and the stability and consistency of a synchronization system are ensured.
Corresponding to the above embodiment, the embodiment of the present application further provides a signal receiving terminal. As shown in fig. 5, the signal receiving terminal 100 includes a memory 110, a processor 120, and a data synchronization program stored in the memory 110 and executable on the processor 120, and when the processor 120 executes the data synchronization program, the data synchronization method of any of the foregoing embodiments is implemented.
According to the signal receiving terminal provided by the embodiment of the application, the computer program of the data synchronization method is executed by the processor, the calculated amount of data synchronization is reduced by adopting a logic operation mode, and the threshold value is not influenced by the amplitude, the modulation mode and the like of the received data signal by adopting a mode of comparing the ratio of the first operation result to the second operation result with the preset threshold value, so that the stability of the threshold value is ensured, and the stability and the consistency of a synchronization system are ensured.
Corresponding to the above embodiment, the embodiment of the present application further provides a data synchronization device. As shown in fig. 6, the data synchronization apparatus includes: a first logic operation module 10, a first accumulator 20, a shift module 30, a second logic operation module 40, a second accumulator 50 and a synchronization module 60.
The first logic operation module 10 is configured to perform logic operation on the received data signal and a predetermined local synchronization sequence symbol, so as to obtain a first logic operation result; the first accumulator 20 performs accumulation and summation on the first logic operation result to obtain a first operation result; the shift module 30 is used for performing shift processing on the data signal to obtain a shift processing result; the second logic operation module 40 is configured to perform a logic operation on the data signal and the shift processing result, so as to obtain a second logic operation result; the second accumulator 50 is configured to accumulate and sum the second logic operation result to obtain a second operation result; the synchronization module 60 is configured to determine a ratio between the first operation result and the second operation result, determine a synchronization position according to the ratio and a preset threshold, and perform data synchronization according to the synchronization position.
In some embodiments, as shown in fig. 7, the first logic operation module 10 and the second logic operation module 40 respectively include: the data signal and the shift processing result are subjected to exclusive-or operation to obtain a second operation value, wherein the exclusive-or gate 11 is used for carrying out exclusive-or operation on the data signal and the local synchronous sequence symbol to obtain a first operation value, and the local synchronous sequence symbol is 0 or 1; the subtracter 12 is configured to subtract the first operation value from the local synchronization sequence symbol to obtain a first logic operation result, or subtract the second operation value from the shift processing result to obtain a second logic operation result.
In some embodiments, the shift module 30 is further to: the data signal is shifted rightward by a preset number of bits, wherein the preset number of bits is the number of bits of the data signal minus 1.
In some embodiments, the synchronization module 60 is further to: and when the times of the ratio continuously being greater than or equal to the preset threshold value reach the preset times, taking the middle position of the continuously preset data signals as the synchronous position.
It should be noted that, the specific implementation manner of the data synchronization device in the embodiment of the present application corresponds to the specific implementation manner of the data synchronization method in the foregoing embodiment of the present application one by one, and will not be described herein again.
According to the data synchronization device of the embodiment of the application, the first logic operation module carries out logic operation on the received data signal and a predetermined local synchronization sequence symbol to obtain a first logic operation result, the first logic operation result is accumulated and summed through the first accumulator to obtain the first operation result, the shift module carries out shift processing on the data signal to obtain a shift processing result, the second logic operation module carries out logic operation on the data signal and the shift processing result to obtain a second logic operation result, the second accumulator carries out accumulation and summed on the second logic operation result to obtain a second operation result, and the synchronization position is determined through the synchronization module according to the ratio of the first operation result to the second operation result and a preset threshold value, and data synchronization is carried out according to the synchronization position. Therefore, the data signal and the local synchronous sequence symbol are subjected to logic operation, so that the multiplication of the data signal and the local known synchronous sequence in the related technology is replaced, the calculated amount of the logic operation is small, the calculated power consumption of the data synchronization is reduced, and the consistency of the data synchronization is further ensured; and by adopting a mode of comparing the ratio of the first operation result and the second operation result with a preset threshold value, the threshold value is not influenced by the amplitude, the modulation mode and the like of the received data signal, the stability of the threshold value is ensured, and the stability and the consistency of a synchronous system are ensured.
It should be noted that the logic and/or steps represented in the flowcharts or otherwise described herein, for example, may be considered as a ordered listing of executable instructions for implementing logical functions, and may be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Furthermore, the terms "first," "second," and the like, as used in embodiments of the present application, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or as implying any particular number of features in the present embodiment. Thus, a feature of an embodiment of the application that is defined by terms such as "first," "second," etc., may explicitly or implicitly indicate that at least one such feature is included in the embodiment. In the description of the present application, the word "plurality" means at least two or more, for example, two, three, four, etc., unless explicitly defined otherwise in the embodiments.
While embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.
Claims (10)
1. A method of data synchronization, comprising:
carrying out logic operation on a received data signal and a predetermined local synchronous sequence symbol to obtain a first logic operation result, carrying out accumulation summation on the first logic operation result to obtain a first operation result, carrying out shift processing on the data signal to obtain a shift processing result, carrying out logic operation on the data signal and the shift processing result to obtain a second logic operation result, and carrying out accumulation summation on the second logic operation result to obtain a second operation result;
determining a ratio between the first operation result and the second operation result, determining a synchronization position according to the ratio and a preset threshold value, and performing data synchronization according to the synchronization position.
2. The method of claim 1, wherein logically operating the received data signal with a predetermined local synchronization sequence symbol to obtain a first logical operation result comprises:
performing exclusive OR operation on the data signal and the local synchronous sequence symbol to obtain a first operation value, wherein the local synchronous sequence symbol is 0 or 1;
and subtracting the local synchronous sequence symbol from the first operation value to obtain the first logic operation result.
3. The data synchronization method according to claim 1, wherein the shifting processing of the data signal includes:
and shifting the data signal to the right by a preset bit number, wherein the preset bit number is the bit number of the data signal minus 1.
4. A data synchronization method according to claim 3, wherein performing a logical operation on the data signal and the shift processing result to obtain a second logical operation result comprises:
performing exclusive OR operation on the data signal and the shift processing result to obtain a second operation value;
and subtracting the shift processing result from the second operation value to obtain the second logic operation result.
5. The method of any of claims 1-4, wherein determining a synchronization position based on the ratio and a preset threshold value comprises:
and when the times of the ratio continuously being larger than or equal to the preset threshold value reach the preset times, continuously presetting the middle position of the data signals as the synchronous position.
6. A computer-readable storage medium, on which a data synchronization program is stored, which, when executed by a processor, implements the data synchronization method of any one of claims 1-5.
7. A signal receiving terminal comprising a memory, a processor and a data synchronization program stored on the memory and executable on the processor, the processor implementing the data synchronization method of any one of claims 1-5 when executing the data synchronization program.
8. A data synchronization device, comprising:
the first logic operation module is used for carrying out logic operation on the received data signal and a predetermined local synchronous sequence symbol to obtain a first logic operation result;
the first accumulator is used for accumulating and summing the first logic operation result to obtain a first operation result;
the shift module is used for carrying out shift processing on the data signals to obtain shift processing results;
the second logic operation module is used for carrying out logic operation on the data signal and the shift processing result to obtain a second logic operation result;
the second accumulator is used for accumulating and summing the second logic operation result to obtain a second operation result;
and the synchronization module is used for determining the ratio between the first operation result and the second operation result, determining a synchronization position according to the ratio and a preset threshold value, and performing data synchronization according to the synchronization position.
9. The data synchronization device of claim 8, wherein the first logic operation module and the second logic operation module each comprise:
an exclusive-or gate, configured to perform an exclusive-or operation on the data signal and the local synchronization sequence symbol to obtain a first operation value, where the local synchronization sequence symbol is 0 or 1, or perform an exclusive-or operation on the data signal and the shift processing result to obtain a second operation value;
and the subtracter is used for subtracting the local synchronous sequence symbol from the first operation value to obtain the first logic operation result, or subtracting the shift processing result from the second operation value to obtain the second logic operation result.
10. The data synchronization device of claim 9, wherein the shift module is further configured to: and shifting the data signal to the right by a preset bit number, wherein the preset bit number is the bit number of the data signal minus 1.
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