CN111198673B - Word length adjusting method, device, equipment and storage medium - Google Patents
Word length adjusting method, device, equipment and storage medium Download PDFInfo
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- CN111198673B CN111198673B CN201811373931.0A CN201811373931A CN111198673B CN 111198673 B CN111198673 B CN 111198673B CN 201811373931 A CN201811373931 A CN 201811373931A CN 111198673 B CN111198673 B CN 111198673B
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Abstract
The embodiment of the invention discloses a word length adjusting method, a word length adjusting device, word length adjusting equipment and a storage medium. The method comprises the following steps: obtaining an original word length M and a target word length N of a signal to be processed; partitioning a field with the width of X of a signal to be processed from the most significant bit after the sign bit, wherein X is the difference value of the original word length M and the target word length N; and carrying out word length adjustment on the signal to be processed according to the blocks and the target word length N. The word length adjusting method, the word length adjusting device, the word length adjusting equipment and the storage medium can improve the performance of a digital signal processing system and avoid word length waste and signal overflow.
Description
Technical Field
The present invention relates to the field of data processing technologies, and in particular, to a method, an apparatus, a device, and a storage medium for adjusting a word length.
Background
In Digital Signal Processing (DSP), the size of the number of bits (word length) occupied by data participating in an operation directly determines the operation amount of an operation module and the size of a storage space for storing an intermediate result, thereby determining the complexity, device cost, and power consumption of a DSP system. On the premise of ensuring that the performance is not lost, reducing the word length of the operation data to the maximum extent is one of the main tasks of DSP algorithm design.
The currently commonly used word length adjustment means is an Automatic Gain Control (AGC) technique. The digital AGC technology adjusts the word length as follows: and calculating the average value of a section of data, adjusting the amplitude of the target data by taking the average value as a basis, and intercepting the adjusted data to adjust the word length so as to achieve the purpose of limiting the word length. For example, assuming that a segment of data includes 1000 digital signals, each digital signal occupies 16 bits, the average value of the segment of data digital signals is calculated to be 234, and the adjustment target word length is 8 bits. It is understood that if the average value is 234, there are digital signals greater than 234 in the 1000 digital signals, and the number of bits corresponding to the maximum value of the digital signals greater than 234 in the 1000 digital signals is not higher than 11 according to the statistical characteristics of the signals. When the target data signal is cut, the data with the data height of 16-11 and the data with the data height of 11-8 and the data with the data height of 3 are discarded. For example, assuming that the 16-bit 2-ary data corresponding to the target data signal is 0101111101010101, the 8-bit 2-ary data corresponding to the adjusted data signal is 11101010.
The digital AGC technique adjusts the word length of the subsequent signal by using the current average value, so the word length adjustment effect of the value obtained by the size of the data block used for calculating the average value (i.e. the estimation time for obtaining an average value) is relatively large. Especially for the burst signal scenario, the target signal to be processed may be a useful signal or pure noise, and if the word length of the next useful signal is adjusted by the average value of the current pure noise, the performance of the DSP system may be degraded. In addition, the word length adjustment requires attention to the maximum and minimum values of the signal. At the maximum the signal cannot overflow and at the minimum the accuracy of the data cannot be lost. The average value of the signal cannot completely reflect the maximum value and the minimum value of the signal, especially for a signal with a large peak-to-average ratio, the difference between the average value of the signal and the maximum value or the minimum value is large, and if the difference is not estimated accurately, the word length may be wasted (the effective word length is far smaller than the output word length) or the signal amplitude exceeds the maximum word length, so that overflow occurs.
Disclosure of Invention
Embodiments of the present invention provide a word length adjusting method, apparatus, device, and storage medium, which can improve performance of a digital signal processing system and avoid waste of word length and occurrence of signal overflow.
In one aspect, an embodiment of the present invention provides a word length adjusting method, including:
obtaining an original word length M and a target word length N of a signal to be processed;
partitioning a field with the width of X of a signal to be processed from the most significant bit after the sign bit, wherein X is the difference value of the original word length M and the target word length N;
and adjusting the word length of the signal to be processed according to the blocks and the target word length N.
In one embodiment of the present invention, partitioning a signal to be processed into blocks starting from a most significant bit after a sign bit and having a width X, includes:
and dividing the signal to be processed into Y blocks from the most significant bit after the sign bit and the field with the width of X, wherein Y is equal to the sum of the value of the quotient of X and n after being rounded downwards and 1, and n is the step size of the blocks.
In an embodiment of the present invention, adjusting the word length of the signal to be processed according to the block and the target word length N includes:
for Y block fields with the total width of X starting from the most significant bit after the sign bit, sequentially judging whether the value corresponding to each block field is zero or not starting from the 1 st block field until judging the field blocks with the values not being zero corresponding to the block fields;
and adjusting the word length of the signal to be processed according to the field block with the value not equal to zero corresponding to the block field and the target word length N.
In an embodiment of the present invention, according to a field block whose value corresponding to a block field is not zero and a target word length N, performing word length adjustment on a signal to be processed, including:
extracting data with the word length of N-1 from the highest bit of a field block with the value not equal to zero corresponding to the block field;
and splicing the sign bit of the signal to be processed and the data with the word length of N-1 to obtain the signal with the word length of N corresponding to the signal to be processed.
In an embodiment of the present invention, according to a field block whose value corresponding to a block field is not zero and a target word length N, performing word length adjustment on a signal to be processed, including:
searching a bit corresponding to 1 from a high bit to a low bit in a field block with a value not equal to zero corresponding to a block field, and extracting data with the word length of N-1 from the bit corresponding to the first searched 1;
and splicing the sign bit of the signal to be processed and the data with the word length of N-1 to obtain the signal with the word length of N corresponding to the signal to be processed.
In an embodiment of the present invention, the word length adjusting method provided in the embodiment of the present invention further includes:
if the values corresponding to the Y block fields are all zero, extracting low N-1 bit data of the signal to be processed;
and splicing the sign bit and the low N-1 bit data of the signal to be processed to obtain a signal with the word length of N corresponding to the signal to be processed.
On the other hand, an embodiment of the present invention provides a word length adjusting device, including:
the device comprises an obtaining module, a processing module and a processing module, wherein the obtaining module is used for obtaining an original word length M and a target word length N of a signal to be processed;
the block module is used for blocking a field with the width of X from the most significant bit after the sign bit of the signal to be processed, wherein X is the difference value of the original word length M and the target word length N;
and the adjusting module is used for adjusting the word length of the signal to be processed according to the blocks and the target word length N.
In an embodiment of the present invention, the blocking module is specifically configured to:
and dividing the signal to be processed into Y blocks from the most significant bit after the sign bit and the field with the width of X, wherein Y is equal to the sum of the value of the quotient of X and n after being rounded downwards and 1, and n is the step size of the blocks.
In one embodiment of the invention, the adjustment module comprises:
the judging unit is used for sequentially judging whether the value corresponding to each block of field is zero or not from the 1 st block of field data aiming at the Y block of field with the total width of X from the most significant bit after the sign bit until judging the field block of which the value corresponding to the block of field is not zero;
and the adjusting unit is used for adjusting the word length of the signal to be processed according to the field block with the value not equal to zero corresponding to the block field and the target word length N.
In an embodiment of the present invention, the adjusting unit is specifically configured to:
extracting data with the word length of N-1 from the highest bit of a field block with the value not equal to zero corresponding to the block field;
and splicing the sign bit of the signal to be processed and the data with the word length of N-1 to obtain the signal with the word length of N corresponding to the signal to be processed.
In an embodiment of the present invention, the adjusting unit is specifically configured to:
searching a bit corresponding to 1 from a high bit to a low bit in a field block with a value not equal to zero corresponding to a block field, and extracting data with the word length of N-1 from the bit corresponding to the first searched 1;
and splicing the sign bit of the signal to be processed and the data with the word length of N-1 to obtain the signal with the word length of N corresponding to the signal to be processed.
In an embodiment of the present invention, the adjusting unit is further configured to:
if the values corresponding to the Y block fields are all zero, extracting low N-1 bit data of the signal to be processed;
and splicing the sign bit and the low N-1 bit data of the signal to be processed to obtain a signal with the word length of N corresponding to the signal to be processed.
In another aspect, an embodiment of the present invention provides a word length adjusting apparatus, where the apparatus includes: a memory, a processor, and a computer program stored on the memory and executable on the processor;
the processor implements the word length adjusting method provided by the embodiment of the invention when executing the computer program.
In another aspect, an embodiment of the present invention provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the computer program implements the word length adjusting method provided in the embodiment of the present invention.
The word length adjusting method, the word length adjusting device, the word length adjusting equipment and the storage medium can improve the performance of a digital signal processing system and avoid word length waste and signal overflow.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic flow chart illustrating a word length adjusting method according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating a blocking result provided by an embodiment of the present invention;
FIG. 3 is a diagram illustrating a first result of word size adjustment provided by an embodiment of the present invention;
FIG. 4 is a diagram illustrating a second result of word size adjustment provided by an embodiment of the present invention;
FIG. 5 is a diagram illustrating a third result of word size adjustment provided by an embodiment of the present invention;
fig. 6 is a schematic structural diagram illustrating a word length adjusting apparatus according to an embodiment of the present invention;
fig. 7 is a block diagram illustrating an exemplary hardware architecture of a computing device capable of implementing the word size adjustment method and apparatus according to an embodiment of the present invention.
Detailed Description
Features and exemplary embodiments of various aspects of the present invention will be described in detail below, and in order to make objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
As shown in fig. 1, fig. 1 is a schematic flow chart illustrating a word length adjusting method according to an embodiment of the present invention. The word length adjusting method may include:
s101: and obtaining the original word length M and the target word length N of the signal to be processed.
S102: and partitioning the signal to be processed from the most significant bit after the sign bit by using a field with the width of X.
And X is the difference value between the original word length M and the target word length N.
It will be appreciated that the original word length M is greater than the target word length N.
S103: and adjusting the word length of the signal to be processed according to the blocks and the target word length N.
According to the word length adjusting method provided by the embodiment of the invention, how to adjust each signal word length is determined by the own signal, and the situation that the signal amplitude estimation is inaccurate and the useful signal is adjusted by mistake due to the occurrence of pure noise in a burst signal scene can be avoided, so that the performance of a digital signal processing system can be improved.
The following describes in detail the word length adjusting method provided in the embodiment of the present invention with a specific example.
The signal to be processed is assumed to be a complex signal, the complex signal includes a real part I and an imaginary part Q, an original word length of the complex signal is M bits, and a corresponding target word length is N bits. The target word length N in the embodiment of the present invention means that the word length of the adjusted signal is N.
Taking absolute values of the real part I and the imaginary part Q, comparing the absolute values of the real part I and the imaginary part Q, and marking the larger absolute value as MAXIQ。
It is understood that MAXIQThe most significant bit of the signal to be processed is the most significant bit after the sign bit.
Will MAXIQDividing the M-N bits from high to low into Y blocks,
n is the step size of the block,
indicating that the quotient of (M-N) and N is rounded down.
Wherein the first and second phases, 1, 2, … …,
blocks, each block comprising n bits; first, the
The block contains k bits. If (M-N)/N is a small number, then
If (M-N)/N is an integer, k is 0.
The blocking result is shown in fig. 2, and fig. 2 shows a schematic diagram of the blocking result provided by the embodiment of the present invention.
To is directed at
The block fields are sequentially judged whether the value corresponding to each block field is zero or not from the 1 st block field until the field block of which the value corresponding to the block field is not zero is judged; and adjusting the word length of the signal to be processed according to the field block with the value not equal to zero corresponding to the block field and the target word length N.
In an embodiment of the present invention, according to a field block whose value corresponding to a block field is not zero and a target word length N, performing word length adjustment on a signal to be processed may include: extracting data with the word length of N-1 from the highest bit of a field block with the value not equal to zero corresponding to the block field; and splicing the sign bit of the signal to be processed and the data with the word length of N-1 to obtain the signal with the word length of N corresponding to the signal to be processed.
Assuming that the block of the field with non-zero value corresponding to the block field is the second
Block, then from
Extracting data with the word length of N-1 from the highest order bit of the block; and splicing the sign bit of the signal to be processed and the data with the word length of N-1 to obtain the signal with the word length of N corresponding to the signal to be processed.
From the first
Extracting data with the word length of N-1 from the highest order bit of the block; the sign bit of the signal to be processed and the data with the word length of N-1 are spliced to obtain the result of the signal with the word length of N corresponding to the signal to be processed, as shown in fig. 3. Fig. 3 is a diagram illustrating a first result of word size adjustment according to an embodiment of the present invention.
In an embodiment of the present invention, according to a field block whose value corresponding to a block field is not zero and a target word length N, performing word length adjustment on a signal to be processed may include: searching a bit corresponding to 1 from a high bit to a low bit in a field block with a value not equal to zero corresponding to a block field, and extracting data with the word length of N-1 from the bit corresponding to the first searched 1; and splicing the sign bit of the signal to be processed and the data with the word length of N-1 to obtain the signal with the word length of N corresponding to the signal to be processed.
Assuming that the block of the field with non-zero value corresponding to the block field is the second
Block, then from
Searching the bit corresponding to 1 from the high order bit to the low order bit in the block, assuming that n is 4, the first order bit
The binary value corresponding to block data is 0011. Then from the first
Extracting data with the word length of N-1 from the 3 rd bit from left to right in the block data; splicing the sign bit of the signal to be processed and the data with the word length of N-1 to obtain the signal with the word length of N corresponding to the signal to be processedThe adjustment results are shown in fig. 4. Fig. 4 is a diagram illustrating a second result of word size adjustment according to an embodiment of the present invention.
In one embodiment of the present invention, if
If the values corresponding to the block fields are all zero, extracting low N-1 bit data of the signal to be processed; and splicing the sign bit and the low N-1 bit data of the signal to be processed to obtain a signal with the word length of N corresponding to the signal to be processed.
The word length adjustment result is shown in fig. 5. Fig. 5 is a diagram illustrating a third result of word size adjustment according to an embodiment of the present invention.
According to the word length adjusting method provided by the embodiment of the invention, how to adjust each signal word length is determined by the own signal, and the situation that the signal amplitude estimation is inaccurate and the useful signal is adjusted by mistake due to the occurrence of pure noise in a burst signal scene can be avoided, so that the performance of a digital signal processing system can be improved. In addition, the embodiment of the invention adjusts the word length according to the field block with the value which is not zero and corresponds to the block field, thereby effectively avoiding the waste of the word length and the occurrence of signal overflow. In addition, the embodiment of the invention can reduce the system overhead and improve the word length adjusting efficiency by searching the bit corresponding to the 1 in a blocking way.
Corresponding to the above method embodiment, the embodiment of the present invention further provides a word length adjusting device. As shown in fig. 6, fig. 6 is a schematic structural diagram of a word length adjusting device according to an embodiment of the present invention. The word length adjusting means may include:
an obtaining module 601, configured to obtain an original word length M and a target word length N of a signal to be processed.
A block module 602, configured to block a field with a width X starting from a most significant bit after a sign bit of the signal to be processed.
Wherein, X is the difference value between the original word length M and the target word length N.
And an adjusting module 603, configured to adjust a word length of the signal to be processed according to the block and the target word length N.
In an embodiment of the present invention, the blocking module 602 may specifically be configured to:
and dividing the signal to be processed into Y blocks from the most significant bit after the sign bit and the field with the width of X, wherein Y is equal to the sum of the value of the quotient of X and n after being rounded downwards and 1, and n is the step size of the blocks.
In an embodiment of the present invention, the adjusting module 603 may include:
the judging unit is used for sequentially judging whether a value corresponding to each block field is zero or not from the 1 st block field aiming at the Y block fields with the total width of n and starting from the most significant bit after the sign bit until the field block with the value not being zero corresponding to the block field is judged;
and the adjusting unit is used for adjusting the word length of the signal to be processed according to the field block with the value not equal to zero corresponding to the block field and the target word length N.
In an embodiment of the present invention, the adjusting unit may specifically be configured to:
extracting data with the word length of N-1 from the highest bit of a field block with the value not equal to zero corresponding to the block field;
and splicing the sign bit of the signal to be processed and the data with the word length of N-1 to obtain the signal with the word length of N corresponding to the signal to be processed.
In an embodiment of the present invention, the adjusting unit may specifically be configured to:
searching a bit corresponding to 1 from a high bit to a low bit in a field block with a value not equal to zero corresponding to a block field, and extracting data with the word length of N-1 from the bit corresponding to the first searched 1;
and splicing the sign bit of the signal to be processed and the data with the word length of N-1 to obtain the signal with the word length of N corresponding to the signal to be processed.
In an embodiment of the present invention, the adjusting unit may further be configured to:
if the values corresponding to the Y block fields are all zero, extracting low N-1 bit data of the signal to be processed;
and splicing the sign bit and the low N-1 bit data of the signal to be processed to obtain a signal with the word length of N corresponding to the signal to be processed.
According to the word length adjusting device provided by the embodiment of the invention, how to adjust each signal word length is determined by the own signal, and the situation that the signal amplitude estimation is inaccurate and the useful signal is adjusted by mistake due to the occurrence of pure noise in a burst signal scene can be avoided, so that the performance of a digital signal processing system can be improved. In addition, the embodiment of the invention adjusts the word length according to the field block with the value not equal to zero corresponding to the field block data, thereby effectively avoiding the waste of the word length and the occurrence of signal overflow. In addition, the embodiment of the invention can reduce the system overhead and improve the word length adjusting efficiency by searching the bit corresponding to the 1 in a blocking way.
Fig. 7 is a block diagram illustrating an exemplary hardware architecture of a computing device capable of implementing the word size adjustment method and apparatus according to an embodiment of the present invention. As shown in fig. 7, computing device 700 includes an input device 701, an input interface 702, a central processor 703, a memory 704, an output interface 705, and an output device 706. The input interface 702, the central processor 703, the memory 25704, and the output interface 705 are connected to each other via a bus 710, and the input device 701 and the output device 706 are connected to the bus 710 via the input interface 702 and the output interface 705, respectively, and further connected to other components of the computing device 700.
Specifically, the input device 701 receives input information from the outside, and transmits the input information to the central processor 703 through the input interface 702; the central processor 703 processes input information based on computer-executable instructions stored in the memory 704 to generate output information, stores the output information temporarily or permanently in the memory 704, and then transmits the output information to the output device 706 through the output interface 705; the output device 706 outputs output information external to the computing device 700 for use by a user.
That is, the computing device shown in fig. 7 may also be implemented as a word length adjusting device that may include: a memory storing computer executable instructions; and a processor which, when executing computer executable instructions, may implement the word size adjustment methods and apparatus described in connection with fig. 1-6.
An embodiment of the present invention further provides a computer-readable storage medium, where the computer-readable storage medium has computer program instructions stored thereon; the computer program instructions, when executed by a processor, implement the word size adjustment method provided by embodiments of the present invention.
It is to be understood that the invention is not limited to the specific arrangements and instrumentality described above and shown in the drawings. A detailed description of known methods is omitted herein for the sake of brevity. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present invention are not limited to the specific steps described and illustrated, and those skilled in the art can make various changes, modifications and additions or change the order between the steps after comprehending the spirit of the present invention.
The functional blocks shown in the above-described structural block diagrams may be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, plug-in, function card, or the like. When implemented in software, the elements of the invention are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine-readable medium or transmitted by a data signal carried in a carrier wave over a transmission medium or a communication link. A "machine-readable medium" may include any medium that can store or transfer information. Examples of a machine-readable medium include electronic circuits, semiconductor memory devices, ROM, flash memory, Erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, Radio Frequency (RF) links, and so forth. The code segments may be downloaded via computer networks such as the internet, intranet, etc.
It should also be noted that the exemplary embodiments mentioned in this patent describe some methods or systems based on a series of steps or devices. However, the present invention is not limited to the order of the above-described steps, that is, the steps may be performed in the order mentioned in the embodiments, may be performed in an order different from the order in the embodiments, or may be performed simultaneously.
As described above, only the specific embodiments of the present invention are provided, and it can be clearly understood by those skilled in the art that, for convenience and simplicity of description, the specific working processes of the system, the module and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again. It should be understood that the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present invention, and these modifications or substitutions should be covered within the scope of the present invention.
Claims (10)
1. A word length adjusting method is characterized by comprising the following steps:
obtaining an original word length M and a target word length N of a signal to be processed;
partitioning a field with the width of X of the signal to be processed from the most significant bit after the sign bit, wherein X is the difference value of the original word length M and the target word length N;
adjusting the word length of the signal to be processed according to the blocks and the target word length N;
the partitioning the to-be-processed signal from the most significant bit after the sign bit by a field with a width of X, includes:
dividing a field with the width of X of the signal to be processed into Y blocks from the most significant bit after the sign bit, wherein Y is equal to the sum of the value of the quotient of X and n after being rounded downwards and 1, and n is the step length of the block;
the adjusting the word length of the signal to be processed according to the block and the target word length N includes:
starting from the 1 st block field, sequentially judging whether the value corresponding to each block field is zero or not for Y block fields with the total width of X starting from the most significant bit after the sign bit until judging the field blocks with the values not being zero corresponding to the block fields;
and adjusting the word length of the signal to be processed according to the field block with the value not equal to zero corresponding to the block field and the target word length N.
2. The method according to claim 1, wherein the adjusting the word length of the signal to be processed according to the field block with the value different from zero corresponding to the block field and the target word length N comprises:
extracting data with the word length of N-1 from the highest bit of the field block with the value not equal to zero corresponding to the block field;
and splicing the sign bit of the signal to be processed and the data with the word length of N-1 to obtain the signal with the word length of N corresponding to the signal to be processed.
3. The method according to claim 1, wherein the adjusting the word length of the signal to be processed according to the field block with the value different from zero corresponding to the block field and the target word length N comprises:
searching a bit corresponding to 1 from a high bit to a low bit in a field block of which the value corresponding to the block field is not zero, and extracting data with the word length of N-1 from the bit corresponding to the 1 searched first;
and splicing the sign bit of the signal to be processed and the data with the word length of N-1 to obtain the signal with the word length of N corresponding to the signal to be processed.
4. The method of claim 1, further comprising:
if all the values corresponding to the Y block fields are zero, extracting low N-1 bit data of the signal to be processed;
and splicing the sign bit of the signal to be processed and the low N-1 bit data to obtain a signal with the word length of N corresponding to the signal to be processed.
5. A character length adjusting apparatus, comprising:
the device comprises an obtaining module, a processing module and a processing module, wherein the obtaining module is used for obtaining an original word length M and a target word length N of a signal to be processed;
a block module, configured to block a field of the to-be-processed signal, which starts from a most significant bit after a sign bit and has a width of X, where X is a difference between the original word length M and the target word length N;
the adjusting module is used for adjusting the word length of the signal to be processed according to the blocks and the target word length N;
the blocking module is specifically configured to:
dividing a field with the width of X of the signal to be processed into Y blocks from the most significant bit after the sign bit, wherein Y is equal to the sum of the value of the quotient of X and n after being rounded downwards and 1, and n is the step length of the block;
the adjustment module includes:
a judging unit, configured to, starting with a 1 st block field, sequentially judge, for a Y block field having a total width of X and starting with a most significant bit after a sign bit, whether a value corresponding to the block field is zero or not for each block field until a field block having a value not zero is judged;
and the adjusting unit is used for adjusting the word length of the signal to be processed according to the field block corresponding to the block field and the target word length N, wherein the value of the field block is not zero.
6. The apparatus according to claim 5, wherein the adjusting unit is specifically configured to:
extracting data with the word length of N-1 from the highest bit of the field block with the value not equal to zero corresponding to the block field;
and splicing the sign bit of the signal to be processed and the data with the word length of N-1 to obtain the signal with the word length of N corresponding to the signal to be processed.
7. The apparatus according to claim 5, wherein the adjusting unit is specifically configured to:
searching a bit corresponding to 1 from a high bit to a low bit in a field block of which the value corresponding to the block field is not zero, and extracting data with the word length of N-1 from the bit corresponding to the 1 searched first;
and splicing the sign bit of the signal to be processed and the data with the word length of N-1 to obtain the signal with the word length of N corresponding to the signal to be processed.
8. The apparatus of claim 5, wherein the adjusting unit is further configured to:
if all the values corresponding to the Y block fields are zero, extracting low N-1 bit data of the signal to be processed;
and splicing the sign bit of the signal to be processed and the low N-1 bit data to obtain a signal with the word length of N corresponding to the signal to be processed.
9. A word size adjusting apparatus, characterized in that the apparatus comprises: a memory, a processor, and a computer program stored on the memory and executable on the processor;
the processor, when executing the computer program, implements the word size adjustment method of any one of claims 1 to 4.
10. A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor, implements the word size adjusting method according to any one of claims 1 to 4.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6259384B1 (en) * | 1999-07-09 | 2001-07-10 | Quantum Corporation | High rate runlength limited codes for 10-bit ECC symbols |
| CN101165510A (en) * | 2006-10-18 | 2008-04-23 | 中国科学院电子学研究所 | Spaceborne synthetic aperture radar variable digit BAQ compression system and method |
| CN101389027A (en) * | 2008-09-28 | 2009-03-18 | 华为技术有限公司 | Watermark embedding method, watermark extracting method, device and system |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2522269B2 (en) * | 1986-11-28 | 1996-08-07 | 三菱電機株式会社 | Multiplexed data separation controller |
| CN101997566B (en) * | 2010-11-08 | 2014-07-09 | 北京理工大学 | Maximum absolute value cumulative mean and grid comparison-based adaptive bit cutting method |
| CN105227190B (en) * | 2014-06-20 | 2019-05-14 | 北京邮电大学 | A kind of building method multiplying the LDPC code of cyclic subgroup in group based on finite field |
| CN106127586A (en) * | 2016-06-17 | 2016-11-16 | 上海经达信息科技股份有限公司 | Vehicle insurance rate aid decision-making system under big data age |
| US10410098B2 (en) * | 2017-04-24 | 2019-09-10 | Intel Corporation | Compute optimizations for neural networks |
-
2018
- 2018-11-19 CN CN201811373931.0A patent/CN111198673B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6259384B1 (en) * | 1999-07-09 | 2001-07-10 | Quantum Corporation | High rate runlength limited codes for 10-bit ECC symbols |
| CN101165510A (en) * | 2006-10-18 | 2008-04-23 | 中国科学院电子学研究所 | Spaceborne synthetic aperture radar variable digit BAQ compression system and method |
| CN101389027A (en) * | 2008-09-28 | 2009-03-18 | 华为技术有限公司 | Watermark embedding method, watermark extracting method, device and system |
Non-Patent Citations (1)
| Title |
|---|
| 6 to 64 Bits: Hexadecimal Numbers Significant to Drive/Partition Limits;Daniel B. Sedory;《https://thestarman.pcministry.com/asm/6to64bits.htm》;20070413;1 * |
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