CN110247734B - Data transmission method and device and electronic equipment - Google Patents
Data transmission method and device and electronic equipment Download PDFInfo
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- CN110247734B CN110247734B CN201910526092.XA CN201910526092A CN110247734B CN 110247734 B CN110247734 B CN 110247734B CN 201910526092 A CN201910526092 A CN 201910526092A CN 110247734 B CN110247734 B CN 110247734B
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Abstract
The application discloses a data transmission method, a data transmission device, a transmitter and a receiver, wherein the method comprises the following steps: obtaining a target data packet to be transmitted, wherein the target data packet comprises a plurality of data bits, and the data bits have phases; obtaining the phase of a data bit in a first data packet after the transmission of a target data packet is completed; processing the phase of the data bit in the target data packet based at least on the phase of the data bit in the first data packet; and transmitting the target data packet subjected to the phase processing. Therefore, in the application, when a target data packet is transmitted, phase processing is performed based on the data bit phase of the previously transmitted data packet to distinguish the data packets transmitted before and after, so that the purpose of limiting the stroke length of data transmission is achieved, and a circuit stably works.
Description
Technical Field
The present disclosure relates to the field of data processing technologies, and in particular, to a data transmission method and apparatus, and an electronic device.
Background
In a Clock and Data Recovery (CDR) circuit constructed by a phase-locked loop, data transmitted from a transmitter to a receiver has a run-length, which is a length of a phase transmitted within a transmission time T of a certain packet in the CDR circuit. In order to keep the circuit stable, the maximum stroke length needs to be limited.
In existing limiting schemes, additional bits are typically added at specific locations of each T in the transmitted data to characterize the end or start bits of the run length.
However, this scheme for transmitting data may add extra transmission content, resulting in inefficient data transmission.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a data transmission method, an apparatus, a transmitter and a receiver, so as to solve the technical problem in the prior art that the data transmission efficiency is low when the stroke length of data transmission is limited.
The application provides a data transmission method, which comprises the following steps:
obtaining a target data packet to be transmitted, wherein the target data packet comprises a plurality of data bits, and the data bits have phases;
obtaining the phase of a data bit in a first data packet which is transmitted before the target data packet;
processing the phase of the data bit in the target data packet based at least on the phase of the data bit in the first data packet;
and transmitting the target data packet subjected to the phase processing.
Preferably, the method for processing the phase of the data bit in the target data packet based on at least the phase of the data bit in the first data packet includes:
if the phase of the data bit in the target data packet and the phase of the data bit in the first data packet are both the phases of the full low bit or the full high bit, performing phase inversion on the phase of the data bit in the target data packet;
and performing target processing on the target data packet subjected to the phase reversal to enable the target data packet to have target characteristics, wherein the target characteristics represent that the target data packet is a data packet subjected to the phase reversal.
Preferably, the method for performing destination processing on the destination packet subjected to phase inversion includes:
and performing phase enhancement processing on the phases of at least part of the data bits in the target data packet subjected to phase inversion.
Preferably, the method for performing phase enhancement processing on the phase of at least part of the data bits in the phase-inverted target data packet includes:
under the condition that the data bits in the target data packet are all high bits, increasing the phases of at least part of the data bits in the target data packet;
and when the data bits in the target data packet are all low bits, reducing the phases of at least part of the data bits in the target data packet.
In the above method, preferably, after obtaining the target data packet to be transmitted, the method further includes:
and judging whether the phase of the data bit in the target data packet is the phase of the full low bit or the phase of the full high bit, if so, executing the steps of obtaining the phase of the data bit in the first data packet which is transmitted before the target data packet and the subsequent steps, and if not, directly transmitting the target data packet.
In the above method, preferably, after obtaining the phase of the data bit in the first data packet whose transmission is completed before the target data packet, the method further includes:
and judging that the phase of the data bit in the target data packet is the same as the phase of the data bit in the first data packet, executing the following steps of processing the phase of the data bit in the target data packet based on the phase of the data bit in the first data packet, and otherwise, directly transmitting the target data packet.
The present application also provides another data transmission method, including:
receiving a transmitted target data packet, wherein the target data packet comprises a plurality of data bits, and the data bits have phases;
judging whether the target data packet is subjected to phase processing or not, wherein the phase processing comprises the following steps: the target data packet is subjected to phase processing before transmission based on the phase of a data bit in a first data packet which is transmitted before the target data packet;
and under the condition that the target data packet is subjected to phase processing, carrying out phase reduction processing on the target data packet to obtain a phase-reduced target data packet.
Preferably, the method for determining whether the target packet is subjected to phase processing includes:
judging whether the target data packet has a target characteristic, wherein the target characteristic represents that the target data packet is a data packet subjected to phase reversal;
wherein the phase reduction of the target data packet includes:
and eliminating the target characteristics in the target data packet, and performing phase reversal on the phase of the data bits in the target data packet to obtain a target data packet with a restored phase.
Preferably, the method for eliminating the target feature in the target data packet includes:
and performing phase weakening processing on the phase of the data bit with the enhanced phase in the target data packet.
Preferably, the method for performing phase reduction processing on the phase-enhanced data bit in the target data packet includes:
if the data bits in the target data packet are all high bits and have data bits with increased phases, the phases of the data bits with increased phases in the target data packet are reduced to be consistent with the phases of other data bits;
if the data bits in the destination packet are all low and have a phase-reduced data bit, the phase of the phase-reduced data bit in the destination packet is increased to match the phase of the other data bits.
The present application further provides a data transmission apparatus, including:
the target obtaining unit is used for obtaining a target data packet to be transmitted, wherein the target data packet comprises a plurality of data bits, and the data bits have phases;
a phase obtaining unit, configured to obtain a phase of a data bit in a first data packet that is transmitted before the target data packet;
a phase processing unit, configured to process a phase of a data bit in the target data packet based on at least a phase of a data bit in the first data packet;
and the packet transmission unit is used for transmitting the target data packet subjected to the phase processing.
The present application also provides another data transmission apparatus, comprising:
a packet receiving unit, configured to receive a transmitted target data packet, where the target data packet includes a plurality of data bits, and the data bits have phases;
a phase determination unit, configured to determine whether the target data packet is subjected to phase processing, where the phase processing includes: the target data packet is subjected to phase processing before transmission based on the phase of a data bit in a first data packet which is transmitted before the target data packet;
and the packet recovery unit is used for performing phase recovery processing on the target data packet under the condition that the target data packet is subjected to phase processing to obtain a phase-recovered target data packet.
The present application further provides a transmitter comprising:
the transmission processor is used for obtaining a target data packet to be transmitted, wherein the target data packet comprises a plurality of data bits, and the data bits have phases; obtaining the phase of a data bit in a first data packet which is transmitted before the target data packet; processing the phase of the data bit in the target data packet based at least on the phase of the data bit in the first data packet;
and the transmitting interface is used for transmitting the target data packet subjected to the phase processing.
The present application also provides a receiver comprising:
a receiving interface, configured to receive a transmitted target data packet, where the target data packet includes a plurality of data bits, and the data bits have phases;
a receiving processor, configured to determine whether the target data packet is subjected to phase processing, where the phase processing includes: the target data packet is subjected to phase processing before transmission based on the phase of a data bit in a first data packet which is transmitted before the target data packet; and under the condition that the target data packet is subjected to phase processing, carrying out phase reduction processing on the target data packet to obtain a phase-reduced target data packet.
According to the above scheme, for the target data packet to be transmitted, the data transmission method, the data transmission device, the transmitter and the receiver provided by the application can transmit the processed target data packet by acquiring the phase of the data bit in the data packet which is completed by the previous transmission of the target data packet and processing the phase of the data bit in the target data packet based on the phase. Therefore, in the application, when a target data packet is transmitted, phase processing is performed based on the data bit phase of the previously transmitted data packet to distinguish the data packets transmitted before and after, so that the purpose of limiting the stroke length of data transmission is achieved, and a circuit stably works.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a data transmission method according to an embodiment of the present application;
FIGS. 2 and 3 are diagrams illustrating an application example of an embodiment of the present application;
fig. 4 is another flowchart of a data transmission method according to an embodiment of the present application;
fig. 5 is a partial flowchart of a data transmission method according to an embodiment of the present application;
FIGS. 6 and 7 are diagrams of another exemplary application of the embodiment of the present application;
fig. 8 is a flowchart illustrating an implementation of a data transmission method according to a second embodiment of the present application;
FIGS. 9, 10a and 10b are diagrams of another exemplary application of the embodiment of the present application, respectively;
fig. 11 is a schematic structural diagram of a data transmission device according to a third embodiment of the present application;
fig. 12 is a schematic structural diagram of a data transmission device according to a fourth embodiment of the present application;
fig. 13 is a schematic structural diagram of an emitter according to a fifth embodiment of the present application;
fig. 14 is a schematic structural diagram of a receiver according to a sixth embodiment of the present application;
fig. 15-18 are diagrams illustrating other applications of the embodiments of the present application, respectively.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, which is a flowchart illustrating an implementation of a data transmission method according to an embodiment of the present disclosure, the method in this embodiment may be applied to a transmitter of a CDR circuit for data transmission, and is mainly used to limit a run length of data to be transmitted, so as to ensure stability of the circuit, and further, improve efficiency of data transmission on the basis.
In this embodiment, the method may include the steps of:
step 101: and obtaining a target data packet to be transmitted.
The destination packet may include a plurality of data bits, such as D1-Dn shown in fig. 2, each having its own phase, i.e. high and low bits, such as high bit 1 or low bit 0.
It should be noted that the number of data bits in the target packet, i.e. the length of the target packet, is the run length of data transmission in the circuit, and in this embodiment, the target packet is distinguished from the preceding and following packets during transmission, so as to limit the maximum run length as the length of the target packet.
Step 102: the phase of the data bit in the first data packet that is transmitted before the target data packet is obtained.
As shown in fig. 3, a data packet a and a data packet B are transmitted before the target data packet, the data packet a is before the data packet B, the data packet B is a data packet that has just been transmitted, and the data packet a is ordered after the data packet B, that is, the target data packet is ready to start transmission.
It should be noted that the phase of the data bit in the first data packet may be the phase that has been processed, or may be the original phase. The phase of the data bit in the first data packet obtained in this embodiment refers to a final phase exhibited by the data bit in the first data packet after the transmission is completed.
Step 103: and processing the phase of the data bit in the target data packet at least based on the phase of the data bit in the first data packet.
In this embodiment, the phase of the data bit in the target data packet may be processed based on the condition that the phase of the data bit in the first data packet is full high, full low or other phases, and the condition that the phase of the data bit in the target data packet is full high, full low or other phases, so as to obtain the target data packet after the phase processing.
Step 104: and transmitting the target data packet subjected to the phase processing.
For example, in the present embodiment, the phase-processed target data packet is transmitted in the transmitter of the circuit to be transmitted to the receiver.
As can be seen from the foregoing solutions, in the data transmission method provided in this embodiment of the present application, for a target data packet to be transmitted, a phase of a data bit in a data packet that is completed by previous transmission of the target data packet is obtained, and the phase of the data bit in the target data packet is processed based on the phase, so that the processed target data packet is transmitted. It can be seen that, in this embodiment, when a target data packet is transmitted, phase processing is performed based on a data bit phase of a previously transmitted data packet to distinguish the data packets transmitted before and after, so as to achieve the purpose of limiting a stroke length of data transmission and enable a circuit to operate stably, and in this implementation process, additional bits are not required to be added, and all data transmitted is valid data, so that loss of data transmission efficiency is not caused, and thus the purpose of 100% of data transmission efficiency is achieved.
In an implementation manner, after obtaining the target data packet in step 101, the following steps may be further included in this embodiment, as shown in fig. 4:
step 105: judging whether the phase of the data bit in the target data packet is the phase of the full low bit or the full high bit, if the phase of the data bit in the target data packet is not the phase of the full low bit or the full high bit, then the step 102 and the step 103 do not need to be executed, the target data packet can be directly transmitted without causing the extension of the stroke length of data transmission, and if the phase of the data bit in the target data packet is the phase of the full low bit or the full high bit, the step 102 and the subsequent steps can be continuously executed, so that the front data packet and the rear data packet can be distinguished, and the data transmission efficiency can be improved on the basis of limiting the stroke length.
Further, after step 102, the method in this embodiment may further include the following steps, as shown in fig. 4:
step 106: judging whether the phase of the data bit in the target data packet is the same as the phase of the data bit in the first data packet, if so, executing step 103 and subsequent steps to distinguish the target data packet from the first data packet, and then transmitting the target data packet, thereby improving the data transmission efficiency on the basis of limiting the stroke length, and if the phase of the data bit in the target data packet is different from the phase of the data bit in the first data packet, then executing step 103 is not needed, the target data packet is not subjected to phase processing, the target data packet can be directly transmitted, and the stroke length of data transmission can not be prolonged.
In one implementation, step 103 may be implemented in the following manner when implemented specifically, as shown in fig. 5:
step 501: and if the phase of the data bit in the target data packet and the phase of the data bit in the first data packet are both the phases of the full low bit or the full high bit, performing phase inversion on the phase of the data bit in the target data packet.
The phase inversion in the present embodiment means that the phase of all low bits is inverted to the phase of all high bits, or the phase of all high bits is inverted to the phase of all low bits.
Step 502: and processing the target data packet subjected to the phase reversal so that the target data packet has the target characteristic.
The target characteristic can represent that the target data packet is a data packet subjected to phase reversal, so that after the target data packet is transmitted to the receiver, the receiver can accurately restore the target data packet to obtain a restored correct target data packet.
In a specific implementation, the processing of the phase-inverted target data packet in step 502 to make the target data packet have the target characteristic may specifically be implemented as follows:
and performing phase enhancement processing on the phases of at least part of the data bits in the target data packet subjected to phase inversion.
Here, the phase enhancement here means a multi-level phase multi-level in which at least one level is set in the high or low direction for the phase of at least some of the all-high bits or all-low bits.
For example, in the case that the data bits in the target packet are all high bits, the phase of at least some of the data bits in the target packet is increased, as shown in fig. 6, the phases of the data bits D2-D4 in the target packet are increased, and the other data bits D1 and D5-D6 are still high bits relative to the reference line, so that the target packet has multi-level phases;
in the case where the data bits in the destination packet are all low bits, the phase of at least some of the data bits in the destination packet is reduced, as shown in fig. 7, while the phases of the data bits D3-D4 in the destination packet are reduced, and the other data bits D1-D2 and D5-D6 are still low bits, so that the destination packet has a multi-level phase.
It should be noted that the multi-stage phase in the present embodiment is not limited to the two-stage phase, and includes three-stage or even more-stage phase settings.
As can be seen, in this embodiment, by setting multi-level phases to data bits in a target data packet after phase inversion, after a subsequent target data packet is transmitted to a receiver of an opposite party, the receiver can identify a data packet subjected to phase processing based on the multi-level phases, so as to perform reduction processing, and obtain an original correct data packet.
Referring to fig. 8, there is provided a flowchart of an implementation of a data transmission method according to the second embodiment of the present application, where the method is applied to a receiver of a CDR circuit for receiving data, and is mainly used to recover the received data to achieve correct transmission of the data.
In this embodiment, the method may include the steps of:
step 801: and receiving the transmitted target data packet.
Wherein the destination data packet includes a plurality of data bits, as shown in fig. 2.
It should be noted that the number of data bits in the target data packet, i.e., the length of the target data packet, is the run length of data transmission in the circuit, and in this embodiment, it is intended to identify whether the transmitted target data packet has undergone phase processing within the run length, so as to restore the correct target data packet.
Step 802: it is determined whether the target packet has undergone phase processing, and if so, step 803 is performed.
The phase processing in this embodiment means: the target packet is phase processed prior to transmission from the transmitter based on the phase of the data bits in the first packet that were completed prior to the target packet.
Step 803: and carrying out phase reduction packet on the target data packet to obtain a phase-reduced target data packet.
And if the target data packet is judged not to be subjected to the phase processing, the recovery processing is not required, and the transmitted target data packet is the original data packet of the transmitter.
As can be seen from the above solutions, in the data transmission method provided in the second embodiment of the present application, for the transmitted target data packet, whether the target data packet is based on the phase of the data bit in the data packet that is completed by the previous transmission may be determined through phase processing, and then the target data packet that has undergone phase processing may be subjected to phase reduction, so as to obtain a reduced target data packet, and implement correct transmission of data. It can be seen that, in this embodiment, when a target data packet is transmitted, phase processing is performed based on a data bit phase of a previously transmitted data packet to distinguish the data packets transmitted before and after, so as to achieve the purpose of limiting a stroke length of data transmission and enable a circuit to operate stably, and no additional bit needs to be added in the implementation process, and all data transmitted is valid data, so that loss of data transmission efficiency is not caused, and after the data is transmitted to a destination, the data can be restored by judging whether phase processing is performed, so that correct data transmission is achieved while the purpose of 100% data transmission efficiency is achieved.
In one implementation manner, in the present embodiment, when determining whether the target packet is subjected to the phase processing, step 802 may be implemented specifically by:
and judging whether the target data packet has a target characteristic, wherein the target characteristic represents that the target data packet is a data packet subjected to phase inversion.
Specifically, the target characteristic may be that the phase of at least part of the data bits present in the target packet is a multi-level phase, such as an increased phase on a high-order basis, or a decreased phase on a low-order basis, so that there are one-level high-order bits and two-level high-order bits or even more-level low-order bits in the target packet, or there are one-level low-order bits and two-level low-order bits or even more-level low-order bits in the target packet, as shown in fig. 9.
Correspondingly, in this embodiment, when performing phase reduction on the target packet in step 803, the following specific method may be used:
and eliminating target characteristics in the target data packet, for example, eliminating multi-stage phases in the target data packet, and performing phase inversion on phases of data bits in the target data packet to obtain a phase-restored target data packet.
Specifically, the elimination of the target feature in the target data packet can be realized by the following steps:
the phase of the data bit with the enhanced phase in the target data packet is weakened.
For example, in the case where the target packet has all the higher-order bits and has higher-order bits, the higher-order bits of the data bits of D2-D4 in the target packet are reduced in phase to match the other bits, as shown in fig. 10a, and the higher-order bits of D1 and D5-D6 in the target packet are reduced in phase to match the original higher-order bits of the other bits;
in the case where the target packet has all the lower bits and has the phase-reduced data bits, the phase of the phase-reduced data bits in the target packet is increased to coincide with the phase of the other data bits, and as shown in fig. 10b, the lower-level phases of the data bits of D3-D4 than the lower bits in the target packet are reduced to coincide with the original lower bits of the other data bits D1-D2 and D5-D6.
Then, in this embodiment, the target data packet with the multi-level phase removed is subjected to phase inversion again to obtain a restored target data packet.
Referring to fig. 11, a schematic structural diagram of a data transmission apparatus according to a third embodiment of the present invention is provided, where the apparatus is applied to a transmitter of a CDR circuit for data transmission, and is mainly used to limit a run length of data to be transmitted, so as to ensure stability of the circuit, and further improve efficiency of data transmission on the basis.
In this embodiment, the apparatus may include the following functional units:
a target obtaining unit 1101, configured to obtain a target data packet to be transmitted.
The destination packet may include a plurality of data bits, such as D1-Dn shown in fig. 2, each having its own phase, i.e. high and low bits, such as high bit 1 or low bit 0.
It should be noted that the number of data bits in the target packet, i.e. the length of the target packet, is the run length of data transmission in the circuit, and in this embodiment, the target packet is distinguished from the preceding and following packets during transmission, so as to limit the maximum run length as the length of the target packet.
A phase obtaining unit 1102, configured to obtain a phase of a data bit in a first data packet that is transmitted before the target data packet.
As shown in fig. 3, a data packet a and a data packet B are transmitted before the target data packet, the data packet a is before the data packet B, the data packet B is a data packet that has just been transmitted, and the data packet a is ordered after the data packet B, that is, the target data packet is ready to start transmission.
It should be noted that the phase of the data bit in the first data packet may be the phase that has been processed, or may be the original phase. The phase of the data bit in the first data packet obtained in this embodiment refers to a final phase exhibited by the data bit in the first data packet after the transmission is completed.
A phase processing unit 1103, configured to process a phase of a data bit in the target data packet based on at least the phase of the data bit in the first data packet.
In this embodiment, the phase of the data bit in the target data packet may be processed based on the condition that the phase of the data bit in the first data packet is full high, full low or other phases, and the condition that the phase of the data bit in the target data packet is full high, full low or other phases, so as to obtain the target data packet after the phase processing.
And a packet transmission unit 1104 for transmitting the phase-processed target data packet.
For example, in the present embodiment, the phase-processed target data packet is transmitted in the transmitter of the circuit to be transmitted to the receiver.
As can be seen from the above solutions, in the data transmission device provided in the third embodiment of the present application, for a target data packet to be transmitted, a phase of a data bit in a data packet that is completed by previous transmission of the target data packet is obtained, and the phase of the data bit in the target data packet is processed based on the phase, so that the processed target data packet is transmitted. It can be seen that, in this embodiment, when a target data packet is transmitted, phase processing is performed based on a data bit phase of a previously transmitted data packet to distinguish the data packets transmitted before and after, so as to achieve the purpose of limiting a stroke length of data transmission and enable a circuit to operate stably, and in this implementation process, additional bits are not required to be added, and all data transmitted is valid data, so that loss of data transmission efficiency is not caused, and thus the purpose of 100% of data transmission efficiency is achieved.
In one implementation, when the phase processing unit 1103 processes the phase of the data bit in the target data packet based on at least the phase of the data bit in the first data packet, it may implement the following:
if the phase of the data bit in the target data packet and the phase of the data bit in the first data packet are both the phases of the full low bit or the full high bit, performing phase inversion on the phase of the data bit in the target data packet; and performing target processing on the target data packet subjected to the phase reversal to enable the target data packet to have target characteristics, wherein the target characteristics represent that the target data packet is a data packet subjected to the phase reversal.
Correspondingly, the step of performing target processing on the target data packet subjected to phase inversion may specifically be:
performing phase enhancement processing on the phases of at least part of the data bits in the target data packet after the phase inversion, for example, performing enhancement processing on the phases of at least part of the data bits in the target data packet when the data bits in the target data packet are all high bits; and when the data bits in the target data packet are all low bits, reducing the phases of at least part of the data bits in the target data packet.
It should be noted that, for the specific implementation of each unit of the data transmission device in this embodiment, reference may be made to the corresponding content in the foregoing and the accompanying drawings, and detailed description is not provided herein.
Referring to fig. 12, a schematic structural diagram of a data transmission apparatus according to a fourth embodiment of the present invention is provided, where the apparatus is applied to a receiver of a CDR circuit for receiving data, and is mainly used to recover the received data to achieve correct transmission of the data.
In this embodiment, the apparatus may include the following functional units:
a packet receiving unit 1201, configured to receive the transmitted target data packet.
Wherein the destination data packet includes a plurality of data bits, as shown in fig. 2.
It should be noted that the number of data bits in the target data packet, i.e., the length of the target data packet, is the run length of data transmission in the circuit, and in this embodiment, it is intended to identify whether the transmitted target data packet has undergone phase processing within the run length, so as to restore the correct target data packet.
A phase determining unit 1202, configured to determine whether the target data packet is subjected to phase processing, and if so, trigger a packet restoring unit 1203.
The phase processing in this embodiment means: the target packet is phase processed prior to transmission from the transmitter based on the phase of the data bits in the first packet that were completed prior to the target packet.
A packet restoring unit 1203, configured to perform phase restoration processing on the target data packet when the target data packet is subjected to phase processing, so as to obtain a phase-restored target data packet.
And if the target data packet is judged not to be subjected to the phase processing, the recovery processing is not required, and the transmitted target data packet is the original data packet of the transmitter.
As can be seen from the foregoing solutions, in the data transmission device provided in the fourth embodiment of the present application, for a transmitted target data packet, whether the target data packet is based on the phase of the data bit in the data packet that is completed by the previous transmission may be determined through phase processing, and then the phase of the target data packet that has undergone phase processing is restored, so as to obtain a restored target data packet, and implement correct transmission of data. It can be seen that, in this embodiment, when a target data packet is transmitted, phase processing is performed based on a data bit phase of a previously transmitted data packet to distinguish the data packets transmitted before and after, so as to achieve the purpose of limiting a stroke length of data transmission and enable a circuit to operate stably, and no additional bit needs to be added in the implementation process, and all data transmitted is valid data, so that loss of data transmission efficiency is not caused, and after the data is transmitted to a destination, the data can be restored by judging whether phase processing is performed, so that correct data transmission is achieved while the purpose of 100% data transmission efficiency is achieved.
In one implementation manner, when the phase determining unit 1202 determines whether the target packet is subjected to phase processing, specifically, the phase determining unit may:
judging whether the target data packet has a target characteristic, wherein the target characteristic represents that the target data packet is a data packet subjected to phase reversal;
correspondingly, the packet recovery unit 1203 may specifically implement the following method when performing the phase recovery on the target data packet:
and eliminating the target characteristics in the target data packet, and performing phase reversal on the phase of the data bits in the target data packet to obtain a target data packet with a restored phase.
Specifically, the removing the target feature in the target data packet may be:
performing phase reduction processing on the phase-enhanced data bits in the target packet, for example, in the case where the data bits in the target packet are all high and have phase-enhanced data bits, reducing the phase of the phase-enhanced data bits in the target packet to be consistent with the phase of the other data bits; if the data bits in the destination packet are all low and have a phase-reduced data bit, the phase of the phase-reduced data bit in the destination packet is increased to match the phase of the other data bits.
It should be noted that, for the specific implementation of each unit of the data transmission device in this embodiment, reference may be made to the corresponding content in the foregoing and the accompanying drawings, and detailed description is not provided herein.
Referring to fig. 13, a schematic structural diagram of a transmitter provided in the fifth embodiment of the present application, where the transmitter is mainly used to limit a run length of data to be sent so as to ensure stability of a circuit, and further, to improve efficiency of data transmission on this basis, the transmitter specifically includes the following structures:
a transmitting processor 1301, configured to obtain a target data packet to be transmitted, where the target data packet includes multiple data bits, and the data bits have phases; obtaining the phase of a data bit in a first data packet which is transmitted before the target data packet; and processing the phase of the data bit in the target data packet at least based on the phase of the data bit in the first data packet.
And a transmitting interface 1302, configured to transmit the phase-processed target data packet.
The transmit interface 1302 may be a circuit interface for transmitting the target data packet to a receiver in the circuit.
As can be seen from the above solutions, in the transmitter provided in the fifth embodiment of the present application, for a target data packet to be transmitted, a phase of a data bit in a data packet that is completed by previous transmission of the target data packet is obtained, and the phase of the data bit in the target data packet is processed based on the phase, so that the processed target data packet is transmitted. It can be seen that, in this embodiment, when a target data packet is transmitted, phase processing is performed based on a data bit phase of a previously transmitted data packet to distinguish the data packets transmitted before and after, so as to achieve the purpose of limiting a stroke length of data transmission and enable a circuit to operate stably, and in this implementation process, additional bits are not required to be added, and all data transmitted is valid data, so that loss of data transmission efficiency is not caused, and thus the purpose of 100% of data transmission efficiency is achieved.
In one implementation, the transmit processor 1301 can perform the following operations when processing the phase of the data bit in the target data packet based on at least the phase of the data bit in the first data packet:
if the phase of the data bit in the target data packet and the phase of the data bit in the first data packet are both the phases of the full low bit or the full high bit, performing phase inversion on the phase of the data bit in the target data packet; and performing target processing on the target data packet subjected to the phase reversal to enable the target data packet to have target characteristics, wherein the target characteristics represent that the target data packet is a data packet subjected to the phase reversal.
Correspondingly, the step of performing target processing on the target data packet subjected to phase inversion may specifically be:
performing phase enhancement processing on the phases of at least part of the data bits in the target data packet after the phase inversion, for example, performing enhancement processing on the phases of at least part of the data bits in the target data packet when the data bits in the target data packet are all high bits; and when the data bits in the target data packet are all low bits, reducing the phases of at least part of the data bits in the target data packet.
It should be noted that, the specific implementation manner of each structure of the transmitter in the present embodiment can refer to the corresponding content in the foregoing and the accompanying drawings, and will not be described in detail herein.
Referring to fig. 14, a schematic structural diagram of a receiver according to a sixth embodiment of the present application, where the receiver is mainly used to restore received data to achieve correct transmission of the data, and specifically includes the following structures:
a receiving interface 1401, configured to receive a transmitted target data packet, where the target data packet includes a plurality of data bits, and the data bits have phases.
A receiving processor 1402, configured to determine whether the target data packet is subjected to phase processing, where the phase processing includes: the target data packet is subjected to phase processing before transmission based on the phase of a data bit in a first data packet which is transmitted before the target data packet; and under the condition that the target data packet is subjected to phase processing, carrying out phase reduction processing on the target data packet to obtain a phase-reduced target data packet.
As can be seen from the above solutions, in the receiver provided in the sixth embodiment of the present application, for a transmitted target data packet, whether the target data packet is based on the phase of the data bit in the data packet that is completed by the previous transmission is determined through phase processing, and then the target data packet that has undergone phase processing is phase-restored, so as to obtain a restored target data packet, and implement correct transmission of data. It can be seen that, in this embodiment, when a target data packet is transmitted, phase processing is performed based on a data bit phase of a previously transmitted data packet to distinguish the data packets transmitted before and after, so as to achieve the purpose of limiting a stroke length of data transmission and enable a circuit to operate stably, and no additional bit needs to be added in the implementation process, and all data transmitted is valid data, so that loss of data transmission efficiency is not caused, and after the data is transmitted to a destination, the data can be restored by judging whether phase processing is performed, so that correct data transmission is achieved while the purpose of 100% data transmission efficiency is achieved.
In one implementation, when determining whether the target data packet is subjected to phase processing, the receiving processor 1402 specifically may:
judging whether the target data packet has a target characteristic, wherein the target characteristic represents that the target data packet is a data packet subjected to phase reversal;
accordingly, the phase restoration of the target data packet by the receiving processor 1402 may be specifically implemented by:
and eliminating the target characteristics in the target data packet, and performing phase reversal on the phase of the data bits in the target data packet to obtain a target data packet with a restored phase.
Specifically, the removing the target feature in the target data packet may be:
performing phase reduction processing on the phase-enhanced data bits in the target packet, for example, in the case where the data bits in the target packet are all high and have phase-enhanced data bits, reducing the phase of the phase-enhanced data bits in the target packet to be consistent with the phase of the other data bits; if the data bits in the destination packet are all low and have a phase-reduced data bit, the phase of the phase-reduced data bit in the destination packet is increased to match the phase of the other data bits.
It should be noted that, the detailed implementation of each structure of the receiver in the present embodiment can refer to the corresponding content in the foregoing and the accompanying drawings, and will not be described in detail herein.
The following illustrates a specific implementation of the present embodiment for transmitting data (data packets) between the TX transmitter (transmitter) and the RX receiver (receiver):
first, in this embodiment, each data packet (T) transmitted in sequence is determined, and if the (N-2) th T (transmission time of data of run length) of the transmission data is random data (non-all high and non-all low), the data signal may be transmitted from Tx to Rx without any processing.
If the (N-1) th T of the transmission data is different from the (N-2) th T and is data of all high or all low, the data signal can be transmitted from the Tx to the Rx without any processing.
If the data transmitted by the (N) th T is random data of opposite phase of the (N-1) T data or all high or all low data of opposite phase, no processing is needed.
However, if data continuously transmits the same phase data in 2T periods of (N-1) T and (N) T, and the 2T data cause run-length (causing a problem in CDR circuit characteristics), it is necessary to perform inversion processing and multi-level transmission when transmitting (N) T data.
As shown in fig. 15, the cases 1-case4 are schematic diagrams of phase processing during normal data transmission of (N-2) th T, (N-1) th T and (N) th T, respectively, where data of the (N-2) th T is not all 0 and not all 1, data of the (N-1) th T is all 0(case1 and case3), data of the (N) th T is all 1, normal data is raw data, and deployed data is phase-processed data, and thus it can be seen that signals transmitted by multi-level and data of the same phase as all high data or all low data do not cause distortion problem and transmission efficiency of data is not lost. In order to detect Multi-level, in this embodiment, 2 comparison circuits for detecting Multi-level may be added to the receiver, and level detection is performed at a relatively low frequency of 1/N, so that the increase in consumed current and size is small.
As shown in fig. 16, on the Tx side, data transfer of Tx to Rx is ready after the initialization process is finished after Power on. If the (N) th and (N +1) th T are all high or all low, the data transmitted by the (N +1) th T needs to be inverted, and a multi-level signal is added after the data of the (N) th T is transmitted together. In the same way, the data of (N +2) T is supplemented and determined to be finally output after 3 packets of information are confirmed.
As shown by the original Tx _ org and Tx _ out in case1 and case2 shown in fig. 17. Case1 (Case 1) is a transfer example of Tx _ out when the same data is transferred for consecutive 3T times, Case2 is a transfer example of Tx _ out when the same data is transferred for consecutive 2T times, and inverted data is transferred for 1T time. REF +, REF-are two voltage reference signals that examine the level in Rx.
Correspondingly, on the Rx side, as shown in fig. 18, data reception is started after Power on and initialization, and if the received data has a multi-level signal, all high or all low data of the corresponding T is inverted, so that the original data can be restored.
It can be seen that in a circuit, a long run-length maintaining time causes CDR circuit characteristic problems, and a scheme for limiting the maximum run-length is required to keep the circuit stable. In the conventional scheme, an additional bit overhead bit is added to the original bit number, so that the transmission efficiency is reduced. The multi-level scheme mentioned in this embodiment enables the RX to receive an accurate data signal without an additional bit increase. Run-length is restricted by performing inversion transfer of the second Tdata in the case where more than two Ts successively transfer the same phase. Because the information of the signal transmitted through the inversion process is opposite to the information originally intended to be transmitted, the information received by the RX is erroneous. Therefore, in the present embodiment, the second T is subjected to the multi-level process simultaneously with the inversion process, and when receiving the multi-level processed information, RX knows that the information is inverted information, and then inverts the information to receive the same data as the original transmission data.
It should be noted that, the multi-level mentioned in this application may not only be applicable to the case of a data signal all high or all low, but also may use the above multi-level scheme to process the data signal in the circuit in any mode (pattern) that affects the stable operation of the circuit, so as to achieve the corresponding purpose.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above detailed description of the data transmission method, apparatus, transmitter and receiver provided in the present application enables those skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method of data transmission, comprising:
obtaining a target data packet to be transmitted, wherein the target data packet comprises a plurality of data bits, and the data bits have phases;
obtaining the phase of a data bit in a first data packet which is transmitted before the target data packet;
processing the phase of the data bit in the target data packet based at least on the phase of the data bit in the first data packet;
transmitting the target data packet subjected to the phase processing;
the processing the phase of the data bit in the target data packet based on at least the phase of the data bit in the first data packet comprises:
if the phase of the data bit in the target data packet and the phase of the data bit in the first data packet are both the phases of the full low bit or the full high bit, performing phase inversion on the phase of the data bit in the target data packet;
and performing target processing on the target data packet subjected to the phase reversal to enable the target data packet to have target characteristics, wherein the target characteristics represent that the target data packet is a data packet subjected to the phase reversal.
2. The method of claim 1, wherein the performing the target processing on the phase-inverted target packet comprises:
and performing phase enhancement processing on the phases of at least part of the data bits in the target data packet subjected to phase inversion.
3. The method of claim 2, wherein performing phase enhancement processing on the phase of at least a portion of the data bits in the phase-inverted target data packet comprises:
under the condition that the data bits in the target data packet are all high bits, increasing the phases of at least part of the data bits in the target data packet;
and when the data bits in the target data packet are all low bits, reducing the phases of at least part of the data bits in the target data packet.
4. A method of data transmission, comprising:
receiving a transmitted target data packet, wherein the target data packet comprises a plurality of data bits, and the data bits have phases;
judging whether the target data packet is subjected to phase processing or not, wherein the phase processing comprises the following steps: the target data packet is subjected to phase processing before transmission based on the phase of a data bit in a first data packet which is transmitted before the target data packet;
under the condition that the target data packet is subjected to phase processing, carrying out phase reduction processing on the target data packet to obtain a phase-reduced target data packet;
the determining whether the target data packet is subjected to phase processing includes:
judging whether the target data packet has a target characteristic, wherein the target characteristic represents that the target data packet is a data packet subjected to phase reversal;
wherein the phase reduction of the target data packet includes:
and eliminating the target characteristics in the target data packet, and performing phase reversal on the phase of the data bits in the target data packet to obtain a target data packet with a restored phase.
5. The method of claim 4, wherein removing the destination characteristic from the destination packet comprises:
and performing phase weakening processing on the phase of the data bit with the enhanced phase in the target data packet.
6. The method of claim 5, wherein performing phase reduction on the phase-enhanced data bits in the destination data packet comprises:
if the data bits in the target data packet are all high bits and have data bits with increased phases, the phases of the data bits with increased phases in the target data packet are reduced to be consistent with the phases of other data bits;
if the data bits in the destination packet are all low and have a phase-reduced data bit, the phase of the phase-reduced data bit in the destination packet is increased to match the phase of the other data bits.
7. A data transmission apparatus, comprising:
the target obtaining unit is used for obtaining a target data packet to be transmitted, wherein the target data packet comprises a plurality of data bits, and the data bits have phases;
a phase obtaining unit, configured to obtain a phase of a data bit in a first data packet that is transmitted before the target data packet;
a phase processing unit, configured to process a phase of a data bit in the target data packet based on at least a phase of a data bit in the first data packet;
a packet transmission unit for transmitting the phase-processed target data packet;
the phase processing unit is specifically configured to:
if the phase of the data bit in the target data packet and the phase of the data bit in the first data packet are both the phases of the full low bit or the full high bit, performing phase inversion on the phase of the data bit in the target data packet;
and performing target processing on the target data packet subjected to the phase reversal to enable the target data packet to have target characteristics, wherein the target characteristics represent that the target data packet is a data packet subjected to the phase reversal.
8. A data transmission apparatus, comprising:
a packet receiving unit, configured to receive a transmitted target data packet, where the target data packet includes a plurality of data bits, and the data bits have phases;
a phase determination unit, configured to determine whether the target data packet is subjected to phase processing, where the phase processing includes: the target data packet is subjected to phase processing before transmission based on the phase of a data bit in a first data packet which is transmitted before the target data packet;
the packet recovery unit is used for performing phase recovery processing on the target data packet under the condition that the target data packet is subjected to phase processing to obtain a phase-recovered target data packet;
the phase determining unit is specifically configured to:
judging whether the target data packet has a target characteristic, wherein the target characteristic represents that the target data packet is a data packet subjected to phase reversal;
the packet restoration unit is specifically configured to:
and eliminating the target characteristics in the target data packet, and performing phase reversal on the phase of the data bits in the target data packet to obtain a target data packet with a restored phase.
9. A transmitter, comprising:
the transmission processor is used for obtaining a target data packet to be transmitted, wherein the target data packet comprises a plurality of data bits, and the data bits have phases; obtaining the phase of a data bit in a first data packet which is transmitted before the target data packet; processing the phase of the data bit in the target data packet based at least on the phase of the data bit in the first data packet;
the transmitting interface is used for transmitting the target data packet subjected to the phase processing;
when the transmission processor processes the phase of the data bit in the target data packet based on at least the phase of the data bit in the first data packet, the transmission processor is specifically configured to:
if the phase of the data bit in the target data packet and the phase of the data bit in the first data packet are both the phases of the full low bit or the full high bit, performing phase inversion on the phase of the data bit in the target data packet; and performing target processing on the target data packet subjected to the phase reversal to enable the target data packet to have target characteristics, wherein the target characteristics represent that the target data packet is a data packet subjected to the phase reversal.
10. A receiver, comprising:
a receiving interface, configured to receive a transmitted target data packet, where the target data packet includes a plurality of data bits, and the data bits have phases;
a receiving processor, configured to determine whether the target data packet is subjected to phase processing, where the phase processing includes: the target data packet is subjected to phase processing before transmission based on the phase of a data bit in a first data packet which is transmitted before the target data packet; under the condition that the target data packet is subjected to phase processing, carrying out phase reduction processing on the target data packet to obtain a phase-reduced target data packet;
when determining whether the target data packet is subjected to phase processing, the receiving processor is specifically configured to:
judging whether the target data packet has a target characteristic, wherein the target characteristic represents that the target data packet is a data packet subjected to phase reversal;
when the receiving processor performs the phase restoration processing on the target data packet, the receiving processor is specifically configured to:
and eliminating the target characteristics in the target data packet, and performing phase reversal on the phase of the data bits in the target data packet to obtain a target data packet with a restored phase.
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