CN116614123B - Differential pair circuit, signal transmission method thereof and display panel - Google Patents
Differential pair circuit, signal transmission method thereof and display panel Download PDFInfo
- Publication number
- CN116614123B CN116614123B CN202310608814.2A CN202310608814A CN116614123B CN 116614123 B CN116614123 B CN 116614123B CN 202310608814 A CN202310608814 A CN 202310608814A CN 116614123 B CN116614123 B CN 116614123B
- Authority
- CN
- China
- Prior art keywords
- triode
- target
- turning
- logic value
- transmitted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 46
- 230000008054 signal transmission Effects 0.000 title claims abstract description 18
- 238000009825 accumulation Methods 0.000 abstract description 15
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 description 11
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 description 11
- 238000010586 diagram Methods 0.000 description 8
- 230000009467 reduction Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 101100350185 Caenorhabditis elegans odd-1 gene Proteins 0.000 description 1
- 101000860173 Myxococcus xanthus C-factor Proteins 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 230000036541 health Effects 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Abstract
The application relates to a differential pair circuit, a signal transmission method thereof and a display panel, wherein the differential circuit comprises: the signal transmitting circuit comprises a first differential circuit, a second differential circuit, a first triode, a second triode, a third triode and a fourth triode; the collector electrodes of the first triode and the second triode are connected in parallel and then connected with a first differential circuit, and the VDD of the emitter electrode of the first triode is not equal to the VDD of the emitter electrode of the second triode; the collector electrodes of the third triode and the fourth triode are connected in parallel and then connected with a second differential circuit, and the VSS of the emitter electrode of the second triode is not equal to the VSS of the emitter electrode of the fourth triode. The differential circuit provided by the application can shorten the duration of the same voltage waveform, so that energy accumulation is weakened, and EMI is reduced.
Description
Technical Field
The present application relates to the field of circuits, and in particular, to a differential pair circuit, a signal transmission method thereof, and a display panel.
Background
Electromagnetic interference (Electromagnetic Interference, EMI) once exceeds the human acceptable limits can cause injury to human health, and for equipment, electromagnetic interference can detract from the inherent electronic equipment operating performance or can bring significant disaster consequences, even damage to highly sensitive components. Thus, for electronics, EMI must be regulated; for high frequency digital signal transmission, the logic value of "0" or "1" is used. However, for the hardware circuit, a differential pair circuit is generally adopted, and as shown in FIG. 1, the front-end transmission section is provided with 4 switches (reference numerals 1,2,3 and 4), 1 voltage VDD and 1 voltage VSS, and 2 control signals A and 2 control signals VSS of opposite polaritiesThe rear end receiving part comprises 1 resistor and a receiver; when a is high, switches 2 and 3 are open and switches 1 and 4 are closed; at the moment, the current is from VDD to 2 to resistors R to 3 to VSS, the receiver receives the high and low voltage of R, and the data is '1'; conversely, it is "0". For continuous '0' or '1' to be output, the differential pair circuit in the prior art can only output continuous '0' or '1' in sequence; the data currently transmitted is 2 consecutive "1 s", as shown in fig. 2. However, too many "0" s or too many "1" s may cause the energy accumulation to be severe, thereby causing EMI to exceed the standard.
There is currently no effective solution to the above-described problems in the related art.
Disclosure of Invention
The application provides a differential pair circuit, a signal transmission method thereof and a display panel, which are used for solving the problem that the differential pair circuit in the prior art can only output 0 or 1 continuously according to sequence, so that energy accumulation is serious and EMI exceeds standard.
In a first aspect, the present application provides a differential pair circuit, where the differential pair circuit includes a signal transmitting circuit, and a signal receiving circuit connected to the signal transmitting circuit, and the signal transmitting circuit includes a first differential circuit, a second differential circuit, a first triode, a second triode, a third triode, and a fourth triode; the first differential circuit and the second differential circuit respectively comprise 2 triodes, and the 2 triodes are used for inputting control signals with opposite polarities; the first triode and the second triode are used for inputting control signals with opposite polarities, and the third triode and the fourth triode are also used for inputting control signals with opposite polarities; the collector electrodes of the first triode and the second triode are connected in parallel and then connected with the first differential circuit, and the VDD of the emitter electrode of the first triode is not equal to the VDD of the emitter electrode of the second triode; and the third triode is connected with the second differential circuit after being connected with the collector electrode of the fourth triode in parallel, and the VSS of the emitter electrode of the second triode is not equal to the VSS of the emitter electrode of the fourth triode.
In a second aspect, the present application provides a signal transmission method based on the differential pair circuit of the first aspect, including: determining the value of a plurality of continuous identical logical values under the condition that the logical value corresponding to the current signal to be transmitted is the plurality of continuous identical logical values; starting the triodes of the same polarity corresponding to the value in the first differential circuit and the second differential circuit, and closing the triodes of the first differential circuit and the second differential circuit, which have opposite polarities to the started triodes; starting the first target triode and the second target triode under the condition that the logic value to be transmitted currently is the 2N-1 logic value in the plurality of continuous identical logic values; starting the first target triode and the third target triode under the condition that the logic value to be transmitted currently is the 2N logic value in the plurality of continuous identical logic values; wherein, in the case that the first target triode is one of the third triode and the fourth triode, the second target triode and the third target triode are one of the first triode and the second triode and are different from each other; and under the condition that the first target triode is one of the first triode and the second triode, the second target triode and the third target triode are one of the third triode and the fourth triode and are different from each other.
In a third aspect, a display panel is provided, including the differential pair circuit of the first aspect.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages:
According to the differential pair circuit in the embodiment of the application, when a plurality of continuous identical logic values are required to be transmitted, under the condition that the states of other triodes are unchanged, as the input voltages VDD of the first triode and the second triode are unequal, different voltage waveforms of the same logic value in a continuous time period are realized by changing the states of the first triode and the second triode. The input voltages VSS of the third triode and the fourth triode are unequal, so that different voltage waveforms of the same logic value in a continuous time period can be realized by changing the states of the third triode and the fourth triode, the duration of the same voltage waveform is shortened, energy accumulation is weakened, and EMI is reduced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a schematic diagram of a differential pair circuit in the prior art;
FIG. 2 is a schematic diagram of signal transmission based on a conventional differential pair circuit;
Fig. 3 is a schematic diagram of a differential pair circuit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of signal transmission based on a differential pair circuit according to an embodiment of the present application;
Fig. 5 is a flow chart of a signal transmission method based on the differential pair circuit according to an embodiment of the application;
FIG. 6 is a schematic diagram of states of components in a differential pair circuit according to an embodiment of the present application;
FIG. 7 is a second schematic diagram of the status of each component in the differential pair circuit according to the embodiment of the present application;
FIG. 8 is a third schematic diagram of the status of each component in the differential pair circuit according to the embodiment of the present application;
FIG. 9 is a diagram illustrating states of various devices in a differential pair circuit according to an embodiment of the present application.
The reference numerals in the present application are as follows: r-resistor, VDD-operating voltage, VSS-ground voltage, A andRepresenting 2 control signals of opposite polarity, B andRepresenting 2 control signals of opposite polarity, C andThe numbers 1 to 8 represent the corresponding switches, representing 2 control signals of opposite polarity.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The application provides a differential pair circuit, as shown in fig. 3, the differential pair circuit comprises a signal transmitting circuit and a signal receiving circuit connected with the signal transmitting circuit, wherein the signal transmitting circuit comprises a first differential circuit (comprising a triode 1 and a triode 2), a second differential circuit (comprising a triode 3 and a triode 4), a first triode (a triode 5), a second triode (a triode 6), a third triode (a triode 7) and a fourth triode (a triode 8);
Wherein the first differential circuit and the second differential circuit respectively comprise 2 triodes, and the 2 triodes are used for inputting control signals (A and A ) ; The first triode and the second triode are used for inputting control signals (B and B) And the third triode and the fourth triode are also used for inputting control signals (C and C)；
The collector electrodes of the first triode and the second triode are connected in parallel and then connected with a first differential circuit, and the VDD of the emitter electrode of the first triode is not equal to the VDD of the emitter electrode of the second triode. The collector electrodes of the third triode and the fourth triode are connected in parallel and then connected with a second differential circuit, and the VSS of the emitter electrode of the second triode is not equal to the VSS of the emitter electrode of the fourth triode.
In the present application, compared to the differential circuit pair in the prior art, the input power supply is newly increased from 1 to 2, in a specific example, VDD1 and VDD2 in fig. 3, and the receiving power supply is newly increased from 1 to 2, in a specific example, VSS1 and VSS2 in fig. 3, and switches are newly added to 2 input power supplies and 2 receiving power supplies, in a specific example, 5/6/7/8 as in fig. 3. And since the voltages of the input power supply are not equal, and the voltages of the receiving power supply are not equal, in a specific example, if VDD1 is greater than VDD2, the logic value to be transmitted currently is 2 consecutive "1", the waveform changes are as shown in fig. 4, and compared with the prior art, although 2 "1" s are transmitted in the present application, the voltages of the 1 st "1" and the second "1" are not the same, but are not as the voltages of 2 "1" s in the prior art. That is, since the voltages of 2 "1" are different in the present application, the duration of VDD2 is shortened, i.e., energy accumulation is weakened, and EMI is reduced.
It should be noted that, the foregoing description is only about 2 consecutive "1", and if the waveforms of the odd number "1" are identical, the waveforms of the even number "1" are identical, that is, the waveforms of the adjacent 2 "1" in the consecutive "1" are different, so as to reduce energy accumulation and reduce EMI.
Of course, fig. 4 is merely illustrative, and in a specific example, VDD1 may be smaller than VDD2, and "1" corresponding to VDD1 may precede "1" corresponding to VVD2, which may be changed according to actual requirements. Further, since VSS1 is not equal to VSS2, the processing is similar to the processing of the consecutive plurality of "0 s" and the consecutive plurality of "1 s", that is, waveforms of adjacent 2 "0 s" among the consecutive plurality of "0 s" are not identical.
In addition, the differential pair circuit in the embodiment of the application can be applied to a display panel, such as an OLED display panel.
The method for transmitting signals based on the differential pair circuit is further explained below with reference to the differential pair circuit in the embodiment of the present application, as shown in fig. 5, the method includes the steps of:
Step 501, determining values of a plurality of consecutive identical logical values under the condition that the logical value corresponding to the current signal to be transmitted is the plurality of consecutive identical logical values;
It should be noted that, in the embodiment of the present application, the logical values are 0 and 1, that is, the plurality of consecutive identical logical values may be a plurality of consecutive 0s or a plurality of consecutive 1 s. For example, one section of the logical values corresponding to the current signal to be transmitted is: 101000011110000111 … …. Of course, the above logical values are merely illustrative, and corresponding settings are required according to the specific situation.
Step 502, turning on the triodes of the same polarity corresponding to the value in the first differential circuit and the second differential circuit, and turning off the triodes of opposite polarities of the turned-on triodes in the first differential circuit and the second differential circuit;
it should be noted that, in the embodiment of the present application, the transistors with control signals of opposite polarities default to the off state when one is turned on, for example, when the signal of B in fig. 3 is high The signal of (2) is low, i.e. the second transistor (transistor 6) is on, the first transistor (transistor 5) is off, and the same is true for other transistors with opposite polarity. Based on this, for turning on the transistors of the same polarity corresponding to the values in the first differential circuit and the second differential circuit in the above step 502, it means to turn on the transistors of the same polarity in the first differential circuit and the second differential circuit, for example, turn on the transistor 2 and the transistor 3, and turn off the transistor 1 and the transistor 4; or the triode 1 and the triode 4 are turned on, and the triode 2 and the triode 3 are turned off.
Step 503, when the current logic value to be transmitted is the 2N-1 logic value of the multiple consecutive identical logic values, turning on the first target triode and the second target triode;
step 504, turning on the first target triode and the third target triode when the current logic value to be transmitted is the 2N logic value in the plurality of continuous identical logic values;
Wherein, under the condition that the first target triode is one of a third triode and a fourth triode, the second target triode and the third target triode are one of the first triode and the second triode and are different from each other; in the case that the first target transistor is one of the first transistor and the second transistor, the second target transistor and the third target transistor are one of the third transistor and the fourth transistor and are different from each other.
In this regard, the second target transistor and the third target transistor being one of the first transistor and the second transistor and being different from each other means that: when the second target triode is the first triode, the third target triode is the second triode, or when the second target triode is the second triode, the third target triode is the first triode. Similar explanations are given for the second and third target transistors being one of the third and fourth transistors and being different from each other.
According to the differential pair circuit in the embodiment of the application, when a plurality of continuous identical logic values are required to be transmitted, under the condition that the states of other triodes are unchanged, as the input voltages VDD of the first triode and the second triode are unequal, different voltage waveforms of the same logic value in a continuous time period are realized by changing the states of the first triode and the second triode. The input voltages VSS of the third triode and the fourth triode are unequal, so that different voltage waveforms of the same logic value in a continuous time period can be realized by changing the states of the third triode and the fourth triode, the duration of the same voltage waveform is shortened, energy accumulation is weakened, and EMI is reduced.
The following explains the transmission signals in the embodiments of the present application in different embodiments.
Example 1
In the case that the logic value to be transmitted currently is the 2N-1 st logic value of the plurality of consecutive identical logic values, the method for turning on the first target transistor and the second target transistor in the step 503 may further include: turning on the fourth triode and turning on the first triode;
If the current plurality of consecutive identical logical values is 1, when the 1 st "1" occurs to be transmitted, as shown in figure 6, The signal is high and the current flows: VDD1 to 5, to 2 to resistors R to 3 to 8 and finally to VSS2, the receiver receives the R voltage up and down, and the data is "1", where x in fig. 6 represents the transistor off, and x in other figures is the same meaning.
For the case that the logic value to be transmitted currently is the 2N-th logic value of the plurality of consecutive identical logic values in the above step 504, the method for turning on the first target transistor and the third target transistor may further include: turning on the fourth triode and turning on the second triode.
In this regard, when 2 "1" s need to be transmitted, as shown in fig. 7, the B/a/C signal is high, the current flows to VDD2 to 5, then to 2 to resistors R to 3 to 8 and finally to VSS2, and the receiver receives the R voltage up and down, and the data is "1". For a subsequent plurality of consecutive identical 1s, the odd 1 is identical to fig. 6 and the even 1 is identical to fig. 7. Since the voltages of VDD1 and VDD2 are not equal, there is no occurrence of multiple consecutive 1s having the same voltage waveform, i.e., decreasing the duration of VDD1 or VDD2, decreasing energy accumulation, and decreasing EMI.
Example 2
In the case that the logic value to be transmitted currently is the 2N-1 st logic value of the plurality of consecutive identical logic values, the method for turning on the first target transistor and the second target transistor in the step 503 may further include: turning on the third triode and turning on the first triode;
For the case that the logic value to be transmitted currently is the 2N-th logic value of the plurality of consecutive identical logic values in the above step 504, the method for turning on the first target transistor and the third target transistor may further include: turning on the third triode and turning on the second triode.
Embodiment 2 differs from embodiment 1 in that in embodiment 1, the fourth transistor is turned on and the third transistor is turned off; in embodiment 2, the third transistor is turned on and the fourth transistor is turned off, i.e. the current flows of the third transistor and the fourth transistor are different, but both are used to transmit the same plurality of consecutive identical logic values, so that the duration of VDD1 or VDD2 can be reduced, and the energy accumulation is reduced to reduce EMI.
Example 3
For the case that the logic value to be transmitted currently is the 2N-1 logic value of the plurality of consecutive identical logic values in the above step 503, the method for turning on the first target transistor and the second target transistor further includes: turning on the third triode and turning on the second triode;
For the case that the logic value to be transmitted currently is the 2N-th logic value of the plurality of consecutive identical logic values in the above step 504, the method for turning on the first target transistor and the third target transistor may further include: turning on the third triode and turning on the first triode.
In both the embodiment 3 and the embodiment 2, the third transistor is turned on, and after the fourth transistor is turned off, the same continuous multiple identical logic values are transmitted by switching the states of the first transistor and the second transistor. Unlike the two, in example 3, the second transistor is turned on for an odd number of logic values, and the first transistor is turned on for an even number of logic values, and example 2 is opposite to example 3. In either case, however, a reduction in the duration of VDD1 or VDD2 can be achieved, reducing energy accumulation and EMI.
Example 4
In the case that the logic value to be transmitted currently is the 2N-1 st logic value of the plurality of consecutive identical logic values, the method for turning on the first target transistor and the second target transistor in the step 503 may further include: turning on the fourth triode and turning on the second triode;
For the case that the logic value to be transmitted currently is the 2N-th logic value of the plurality of consecutive identical logic values in the above step 504, the method for turning on the first target transistor and the third target transistor may further include: turning on the fourth transistor and turning on the first transistor.
In both the embodiment 4 and the embodiment 1, the same continuous multiple identical logic values are transmitted by switching the states of the first transistor and the second transistor after turning on the fourth transistor and turning off the third transistor. Unlike the two, in embodiment 4, the second transistor is turned on for an odd number of logic values, and the first transistor is turned on for an even number of logic values, and embodiment 1 is opposite to embodiment 4. In either case, however, a reduction in the duration of VDD1 or VDD2 can be achieved, reducing energy accumulation and EMI.
Example 5
In the case that the logic value to be transmitted currently is the 2N-1 st logic value of the plurality of consecutive identical logic values, the method for turning on the first target transistor and the second target transistor in the step 503 may further include: turning on the second triode and turning on the third triode;
If the current plurality of consecutive identical logical values is 0, when the 1 st "0" occurs to be transmitted, as shown in figure 8, The signal is high and the current flows: VDD2 to 6, to 1 to resistors R to 4 to 7 and finally to VSS1, the receiver receives the high and low voltages of R, and the data is "0".
For the case that the logic value to be transmitted currently is the 2N-th logic value of the plurality of consecutive identical logic values in the above step 504, the method for turning on the first target transistor and the third target transistor may further include: the second transistor is turned on and the fourth transistor is turned on.
In this regard, when 2 "0" s are present to be transmitted, as shown in figure 9,The signal is high, VDD2 to 6, to 1 to resistors R to 4 to 8 and finally to VSS2, the receiver receives the high up and low voltage R, and the data is "0". For a subsequent plurality of consecutive identical 0 s, the odd number 0 s corresponds to fig. 8 and the even number 0 s corresponds to fig. 9. Because the VSS1 and VSS2 voltages are not equal, there is no occurrence of multiple consecutive 0 s having the same voltage waveform, i.e., reducing the duration of VSS1 or VSS, reducing energy accumulation, and reducing EMI.
Example 6
In the case that the logic value to be transmitted currently is the 2N-1 st logic value of the plurality of consecutive identical logic values, the method for turning on the first target transistor and the second target transistor in the step 503 may further include: turning on the first triode and turning on the third triode;
For the case that the logic value to be transmitted currently is the 2N-th logic value of the plurality of consecutive identical logic values in the above step 504, the method for turning on the first target transistor and the third target transistor may further include: the first transistor is turned on and the fourth transistor is turned on.
Embodiment 5 differs from embodiment 6 in that in embodiment 6, the first transistor is turned on and the second transistor is turned off; in embodiment 5, the second transistor is turned on, and the first transistor is turned off, i.e. the current flows of the two transistors are different, but both are used to transmit the same plurality of consecutive identical logic values, so that the duration of VDD1 or VDD2 can be reduced, and the energy accumulation is reduced, thereby reducing EMI.
Example 7
In the case that the logic value to be transmitted currently is the 2N-1 st logic value of the plurality of consecutive identical logic values, the method for turning on the first target transistor and the second target transistor in the step 503 may further include: turning on the first triode and turning on the fourth triode;
For the case that the logic value to be transmitted currently is the 2N-th logic value of the plurality of consecutive identical logic values in the above step 504, the method for turning on the first target transistor and the third target transistor may further include: the first transistor is turned on and the third transistor is turned on.
In both the embodiment 6 and the embodiment 7, the same logic values are continuously transmitted by switching the states of the third transistor and the fourth transistor after the first transistor is turned on and the second transistor is turned off. The difference is that in example 6, the third transistor is turned on for an odd number of logic values and the fourth transistor is turned on for an even number of logic values, and example 7 is opposite to example 3. In either case, however, a reduction in the duration of VSS1 or VSS2 can be achieved, reducing energy accumulation and reducing EMI.
Example 8
In the case that the logic value to be transmitted currently is the 2N-1 st logic value of the plurality of consecutive identical logic values, the method for turning on the first target transistor and the second target transistor in the step 503 may further include: turning on the second triode and turning on the fourth triode;
For the case that the logic value to be transmitted currently is the 2N-th logic value of the plurality of consecutive identical logic values in the above step 504, the method for turning on the first target transistor and the third target transistor may further include: the second triode is turned on and the third triode is turned on.
In both the embodiment 8 and the embodiment 5, the second transistor is turned on, and after the first transistor is turned off, the same continuous multiple identical logic values are transmitted by switching the states of the third transistor and the fourth transistor. Unlike the above, in example 8, the fourth transistor is turned on for an odd number of logic values, and the third transistor is turned on for an even number of logic values, and example 5 is opposite to example 8. In either case, however, a reduction in the duration of VSS1 or VSS2 can be achieved, reducing energy accumulation and reducing EMI.
It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising 1, … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. The differential pair circuit is characterized by comprising a signal transmitting circuit and a signal receiving circuit connected with the signal transmitting circuit, wherein the signal transmitting circuit comprises a first differential circuit, a second differential circuit, a first triode, a second triode, a third triode and a fourth triode;
The first differential circuit and the second differential circuit respectively comprise 2 triodes, and the 2 triodes are used for inputting control signals with opposite polarities; the first triode and the second triode are used for inputting control signals with opposite polarities, and the third triode and the fourth triode are also used for inputting control signals with opposite polarities;
the first triode is connected with the first differential circuit after being connected with the collector electrode of the second triode in parallel, and the working voltage VDD of the emitter electrode of the first triode is not equal to the VDD of the emitter electrode of the second triode;
And the third triode is connected with the second differential circuit after being connected with the collector electrode of the fourth triode in parallel, and the voltage VSS of the grounding terminal of the emitter electrode of the second triode is not equal to the VSS of the emitter electrode of the fourth triode.
2. The signal transmission method based on the differential pair circuit as claimed in claim 1, comprising:
Determining the value of a plurality of continuous identical logical values under the condition that the logical value corresponding to the current signal to be transmitted is the plurality of continuous identical logical values;
Starting the triodes of the same polarity corresponding to the value in the first differential circuit and the second differential circuit, and closing the triodes of the first differential circuit and the second differential circuit, which have opposite polarities to the started triodes;
Starting the first target triode and the second target triode under the condition that the logic value to be transmitted currently is the 2N-1 logic value in the plurality of continuous identical logic values;
starting the first target triode and the third target triode under the condition that the logic value to be transmitted currently is the 2N logic value in the plurality of continuous identical logic values;
wherein, in the case that the first target triode is one of the third triode and the fourth triode, the second target triode and the third target triode are one of the first triode and the second triode and are different from each other;
And under the condition that the first target triode is one of the first triode and the second triode, the second target triode and the third target triode are one of the third triode and the fourth triode and are different from each other.
3. The method of signal transmission for a differential pair circuit according to claim 2, wherein,
And turning on the first target triode and the second target triode under the condition that the logic value to be transmitted is the 2N-1 logic value in the plurality of continuous identical logic values, wherein the method comprises the following steps: turning on the third triode and turning on the first triode;
and turning on the first and third target transistors in case that the logic value to be transmitted is the 2N-th logic value among the plurality of consecutive identical logic values, including: and starting the third triode and starting the second triode.
4. The method of signal transmission for a differential pair circuit according to claim 2, wherein,
And turning on the first target triode and the second target triode under the condition that the logic value to be transmitted is the 2N-1 logic value in the plurality of continuous identical logic values, wherein the method comprises the following steps: turning on the fourth triode and turning on the first triode;
And turning on the first and third target transistors in case that the logic value to be transmitted is the 2N-th logic value among the plurality of consecutive identical logic values, including: and starting the fourth triode and starting the second triode.
5. The method of signal transmission for a differential pair circuit according to claim 2, wherein,
And turning on the first target triode and the second target triode under the condition that the logic value to be transmitted is the 2N-1 logic value in the plurality of continuous identical logic values, wherein the method comprises the following steps: turning on the third triode and turning on the second triode;
And turning on the first and third target transistors in case that the logic value to be transmitted is the 2N-th logic value among the plurality of consecutive identical logic values, including: and starting the third triode and starting the first triode.
6. The method of signal transmission for a differential pair circuit according to claim 2, wherein,
And turning on the first target triode and the second target triode under the condition that the logic value to be transmitted is the 2N-1 logic value in the plurality of continuous identical logic values, wherein the method comprises the following steps: turning on the fourth triode and turning on the second triode;
And turning on the first and third target transistors in case that the logic value to be transmitted is the 2N-th logic value among the plurality of consecutive identical logic values, including: and starting the fourth triode and starting the first triode.
7. The method of signal transmission for a differential pair circuit according to claim 2, wherein,
And turning on the first target triode and the second target triode under the condition that the logic value to be transmitted is the 2N-1 logic value in the plurality of continuous identical logic values, wherein the method comprises the following steps: turning on the first triode and turning on the third triode;
and turning on the first and third target transistors in case that the logic value to be transmitted is the 2N-th logic value among the plurality of consecutive identical logic values, including: and starting the first triode and starting the fourth triode.
8. The method of signal transmission for a differential pair circuit according to claim 2, wherein,
And turning on the first target triode and the second target triode under the condition that the logic value to be transmitted is the 2N-1 logic value in the plurality of continuous identical logic values, wherein the method comprises the following steps: turning on the second triode and turning on the third triode;
And turning on the first and third target transistors in case that the logic value to be transmitted is the 2N-th logic value among the plurality of consecutive identical logic values, including: and starting the second triode and starting the fourth triode.
9. The method of signal transmission for a differential pair circuit according to claim 2, wherein,
And turning on the first target triode and the second target triode under the condition that the logic value to be transmitted is the 2N-1 logic value in the plurality of continuous identical logic values, wherein the method comprises the following steps: turning on the first triode and turning on the fourth triode;
and turning on the first and third target transistors in case that the logic value to be transmitted is the 2N-th logic value among the plurality of consecutive identical logic values, including: and starting the first triode and starting the third triode.
10. A display panel comprising the differential pair circuit of claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310608814.2A CN116614123B (en) | 2023-05-25 | Differential pair circuit, signal transmission method thereof and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310608814.2A CN116614123B (en) | 2023-05-25 | Differential pair circuit, signal transmission method thereof and display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116614123A CN116614123A (en) | 2023-08-18 |
| CN116614123B true CN116614123B (en) | 2024-06-28 |
Family
ID=
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103647518A (en) * | 2013-12-01 | 2014-03-19 | 西安电子科技大学 | Adjustable input error amplifier for single-stage power factor correction controller |
| CN109565277A (en) * | 2016-08-30 | 2019-04-02 | 株式会社半导体能源研究所 | Receive receiver, the IC and display device including receiver of differential signal |
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103647518A (en) * | 2013-12-01 | 2014-03-19 | 西安电子科技大学 | Adjustable input error amplifier for single-stage power factor correction controller |
| CN109565277A (en) * | 2016-08-30 | 2019-04-02 | 株式会社半导体能源研究所 | Receive receiver, the IC and display device including receiver of differential signal |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100218506B1 (en) | Level shift circuit for liquid crystal device | |
| US8026891B2 (en) | Flat panel display including transceiver circuit for digital interface | |
| US5365127A (en) | Circuit for conversion from CMOS voltage levels to shifted ECL voltage levels with process compensation | |
| US20090121771A1 (en) | Level shift circuit and method thereof | |
| WO2014124580A1 (en) | Driving circuit and display device of using same | |
| CN111105759B (en) | Shifting register unit and driving method thereof, grid driving circuit and display device | |
| CN114389630A (en) | Hysteresis circuit, receiver and chip | |
| CN116614123B (en) | Differential pair circuit, signal transmission method thereof and display panel | |
| US7449916B2 (en) | Voltage level shift circuit | |
| CN116614123A (en) | Differential pair circuit, signal transmission method thereof and display panel | |
| US7157931B2 (en) | Termination circuits having pull-down and pull-up circuits and related methods | |
| US20170264296A1 (en) | Pre-driver for driving low voltage differential signaling (lvds) driving circuit | |
| US20040080336A1 (en) | Output buffer apparatus capable of adjusting output impedance in synchronization with data signal | |
| CN215577702U (en) | Shifting register unit, grid driving circuit and display panel | |
| CN110896338B (en) | Clock transmission module and network transmission method | |
| CN113744682A (en) | Display chip and electronic equipment | |
| US10305482B2 (en) | Voltage level shifter | |
| US11909394B2 (en) | Level shifter circuit | |
| CN112087225B (en) | Differential clock correction circuit | |
| TWI796841B (en) | Driving device | |
| CN112751549B (en) | High-speed LVDS resistance state control circuit and control method | |
| CN217739897U (en) | High speed serial interface driver for low voltage differential signals | |
| JPH0661836A (en) | Termination circuit and waveform shaping circuit | |
| CN219087122U (en) | Level conversion and isolation circuit | |
| KR100384833B1 (en) | Level shifer with low space |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |