CN219087122U - Level conversion and isolation circuit - Google Patents

Abstract

The application relates to a level conversion and isolation circuit, in particular to the technical field of level conversion. The circuit comprises a first switch unit and a first input unit; in the first switch unit, a first external chip power supply end sequentially passes through a first resistor and a second switch tube to be grounded; the control end of the second switching tube is connected to the first signal switching end; the first external chip power end is also connected to a first node through a first switching tube; the power end of the first external chip is connected to the control end of the first switching tube through a first resistor; in the first input unit, the first node is connected to the control end of the third switching tube through the second resistor; the main chip input pin is connected to the first external chip output pin through a third switch tube; the first node is also connected to the first external chip output pin through a fourth resistor. Based on the circuit, when the level conversion and isolation functions are realized, the circuit has a simple structure and is flexible to control.

Description

Level conversion and isolation circuit

Technical Field

The application relates to the technical field of level conversion, in particular to a level conversion and isolation circuit.

Background

Along with the higher and higher integration level of electronic products, more and more types of electronic products, in actual use, a main chip interface needs to be connected with 2 or more external interface chips, and channel selection and isolation are needed for the external interfaces, otherwise, the situation of level mismatch can occur, signal transmission errors are caused, and the chips can be damaged in severe cases.

Currently, a level shifting chip is used to channel and isolate the external interface. The level shifting chip may provide different voltages to the input and output signals, respectively, with the shifting being done internally to the chip.

However, the above method is bulky and inflexible when implementing the level shift function.

Disclosure of Invention

The application provides a level conversion and isolation circuit, when realizing level conversion and isolation circuit function, simple structure uses in a flexible way, and this technical scheme is as follows.

There is provided a level shifting and isolating circuit comprising a first switching unit, a first input unit;

in the first switch unit, a first external chip power supply end is grounded through a first resistor R100 and a second switch tube Q30 in sequence; the control end of the second switching tube Q30 is connected to the first signal switching end SWITCH_1;

the first external chip power supply end is also connected to a first node through a first switching tube Q29; the first external chip power supply end is connected to the control end of the first switching tube Q29 through the first resistor R100;

in the first input unit, the first node is connected to the control end of a third switching tube Q27 through a second resistor R94; the main chip input pin uart0_rx is connected to a first external chip output pin uart1_tx through the third switching tube Q27; the first node is further connected to a first external chip output pin uart1_tx through a fourth resistor R96.

In one possible implementation, the circuit further includes a first output unit;

in the first output unit, the first node is connected to the control end of the fourth switching tube Q28 through a fifth resistor R97; the first external chip input pin uart1_rx is connected to the main chip output pin uart0_tx through the fourth switching tube Q28; the first node is further connected to a first external chip input pin uart1_rx through a seventh resistor R99.

In one possible implementation manner, the first switching tube Q29 is a PMOS tube; the second switching tube Q30 is an NMOS tube; the third switching tube Q27 is an NPN triode.

In one possible implementation, the fourth switching transistor Q28 is an NPN transistor.

In a possible implementation manner, the circuit further comprises a second switch unit and a second input unit;

in the second switch unit, a second external chip power supply end is grounded through an eighth resistor R107 and a sixth switch tube Q34 in sequence; the control end of the sixth switching tube Q34 is connected to the second signal switching end SWITCH_2;

the second external chip power supply end is also connected to a second node through a fifth switching tube Q33; the second external chip power supply end is connected to the control end of the fifth switching tube Q33 through the eighth resistor R107;

in the second input unit, the second node is connected to the control end of a seventh switching tube Q31 through a ninth resistor R101; the main chip input pin uart0_rx is connected to the second external chip output pin uart2_tx through the seventh switching tube Q31; the second node is also connected to a second external chip output pin uart2_tx through a tenth resistor R103.

In one possible implementation, the circuit further includes a second output unit;

in the second output unit, the second node is connected to the control end of the eighth switching tube Q32 through an eleventh resistor R104; the second external chip input pin uart2_rx is connected to the main chip output pin uart0_tx through the eighth switching tube Q32; the second node is also connected to a second external chip input pin uart2_rx through a twelfth resistor R106.

In one possible implementation manner, the fifth switching tube Q33 is a PMOS tube; the sixth switching tube Q34 is an NMOS tube; the seventh switching tube Q31 is an NPN triode.

In one possible implementation, the eighth switching transistor Q32 is an NPN transistor.

In one possible implementation, in the first input unit, the main chip power supply terminal is connected to the main chip input pin uart0_rx through a third resistor R95.

In one possible implementation, in the first output unit, the main chip power supply terminal is connected to the main chip output pin uart0_tx through a sixth resistor R98.

The technical scheme that this application provided can include following beneficial effect:

the level conversion and isolation circuit comprises a first switch unit and a first input unit; in the first switch unit, a first external chip power supply end sequentially passes through a first resistor and a second switch tube to be grounded; the control end of the second switching tube is connected to the first signal switching end; the first external chip power end is also connected to a first node through a first switching tube; the power end of the first external chip is connected to the control end of the first switching tube through a first resistor; in the first input unit, the first node is connected to the control end of the third switching tube through the second resistor; the main chip input pin is connected to the first external chip output pin through a third switch tube; the first node is also connected to the first external chip output pin through a fourth resistor. The main chip controls the on-off of the first switching tube and the second switching tube by controlling the level of the first signal switching end, and further controls the communication between the main chip and the first external chip, so that the level conversion and isolation functions are realized. Therefore, the circuit has simple structure and flexible control when realizing the level conversion and isolation functions.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram illustrating a level shifting and isolation circuit according to an exemplary embodiment.

Fig. 2 is a schematic structural diagram of a level shift and isolation circuit according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the utility model are shown. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

Fig. 1 is a schematic diagram illustrating a level shifting and isolation circuit according to an exemplary embodiment. As shown in fig. 1, the circuit includes a first switch unit, a first input unit;

in the first switch unit, a first external chip power supply end is grounded through a first resistor R100 and a second switch tube Q30 in sequence; the control end of the second switching tube Q30 is connected to the first signal switching end SWITCH_1;

the first external chip power supply end is also connected to a first node through a first switch tube Q29; the first external chip power end is connected to the control end of the first switch tube Q29 through the first resistor R100;

in the first input unit, the first node is connected to the control end of the third switching tube Q27 through a second resistor R94; the main chip input pin UART0_RX is connected to the first external chip output pin UART1_TX through the third switch tube Q27; the first node is further connected to a first external chip output pin uart1_tx through a fourth resistor R96.

In one possible implementation, the circuit further includes a first output unit;

in the first output unit, the first node is connected to the control end of the fourth switching tube Q28 through a fifth resistor R97; the first external chip input pin uart1_rx is connected to the main chip output pin uart0_tx through the fourth switching tube Q28; the first node is further connected to a first external chip input pin uart1_rx through a seventh resistor R99.

In one possible implementation manner, the first switching tube Q29 is a PMOS tube; the second switching tube Q30 is an NMOS tube; the third switching transistor Q27 is an NPN transistor.

In one possible implementation, the fourth switching transistor Q28 is an NPN transistor.

In one possible implementation, in the first input unit, the main chip power supply terminal is connected to the main chip input pin uart0_rx through a third resistor R95.

In one possible implementation, in the first output unit, the main chip power supply terminal is connected to the main chip output pin uart0_tx through a sixth resistor R98.

The level shift and isolation circuit shown in fig. 1 operates as follows:

after the circuit is powered on, the main chip can control the level of the first signal SWITCH terminal switch_1. When the level of the first signal SWITCH terminal switch_1 is pulled up by the main chip, the MOS transistor SWITCH formed by the first SWITCH transistor Q29 and the second SWITCH transistor Q30 is turned on, so that the voltage vdd_k1 of the first node is equal to the voltage VDDA of the power terminal of the first external chip, and the voltage of the control terminal of the third SWITCH transistor Q27 and the voltage of the control terminal of the fourth SWITCH transistor Q28 are equal to the voltage VDDA of the power terminal of the first external chip.

At this time, if the voltage of the first external chip output pin uart1_tx (transmitting end) is at a high level, the third switching tube Q27 is turned off, and the voltage of the main chip input pin uart0_rx (receiving end) is pulled up by the third resistor R95 to be equal to the voltage VCC of the main chip power supply end; if the voltage of the first external chip output pin uart1_tx (transmitting end) is at a low level, the third switch Q27 is turned on, and the voltage of the main chip input pin uart0_rx (receiving end) is pulled down to a low level at the same time. Through the above process, the level conversion process of the main chip receiving the first external chip can be completed.

Similarly, if the voltage of the main chip output pin uart0_tx (transmitting end) is at a high level, the fourth switching tube Q28 is turned off, and the voltage of the first external chip input pin uart1_rx (receiving end) is pulled up by the seventh resistor R99 to be equal to the voltage VDDA of the first external chip power supply end; if the voltage of the main chip output pin uart0_tx (transmitting end) is at a low level, the fourth switching tube Q28 is turned on, and the voltage of the first external chip input pin uart1_rx (receiving end) is pulled down to a low level at the same time. Through the above process, the level conversion process of the main chip to the first external chip can be completed.

When the level of the first signal SWITCH end switch_1 is pulled down by the main chip, the MOS transistor SWITCH formed by the first SWITCH tube Q29 and the second SWITCH tube Q30 is turned off, the voltage VDD_K1 of the first node is equal to 0V, the voltage of the control end of the third SWITCH tube Q27 and the voltage of the control end of the fourth SWITCH tube Q28 are both 0V, the third SWITCH tube Q27 and the fourth SWITCH tube Q28 are both turned off, the communication channel between the main chip and the first external chip is turned off, and signals are isolated.

In summary, in the level shift and isolation circuit shown in the present application, the level shift and isolation circuit includes a first switch unit and a first input unit; in the first switch unit, a first external chip power supply end sequentially passes through a first resistor and a second switch tube to be grounded; the control end of the second switching tube is connected to the first signal switching end; the first external chip power end is also connected to a first node through a first switching tube; the power end of the first external chip is connected to the control end of the first switching tube through a first resistor; in the first input unit, the first node is connected to the control end of the third switching tube through the second resistor; the main chip input pin is connected to the first external chip output pin through a third switch tube; the first node is also connected to the first external chip output pin through a fourth resistor. The main chip controls the on-off of the first switching tube and the second switching tube by controlling the level of the first signal switching end, and further controls the communication between the main chip and the first external chip, so that the level conversion and isolation functions are realized. Therefore, the circuit has simple structure and flexible control when realizing the level conversion and isolation functions.

Alternatively, the level shift and isolation circuit may be the structure of fig. 2 based on fig. 1. Fig. 2 is a schematic structural diagram of a level shift and isolation circuit according to an embodiment of the present application. As shown in fig. 2, in a possible implementation manner, the circuit further includes a second switch unit and a second input unit;

in the second switch unit, a second external chip power supply end is grounded through an eighth resistor R107 and a sixth switch tube Q34 in sequence; the control end of the sixth switching tube Q34 is connected to the second signal switching end SWITCH_2;

the second external chip power supply end is also connected to a second node through a fifth switching tube Q33; the second external chip power end is connected to the control end of the fifth switching tube Q33 through the eighth resistor R107;

in the second input unit, the second node is connected to the control end of the seventh switching tube Q31 through a ninth resistor R101; the main chip input pin uart0_rx is connected to the second external chip output pin uart2_tx through the seventh switching tube Q31; the second node is also connected to a second external chip output pin uart2_tx through a tenth resistor R103.

As shown in fig. 2, in one possible implementation, the circuit further includes a second output unit;

in the second output unit, the second node is connected to the control end of the eighth switching tube Q32 through an eleventh resistor R104; the second external chip input pin uart2_rx is connected to the main chip output pin uart0_tx through the eighth switching tube Q32; the second node is also connected to a second external chip input pin uart2_rx through a twelfth resistor R106.

As shown in fig. 2, in one possible implementation, the fifth switching tube Q33 is a PMOS tube; the sixth switching tube Q34 is an NMOS tube; the seventh switching transistor Q31 is an NPN transistor.

In one possible implementation, as shown in fig. 2, the eighth switching transistor Q32 is an NPN transistor.

The level shift and isolation circuit shown in fig. 2 operates as follows:

after the circuit is powered on, the same principle as the main chip can control the level of the first signal SWITCH end SWITCH_1, and the main chip can control the level of the second signal SWITCH end SWITCH_2. When the main chip pulls up the level of the second signal SWITCH terminal switch_2, the MOS transistor SWITCH formed by the fifth SWITCH transistor Q33 and the sixth SWITCH transistor Q34 is turned on, so that the voltage vdd_k2 of the second node is equal to the voltage VDDB of the power terminal of the second external chip, and the voltage of the control terminal of the seventh SWITCH transistor Q31 and the voltage of the control terminal of the eighth SWITCH transistor Q32 are equal to the voltage VDDB of the power terminal of the second external chip.

At this time, if the voltage of the second external chip output pin uart2_tx (transmitting end) is at a high level, the seventh switching tube Q31 is turned off, and the voltage of the main chip input pin uart0_rx (receiving end) is pulled up by the ninth resistor R101 to be equal to the voltage VCC of the main chip power supply end; if the voltage of the second external chip output pin uart2_tx (transmitting end) is at a low level, the seventh switching tube Q31 is turned on, and the voltage of the main chip input pin uart0_rx (receiving end) is pulled down to a low level at the same time. Through the above process, the main chip receiving second external chip level conversion process can be completed.

Similarly, if the voltage of the main chip output pin uart0_tx (transmitting end) is at a high level, the eighth switching tube Q32 is turned off, and the voltage of the second external chip input pin uart2_rx (receiving end) is pulled up by the twelfth resistor R106 to be equal to the voltage VDDB of the second external chip power supply end; if the voltage of the main chip output pin uart0_tx (transmitting end) is at a low level, the eighth switching tube Q32 is turned on, and the voltage of the second external chip input pin uart2_rx (receiving end) is pulled down to a low level at the same time. Through the above process, the level conversion process of the main chip to the second external chip can be completed.

When the level of the second signal SWITCH end switch_2 is pulled down by the main chip, the MOS transistor SWITCH formed by the fifth SWITCH tube Q33 and the sixth SWITCH tube Q34 is turned off, the voltage vdd_k2 of the second node is equal to 0V, the voltage of the control end of the seventh SWITCH tube Q31 and the voltage of the control end of the eighth SWITCH tube Q32 are both 0V, the seventh SWITCH tube Q31 and the eighth SWITCH tube Q32 are both turned off, the communication channel between the main chip and the second external chip is turned off, and the signals are isolated.

Furthermore, the main chip can control the on and off of the MOS tube switch by controlling the level of the signal switch end, thereby realizing the level conversion and isolation functions. The main chip may control the level of the first signal SWITCH terminal switch_1 or the level of the second signal SWITCH terminal switch_2 separately, or may control the level of the first signal SWITCH terminal switch_1 and the level of the second signal SWITCH terminal switch_2 simultaneously if the main chip is simultaneously. If the main chip simultaneously pulls up the level of the first signal SWITCH end SWITCH_1 and the level of the second signal SWITCH end SWITCH_2, the first external chip and the second external chip are simultaneously opened, and the first external chip and the second external chip are in an activated state and can simultaneously receive signals from the main chip; if the main chip pulls down the level of the first signal SWITCH end switch_1 and the level of the second signal SWITCH end switch_2 at the same time, the first external chip and the second external chip are turned off at the same time, the first external chip and the second external chip cannot receive signals from the main chip, the signals are isolated, and the whole circuit is in a low power consumption state.

Alternatively, the resistors in the level shift and isolation circuit may be set according to actual needs. For example, the resistance values of the first resistor R100 and the eighth resistor R107 are set to a larger value, for example, set to 100kΩ, so that the main chip can control the signal switch terminal through a smaller voltage, and further control the state of the entire circuit. For example, the resistance values of the second resistor R94, the fifth resistor R97, the ninth resistor R101, and the eleventh resistor R104 are set to 4.7kΩ, and the resistance values of the third resistor R95, the fourth resistor R96, the sixth resistor R98, the 7 th resistor R99, the tenth resistor R103, and the twelfth resistor R106 are set to 10kΩ.

Optionally, the type of each switch tube in the level conversion and isolation circuit can be selected according to actual needs. For example, the third switching tube Q27, the fourth switching tube Q28, the seventh switching tube Q31, and the eighth switching tube Q32 are 9013 transistors, the first switching tube Q29 and the fifth switching tube Q33 are AO3401, and the second switching tube Q30 and the sixth switching tube Q34 are AO3402.

It should be noted that, by the above structure, the level shift and isolation circuit can realize any high-low level shift between the transmitting end and the receiving end within the bearing range of each switching tube. Since the leakage current between the transmitting end and the receiving end is small (microampere level), the level conversion and isolation circuit can realize power-off isolation between the transmitting end and the receiving end.

Further, other circuit structures capable of realizing the switching function can be selected to replace each switching tube.

Furthermore, the number of the switch units, the input units and the output units can be increased according to actual needs, so that the main chip can control the on-off of the transmitting end and the receiving end between the external chips with a larger number, and the multi-channel level conversion and isolation functions are realized.

In summary, in the level shift and isolation circuit shown in the present application, the level shift and isolation circuit includes a first switch unit and a first input unit; in the first switch unit, a first external chip power supply end sequentially passes through a first resistor and a second switch tube to be grounded; the control end of the second switching tube is connected to the first signal switching end; the first external chip power end is also connected to a first node through a first switching tube; the power end of the first external chip is connected to the control end of the first switching tube through a first resistor; in the first input unit, the first node is connected to the control end of the third switching tube through the second resistor; the main chip input pin is connected to the first external chip output pin through a third switch tube; the first node is also connected to the first external chip output pin through a fourth resistor. The main chip controls the on-off of the first switching tube and the second switching tube by controlling the level of the first signal switching end, and further controls the communication between the main chip and the first external chip, so that the level conversion and isolation functions are realized. Therefore, the circuit has simple structure and flexible control when realizing the level conversion and isolation functions.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the utility model disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (10)

1. The level conversion and isolation circuit is characterized by comprising a first switch unit and a first input unit;

in the first switch unit, a first external chip power supply end is grounded through a first resistor R100 and a second switch tube Q30 in sequence; the control end of the second switching tube Q30 is connected to the first signal switching end SWITCH_1;

the first external chip power supply end is also connected to a first node VDD_K1 through a first switching tube Q29; the first external chip power supply end is connected to the control end of the first switching tube Q29 through the first resistor R100;

in the first input unit, the first node vdd_k1 is connected to a control terminal of a third switching tube Q27 through a second resistor R94; the main chip input pin uart0_rx is connected to a first external chip output pin uart1_tx through the third switching tube Q27; the first node vdd_k1 is further connected to a first external chip output pin uart1_tx through a fourth resistor R96.

2. The circuit of claim 1, further comprising a first output unit;

in the first output unit, the first node vdd_k1 is connected to the control terminal of the fourth switching tube Q28 through a fifth resistor R97; the first external chip input pin uart1_rx is connected to the main chip output pin uart0_tx through the fourth switching tube Q28; the first node vdd_k1 is further connected to a first external chip input pin uart1_rx through a seventh resistor R99.

3. The circuit of claim 1, wherein the first switching tube Q29 is a PMOS tube; the second switching tube Q30 is an NMOS tube; the third switching tube Q27 is an NPN triode.

4. The circuit of claim 2, wherein the fourth switching transistor Q28 is an NPN transistor.

5. The circuit of claim 1, further comprising a second switching unit, a second input unit;

in the second switch unit, a second external chip power supply end is grounded through an eighth resistor R107 and a sixth switch tube Q34 in sequence; the control end of the sixth switching tube Q34 is connected to the second signal switching end SWITCH_2;

the second external chip power supply end is also connected to a second node through a fifth switching tube Q33; the second external chip power supply end is connected to the control end of the fifth switching tube Q33 through the eighth resistor R107;

in the second input unit, the second node is connected to the control end of a seventh switching tube Q31 through a ninth resistor R101; the main chip input pin uart0_rx is connected to the second external chip output pin uart2_tx through the seventh switching tube Q31; the second node is also connected to a second external chip output pin uart2_tx through a tenth resistor R103.

6. The circuit of claim 5, further comprising a second output unit;

in the second output unit, the second node is connected to the control end of the eighth switching tube Q32 through an eleventh resistor R104; the second external chip input pin uart2_rx is connected to the main chip output pin uart0_tx through the eighth switching tube Q32; the second node is also connected to a second external chip input pin uart2_rx through a twelfth resistor R106.

7. The circuit of claim 5, wherein the fifth switching tube Q33 is a PMOS tube; the sixth switching tube Q34 is an NMOS tube; the seventh switching tube Q31 is an NPN triode.

8. The circuit of claim 6, wherein the eighth switching transistor Q32 is an NPN transistor.

9. The circuit of claim 1, wherein in the first input unit, a main chip power supply terminal is connected to a main chip input pin uart0_rx through a third resistor R95.

10. The circuit of claim 2, wherein in the first output unit, a main chip power supply terminal is connected to a main chip output pin uart0_tx through a sixth resistor R98.

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