CN116611528B - Quantum computing device - Google Patents
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- CN116611528B CN116611528B CN202310518371.8A CN202310518371A CN116611528B CN 116611528 B CN116611528 B CN 116611528B CN 202310518371 A CN202310518371 A CN 202310518371A CN 116611528 B CN116611528 B CN 116611528B
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- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 4
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
- G06N10/40—Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Condensed Matter Physics & Semiconductors (AREA)
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- General Engineering & Computer Science (AREA)
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Abstract
The application relates to the technical field of quantum computing, in particular to a quantum computing device. The embodiment of the application provides a quantum computing device, which comprises a quantum chip, a shell, a low-temperature fluid pipeline and a supporting structure, wherein the quantum chip is arranged on the shell; the low-temperature fluid pipeline passes through the shell, and the low-temperature fluid pipeline is circulated with low-temperature fluid to provide a low-temperature environment for the quantum chip; one end of the supporting structure is connected with the inner wall of the shell, and the other end of the supporting structure is connected with the quantum chip, and the quantum chip is arranged in the shell through the supporting structure. The embodiment of the application provides a quantum computing device which can provide a stable computing environment for a quantum chip.
Description
Technical Field
The application relates to the technical field of quantum computing, in particular to a quantum computing device.
Background
As the size of components on conventional chips continues to shrink, the performance of the chips continues to increase. However, there is a minimum size limit for elements on the chip, such as transistors, and the existence of quantum tunneling significantly reduces the computational accuracy of the computer when the dimensions of the elements reach the nanometer scale. Therefore, quantum chips with increased calculation speed and calculation excess index become the main attack direction of future researches.
Quantum chips achieve their excellent performance based on quantum entanglement. However, quantum chips have very high demands on their working environment. Therefore, it is significant to provide more stable environment for the quantum chip.
Disclosure of Invention
The embodiment of the application provides a quantum computing device which can provide a stable computing environment for a quantum chip.
The embodiment of the application provides a quantum computing device, which comprises a quantum chip, a shell, a low-temperature fluid pipeline and a supporting structure, wherein the quantum chip is arranged on the shell;
the low-temperature fluid pipeline passes through the shell, and the low-temperature fluid pipeline is circulated with low-temperature fluid to provide a low-temperature environment for the quantum chip;
one end of the supporting structure is connected with the inner wall of the shell, and the other end of the supporting structure is connected with the quantum chip, and the quantum chip is arranged in the shell through the supporting structure.
In one possible design, the support structure includes a first sleeve, a second sleeve and a third sleeve sleeved in sequence from inside to outside, the first sleeve, the second sleeve and the third sleeve are connected through respective ports, the first sleeve includes a first port and a second port, the second sleeve includes a third port and a fourth port, the third sleeve includes a fifth port and a sixth port, the first port, the third port and the fifth port are all directed toward the inner wall of the housing, the second port, the fourth port and the sixth port are all directed toward the quantum chip, the first port is connected with the inner wall of the housing, the second port is connected with the fourth port, the third port is connected with the fifth port, and the sixth port is connected with the quantum chip.
In one possible design, the first sleeve, the second sleeve and the third sleeve are all pipes perpendicular to the inner wall of the shell, and the second port and the fourth port are all connected with the third port and the fifth port through connectors.
In one possible design, the first sleeve has a cross-sectional radius that increases gradually from the first port to the second port, the second sleeve has a cross-sectional radius that increases gradually from the fourth port to the third port, and the third sleeve has a cross-sectional radius that increases gradually from the fifth port to the sixth port.
In one possible design, the sixth port is connected with the quantum chip through a heat-insulating rubber ring.
In one possible design, the support structure is made of a material comprising a ceramic composite material of low thermal conductivity and high strength.
In one possible design, the quantum chip includes a chip body and a support connection portion disposed around the chip body, the chip body being configured to implement quantum computation, the support connection portion being configured to connect with the support structure;
the low-temperature fluid pipeline comprises a pipeline part and a heat transfer part which are mutually communicated, the shape of the heat transfer part is plate-shaped, and the heat transfer part is attached to the chip main body to cool the chip main body.
In one possible design, the low-temperature fluid pipeline comprises two low-temperature fluid pipelines, two heat transfer parts of the two low-temperature fluid pipelines are respectively arranged on two sides of the chip main body, the heat transfer parts sequentially comprise a shielding part and a heat conduction insulation part along the thickness direction, the shielding part is used for shielding electromagnetic wave signals so as to prevent interference of electromagnetic waves on the chip main body, the heat conduction insulation part is used for cooling the chip main body, a cavity is arranged inside the heat conduction insulation part, and the cavity is communicated with the pipeline part so as to circulate low-temperature fluid.
In one possible design, the shielding portion is a metamaterial for shielding the Ghz band;
the metamaterial comprises a periodic arrangement layer and a substrate layer;
the periodic arrangement layer is formed by periodically arranging a plurality of rectangular periodic units;
the periodic unit sequentially comprises a first circular ring, a regular hexagon ring and a second circular ring from outside to inside, and the geometric centers of the first circular ring, the regular hexagon ring and the second circular ring are overlapped with the geometric center of the periodic unit;
the side length of the periodic unit is 6-9 mm, the ring width of the first circular ring is 2mm, the outer diameter of the first circular ring is 5-8 mm, the ring width of the regular hexagon ring is 2mm, the outer diameter of the regular hexagon ring is 4-7 mm, the ring width of the second circular ring is 1mm, and the outer diameter of the second circular ring is 3-5 mm;
the thickness of the periodically arranged layers is 0.5-0.8 mm, and the thickness of the substrate layer is 2-3 mm.
In one possible design, the thermally conductive and insulating portion is made of a material including at least one of silicone rubber, silicone resin, aluminum oxide, boron nitride, and aluminum nitride.
Compared with the prior art, the application has at least the following beneficial effects:
in an embodiment of the application, the quantum chip is placed in a housing, and a cryogenic fluid conduit passes through the housing to provide a stable cryogenic environment for the quantum chip in the housing. In order to reduce the loss of cold energy, the vacuum pumping is needed in the shell, and the contact area between the quantum chip and the shell is also needed to be reduced, so that the quantum chip is suspended and fixed in the shell through the supporting structure, and the supporting structure can not only provide stable supporting performance, but also reduce the cold energy loss of the quantum chip. Specifically, the reduction of the cooling capacity loss of the quantum chip by the support structure comes from two aspects, firstly, the support structure has a certain length, the longer the length is, the more favorable for preventing the cooling capacity loss is, and secondly, the contact area between the support structure and the quantum chip and the shell is small, and the cooling capacity loss can be reduced as well.
It will be appreciated that the external shape of the cryogenic fluid conduit may be adapted to accommodate the space within the housing and the location of the quantum chip. In order to ensure the low-temperature environment of the quantum chip, a plurality of low-temperature fluid pipelines can be designed, and certain space is sacrificed. In order to ensure the cooling effect on the quantum chip, a low-temperature fluid pipeline is required to be attached to the quantum chip for sufficient heat transfer.
It should be noted that, the quantum computing device of this embodiment further includes a wire, one end of which passes through the housing and is connected with the quantum chip, and the other end of which is connected with the external microwave pulse device, the signal receiving device, and other devices. The cryogenic fluid flowing through the cryogenic fluid conduit may be liquid hydrogen, liquid nitrogen, or liquid helium.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a quantum computing device according to an embodiment of the present application;
FIG. 2 is a schematic view of a support structure according to an embodiment of the present application;
FIG. 3 is a schematic view of another support structure according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a periodically arranged layer according to an embodiment of the present application.
In the figure:
1-a quantum chip;
11-a chip body;
12-a support connection;
2-a housing;
3-cryogenic fluid piping;
31-a pipe section;
32-a heat transfer section;
321-a shielding portion;
321 a-a first ring;
321 b-a regular hexagonal ring;
321 c-a second ring;
322-a thermally conductive insulating portion;
4-a support structure;
41-a first sleeve;
42-a second sleeve;
43-a third sleeve;
44-a connector;
51-superconducting temperature measuring part;
52-wire portion.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments, and all other embodiments obtained by those skilled in the art without making any inventive effort based on the embodiments of the present application are within the scope of protection of the present application.
In the description of embodiments of the present application, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying any relative importance unless explicitly specified or limited otherwise; the term "plurality" means two or more, unless specified or indicated otherwise; the terms "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, integrally connected, or electrically connected; can be directly connected or indirectly connected through an intermediate medium. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
In the description of the present specification, it should be understood that the terms "upper", "lower", and the like used in the embodiments of the present application are described in terms of the angles shown in the drawings, and should not be construed as limiting the embodiments of the present application. In the context of this document, it will also be understood that when an element is referred to as being "on" or "under" another element, it can be directly on the other element or be indirectly on the other element through intervening elements.
As shown in fig. 1, an embodiment of the present application provides a quantum computing device including a quantum chip 1, a housing 2, a cryogenic fluid pipe 3, and a support structure 4;
a low-temperature fluid pipe 3 passes through the housing 2, and the low-temperature fluid pipe 3 is circulated with low-temperature fluid to provide a low-temperature environment for the quantum chip 1;
one end of the supporting structure 4 is connected with the inner wall of the shell 2, one end of the supporting structure is connected with the quantum chip 1, and the quantum chip 1 is arranged in the shell 2 through the supporting structure 4.
In an embodiment of the present application, the quantum chip 1 is placed in the housing 2, and the cryogenic fluid pipe 3 passes through the housing 2, providing a stable low temperature environment for the quantum chip 1 in the housing 2. In order to reduce the loss of cold energy, the vacuum is required to be pumped in the shell 2, and the contact area between the quantum chip 1 and the shell 2 is also required to be reduced, so that the quantum chip 1 is suspended and fixed in the shell 2 through the supporting structure 4, and the supporting structure 4 can not only provide stable supporting performance, but also reduce the loss of cold energy of the quantum chip 1. Specifically, the reduction of the cooling loss of the quantum chip 1 by the support structure 4 comes from two aspects, firstly, the support structure 4 has a certain length, the longer the length is, the more favorable for preventing the cooling loss, and secondly, the contact area between the support structure 4 and the quantum chip 1 and the housing 2 is small, and the cooling loss can also be reduced.
It will be appreciated that the external shape of the cryogenic fluid pipe 3 may be adapted to accommodate the space within the housing 2 and the position of the quantum chip 1. In order to ensure a low temperature environment of the quantum chip 1, a plurality of low temperature fluid pipes 3 may be designed, which of course sacrifices a certain space. In order to ensure the cooling effect on the quantum chip 1, the cryogenic fluid pipe 3 is required to be attached to the quantum chip 1 for sufficient heat transfer.
It should be noted that, the quantum computing device of this embodiment further includes a wire, one end of which passes through the housing 2 and is connected to the quantum chip 1, and the other end of which is connected to an external microwave pulse device, a signal receiving device, and other devices. The cryogenic fluid flowing through the cryogenic fluid line 3 may be liquid hydrogen, liquid nitrogen, or liquid helium.
It should be noted that, the material for preparing the support structure 4 may be a metal with low heat conductivity, or may be a ceramic with low heat conductivity, and preferably a metal material that is convenient for processing and welding.
In this embodiment, the temperature of the cryogenic fluid may be 1mK-10K.
In some embodiments of the present application, the support structure 4 includes a first sleeve 41, a second sleeve 42, and a third sleeve 43 sleeved in sequence from inside to outside, where the first sleeve 41, the second sleeve 42, and the third sleeve 43 are connected by respective ports, the first sleeve 41 includes a first port and a second port, the second sleeve 42 includes a third port and a fourth port, the third sleeve 43 includes a fifth port and a sixth port, the first port, the third port, and the fifth port are all oriented toward the inner wall of the housing 2, the second port, the fourth port, and the sixth port are all oriented toward the quantum chip 1, the first port is connected with the inner wall of the housing 2, the second port is connected with the fourth port, the third port is connected with the fifth port, and the sixth port is connected with the quantum chip 1.
In this embodiment, in order to lengthen the heat conduction path as much as possible in a certain space to reduce the loss of the cold energy, the first sleeve 41, the second sleeve 42 and the third sleeve 43 are sequentially sleeved from inside to outside, and the ports of the first sleeve 41, the second sleeve 42 and the third sleeve 43 are connected with each other, and the pipe body is not contacted, so that the space in the shell 2 is saved through the three sleeved sleeves, and meanwhile, the heat conduction path is prolonged due to the design that the ports are connected with each other and the pipe walls are not contacted, so that the loss of the cold energy is reduced. In addition, the hollow tubular design of the first sleeve 41, the second sleeve 42 and the third sleeve 43 can provide stable support, and meanwhile, the hollow tubular design also has a smaller cross section, the smaller cross section is beneficial to reducing the contact area between the sleeve and the quantum chip 1 and/or the shell 2, the small contact area is beneficial to reducing the cold energy loss, and in addition, the small cross section is beneficial to reducing the cold energy loss.
It should be noted that, the housing 2 further includes a plurality of wires connected to the quantum chip 1, so that saving space in the housing 2 is of great importance.
As shown in fig. 3, in some embodiments of the present application, the first sleeve 41, the second sleeve 42 and the third sleeve 43 are all pipes perpendicular to the inner wall of the housing 2, and the second port and the fourth port are connected to the third port and the fifth port through the connection member 44.
In this embodiment, a structure in which ports are connected and tubes are not connected can be realized by the connection member 44.
As shown in fig. 2, in some embodiments of the application, the cross-sectional radius of the first sleeve 41 increases gradually from the first port to the second port, the cross-sectional radius of the second sleeve 42 increases gradually from the fourth port to the third port, and the cross-sectional radius of the third sleeve 43 increases gradually from the fifth port to the sixth port.
In this embodiment, the sections of the first sleeve 41, the second sleeve 42 and the third sleeve 43 are set to have variable diameters, and the section radii of the connection part between the first sleeve 41 and the housing 2 and the connection part between the third sleeve 43 and the quantum chip 1 are large, so that the support performance is higher, the support performance is more stable, and the quantum chip is not easy to bend. In addition, the reducing design also increases the heat conduction path and reduces the loss of cold.
In some embodiments of the application, the sixth port is connected to the quantum chip 1 through an adiabatic rubber ring.
In the present embodiment, since the sixth port is annular, has a small sectional area and a high pressure, in order to protect the quantum chip 1 and prevent the cold loss, an adiabatic rubber ring is provided between the sixth port and the quantum chip 1 to protect the quantum chip 1 and reduce the cold loss.
In some embodiments of the present application, the support structure 4 is made of a material comprising a ceramic composite material with low thermal conductivity and high strength.
In this embodiment, the ceramic composite has excellent strength and low thermal conductivity.
In some embodiments of the present application, the quantum chip 1 includes a chip body 11 and a support connection portion 12 disposed around the chip body 11, where the chip body 11 is used to implement quantum computation, and the support connection portion 12 is used to connect with the support structure 4;
the low-temperature fluid pipe 3 includes a pipe portion 31 and a heat transfer portion 32 which are communicated with each other, the heat transfer portion 32 has a plate-like outer shape, and the heat transfer portion 32 is bonded to the chip main body 11 to cool the chip main body 11.
In this embodiment, in order to avoid collision between the support structure 4 and the heat transfer portion 32, the support connection portion 12 is provided for connection of the support structure 4, and the plate-shaped heat transfer portion 32 is attached to the chip main body 11. The plate-shaped heat transfer part 32 is fully contacted with the chip main body 11, so that the heat conduction efficiency is high, and the cooling effect is obvious. In addition, the flat plate design increases the residence time of the cryogenic fluid at that location, increasing the refrigeration efficiency of the cryogenic fluid.
It will be appreciated that the support structure 4 may be provided in plurality or in one.
In some embodiments of the present application, the heat transfer device comprises two low-temperature fluid pipes 3, two heat transfer parts 32 of the two low-temperature fluid pipes 3 are respectively disposed at two sides of a chip main body 11, the heat transfer parts 32 sequentially comprise a shielding part 321 and a heat conducting insulation part (322) along a thickness direction, the shielding part 321 is used for shielding electromagnetic wave signals to prevent interference of electromagnetic waves on the chip main body 11, the heat conducting insulation part (322) is used for cooling the chip main body 11, the inside of the heat conducting insulation part (322) is a cavity, and the cavity is communicated with the pipe part 31 to circulate low-temperature fluid.
In the present embodiment, the two shielding portions 321 of the plate-shaped heat transfer portions 32 on both sides of the chip body 11 form a shielding structure capable of shielding electromagnetic waves that interfere with the chip body 11 while cooling. In order to achieve the effect of shielding electromagnetic waves, the shielding portion 321 cannot directly contact the chip main body 11, and therefore, the heat conductive insulating portion (322) is provided to play a role of isolating the shielding portion 321 from the chip main body 11, and at the same time, the heat conductive insulating portion (322) having a high heat conductive property can also ensure the cooling effect on the chip main body 11.
It will be appreciated that the cryogenic fluid flows through the interior of the thermally conductive and insulating portion (322).
In some embodiments of the present application, the shielding portion 321 is a metamaterial for shielding the Ghz band;
the metamaterial comprises a periodic arrangement layer and a substrate layer;
the periodic arrangement layer is formed by periodically arranging a plurality of rectangular periodic units;
the periodic unit sequentially comprises a first circular ring 321a, a regular hexagonal ring 321b and a second circular ring 321c from outside to inside, and the geometric centers of the first circular ring 321a, the regular hexagonal ring 321b and the second circular ring 321c are overlapped with the geometric center of the periodic unit;
the side length of the periodic unit is 6-9 mm, the ring width of the first circular ring 321a is 2mm, the outer diameter of the first circular ring is 5-8 mm, the ring width of the regular hexagonal ring 321b is 2mm, the outer diameter of the regular hexagonal ring is 4-7 mm, the ring width of the second circular ring 321c is 1mm, and the outer diameter of the second circular ring is 3-5 mm;
the thickness of the periodically arranged layers is 0.5-0.8 mm, and the thickness of the base layer is 2-3 mm.
In the present embodiment, the metamaterial is thin, and the use of the metamaterial in the present embodiment as the shielding portion 321 enables a superior shielding effect to be achieved in a smaller space. The loss array formed by etching the periodic units with special shapes can form specific resistance which can shield electromagnetic waves with the wave band of 2-18 Ghz.
The direction of the periodic arrangement of the periodic units is the direction of two sides adjacent to the periodic unit, and the minimum period of the periodic arrangement is the side length of the periodic unit.
The special shape on the periodic unit can be obtained by a laser etching process on the polyimide film.
In some embodiments of the present application, the thermally conductive and insulating portion (322) is made of a material including at least one of silicone rubber, silicone resin, aluminum oxide, boron nitride, and aluminum nitride.
In this embodiment, silicone rubber, silicone resin, aluminum oxide, boron nitride, and aluminum nitride are all insulating materials having excellent heat conduction functions.
In some embodiments of the present application, in order to monitor the temperature of the quantum chip 1 in the quantum computing device, a temperature measuring device is provided, the temperature measuring device includes a superconducting temperature measuring part 51, a wire part 52, a power supply, an ammeter, a voltmeter and a display part, the superconducting temperature measuring part 51 is attached to the quantum chip 1, the superconducting temperature measuring part 51 is connected with the power supply through the wire part 52 to form a circuit, the ammeter is used for measuring the current of the circuit, the voltmeter is used for measuring the voltage of the circuit, the display device is used for collecting the resistance of the circuit in real time, and whether the temperature of the quantum chip 1 is in a safe interval or not is displayed according to the resistance of the circuit.
In the embodiment of the application, in order to ensure the safe operation environment of the quantum chip 1, the temperature of the quantum chip 1 needs to be monitored, and in the existing thermometer, part of the thermometer cannot adapt to the ultralow-temperature environment, and part of the thermometer has the advantages of complex structure, more circuits and larger occupied space. Therefore, the application designs a temperature measuring device to realize ultralow temperature measurement. The temperature measuring device includes a superconducting temperature measuring part 51, a wire part 52, a power supply, an ammeter, a voltmeter and a display part. The superconducting temperature measuring part 51 is attached to the quantum chip 1, and the temperature of the superconducting temperature measuring part 51 is the temperature of the quantum chip 1. The resistance value of the circuit can be calculated by collecting the values of the voltmeter and the ammeter, and the resistance of the superconducting temperature measuring part 51 made of the superconducting material can change along with the change of temperature, so that the measured resistance of the circuit also changes along with the change of temperature, and the display part can obtain the temperature condition of the quantum chip 1 according to the resistance value of the circuit, thereby realizing the temperature monitoring function of the quantum chip 1. The superconducting temperature measuring section 51 has a strip shape or a linear shape, and occupies a small space. The superconducting temperature measuring part 51 may be prepared by selecting a superconducting material suitable for a supercritical temperature according to an operating temperature of the quantum chip 1.
In some embodiments of the present application, the superconducting temperature measuring part 51 includes an insulating connection part and a superconducting part, the superconducting part is fixed on the quantum chip 1 through the insulating connection part, a preparation material of the superconducting part includes a superconducting material, and a preparation material of the insulating connection part includes a heat conductive insulating material.
In the present embodiment, in order to reduce the influence of the quantum chip 1 on the resistance of the circuit, the superconducting portion and the quantum chip 1 are connected by an insulating connection portion. Alternatively, the superconducting portion may be a tape-shaped superconducting material having a width of less than 4mm, or may be a wire-shaped superconducting material having a diameter of less than 0.5 mm. The insulating connecting part can be glass fiber cloth or insulating paper, and the thickness is lower than 0.05mm.
In some embodiments of the application, the superconducting portion includes a plurality of superconducting materials having different superconducting critical temperatures connected in sequence.
In this embodiment, a plurality of superconducting materials having different superconducting critical temperatures are connected in series, and before the superconducting section is incorporated into the quantum computing device, different resistances of the circuit are measured when the superconducting section is at the different superconducting critical temperatures, and the different resistances are input to the display device. After being installed into the quantum computing device, the display device can output the temperature of the quantum chip 1 according to different resistance values acquired in real time.
It will be appreciated that the more superconducting materials in series, the smaller the different superconducting critical temperature intervals, the more accurate the value output by the display device.
In some embodiments of the present application, the resistance of the circuit includes a first resistance value and a second resistance value, the first resistance value is a value of the resistance of the circuit when the superconducting temperature measurement portion 51 reaches the highest safe use temperature, and the second resistance value is a value of the resistance of the circuit after the superconducting temperature measurement portion 51 is superconducting;
the display device outputs a safety value according to the resistance of the circuit, and the safety value is calculated by the following formula:
Q=100%-(R-R2)/(R1-R2)
wherein Q is a safety value, R is a resistor of the circuit, R1 is a first resistance value, and R2 is a second resistance value.
In this embodiment, when only a single kind of superconducting material is provided, the resistances of the circuit, that is, the first resistance value and the second resistance value, can be measured in two extreme states, and then the resistances measured in real time are converted into the safety values representing the temperature of the quantum chip 1 based on the first resistance value and the second resistance value. The higher the safety value is, the safer the operation temperature of the quantum chip 1 is, the lower the safety value is, the more dangerous the operation environment of the quantum chip 1 is, when the safety value is lower than 0, the operation temperature of the quantum chip 1 exceeds the bearable temperature, and the operation and maintenance are required to be stopped.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims (9)
1. A quantum computing device characterized by comprising a quantum chip (1), a housing (2), a cryogenic fluid conduit (3) and a support structure (4);
the low-temperature fluid pipeline (3) passes through the shell (2), and the low-temperature fluid pipeline (3) is communicated with low-temperature fluid so as to provide a low-temperature environment for the quantum chip (1);
one end of the supporting structure (4) is connected with the inner wall of the shell (2), the other end of the supporting structure is connected with the quantum chip (1), and the quantum chip (1) is arranged in the shell (2) through the supporting structure (4);
the support structure (4) comprises a first sleeve (41), a second sleeve (42) and a third sleeve (43) which are sequentially sleeved from inside to outside, the first sleeve (41), the second sleeve (42) and the third sleeve (43) are connected through respective ports, the first sleeve (41) comprises a first port and a second port, the second sleeve (42) comprises a third port and a fourth port, the third sleeve (43) comprises a fifth port and a sixth port, the first port, the third port and the fifth port face the inner wall of the shell (2), the second port, the fourth port and the sixth port face the inner wall of the shell (2), the first port is connected with the inner wall of the shell (2), the second port is connected with the fourth port, the third port is connected with the fifth port, and the sixth port is connected with the quantum chip (1).
2. The quantum computing device according to claim 1, wherein the first sleeve (41), the second sleeve (42) and the third sleeve (43) are all tubular bodies perpendicular to the inner wall of the housing (2), and the second port and the fourth port are connected with the third port and the fifth port through connecting pieces (44).
3. The quantum computing device according to claim 1, wherein a cross-sectional radius of the first sleeve (41) gradually increases from the first port to the second port, a cross-sectional radius of the second sleeve (42) gradually increases from the fourth port to the third port, and a cross-sectional radius of the third sleeve (43) gradually increases from the fifth port to the sixth port.
4. Quantum computing device according to claim 1, characterized in that the sixth port is connected to the quantum chip (1) by means of a thermally insulating rubber ring.
5. Quantum computing device according to claim 1, characterized in that the preparation material of the support structure (4) comprises a ceramic composite material of low thermal conductivity and high strength.
6. The quantum computing device according to claim 1, characterized in that the quantum chip (1) comprises a chip body (11) and support connections (12) arranged around the chip body (11), the chip body (11) being for performing quantum computation, the support connections (12) being for connection with the support structure (4);
the low-temperature fluid pipeline (3) comprises a pipeline part (31) and a heat transfer part (32) which are communicated with each other, the shape of the heat transfer part (32) is plate-shaped, and the heat transfer part (32) is attached to the chip main body (11) to cool the chip main body (11).
7. The quantum computing device according to claim 6, comprising two low-temperature fluid pipes (3), two heat transfer portions (32) of the two low-temperature fluid pipes (3) being respectively disposed on both sides of the chip main body (11), the heat transfer portions (32) sequentially including a shielding portion (321) and a heat conductive insulating portion (322) in a thickness direction, the shielding portion (321) being for shielding electromagnetic wave signals to prevent interference of electromagnetic waves on the chip main body (11), the heat conductive insulating portion (322) being for cooling the chip main body (11), an inside of the heat conductive insulating portion (322) being a cavity, the cavity being in communication with the pipe portion (31) to circulate low-temperature fluid.
8. The quantum computing device according to claim 7, wherein the shielding portion (321) is a metamaterial for shielding the Ghz band;
the metamaterial comprises a periodic arrangement layer and a substrate layer;
the periodic arrangement layer is formed by periodically arranging a plurality of rectangular periodic units;
the periodic unit sequentially comprises a first circular ring (321 a), a regular hexagon ring (321 b) and a second circular ring (321 c) from outside to inside, wherein the geometric centers of the first circular ring (321 a), the regular hexagon ring (321 b) and the second circular ring (321 c) are overlapped with the geometric center of the periodic unit;
the side length of the periodic unit is 6-9 mm, the ring width of the first circular ring (321 a) is 2mm, the outer diameter of the first circular ring is 5-8 mm, the ring width of the regular hexagon ring (321 b) is 2mm, the outer diameter of the regular hexagon ring is 4-7 mm, the ring width of the second circular ring (321 c) is 1mm, and the outer diameter of the second circular ring is 3-5 mm;
the thickness of the periodic arrangement layer is 0.5-0.8 mm, and the thickness of the basal layer is 2-3 mm.
9. The quantum computing device of claim 7, wherein the thermally conductive and insulating portion (322) is made of a material comprising at least one of silicone rubber, silicone, aluminum oxide, boron nitride, and aluminum nitride.
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