CN116598353A - Double-groove gallium oxide field effect transistor structure and manufacturing method - Google Patents
Double-groove gallium oxide field effect transistor structure and manufacturing method Download PDFInfo
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- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 title claims abstract description 90
- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 89
- 230000005669 field effect Effects 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000010410 layer Substances 0.000 claims abstract description 197
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 12
- 230000009977 dual effect Effects 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 230000000694 effects Effects 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 14
- 239000003989 dielectric material Substances 0.000 abstract description 3
- 239000000463 material Substances 0.000 description 8
- 238000001259 photo etching Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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Abstract
The invention discloses a double-groove gallium oxide field effect transistor structure, which comprises: the gallium oxide substrate, the drain electrode located at the bottom side of the gallium oxide substrate, the gallium oxide epitaxial layer located at the upper side of the gallium oxide substrate, the source electrode located above the gallium oxide epitaxial layer; the gallium oxide epitaxial layer consists of a pressure-resistant layer, a pbase layer and a conductive layer from bottom to top; the upper part of the gallium oxide epitaxial layer is provided with a first groove and a second groove which are distributed at intervals and extend to the pressure-resistant layer; a P-type oxide layer is deposited on the surface of the first groove, and an ohmic metal layer for filling the first groove is deposited on the surface of the P-type oxide layer; a high-resistance layer is arranged at the bottom of the second groove, and an insulating layer, a gate dielectric layer and a gate electrode filling the second groove are sequentially deposited on the surface of the second groove; an interlayer dielectric layer is covered between the gate electrode and the source electrode. The invention reduces the electric field on the surface of the device, reduces the dependence of the device on the thickness of the gate dielectric material, and reduces the manufacturing difficulty of the device.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a double-groove gallium oxide field effect transistor structure unit and a manufacturing method thereof.
Background
In wide bandgap semiconductor material, ga 2 O 3 Has a forbidden band width of 4.8eV, an ideal breakdown electric field strength of 8MV/cm and BFOM value of 3400, which is about 4 times of GaN and 10 times of SiC. Ga is therefore in power electronics applications today with higher power density and lower power consumption requirements 2 O 3 The material has more important research significance and wider market application prospect. Contrary to the ease of n-type doping, ga is not currently available 2 O 3 Is reported to be successful in achieving p-type doping, which results in Ga 2 O 3 The application in bipolar power devices is limited compared to materials that can be doped bipolar. Gallium oxide lacks an effective P-type semiconductor, so that it cannot be made into a MOSFET of a conventional structure like SiC or GaN, and can be made into a MISFET device or JFET device in which the drain, source and drift regions are all N-type conductive. The gallium oxide MISFET and JFET devices have work function differences between gate metal, polysilicon, P-type semiconductor and gallium oxide epitaxial layers, so that depletion layers appear on conductive channels to influence the working characteristics of the devices.
To achieve enhanced device and reduced metal-semiconductorAn electric field of the interface is used for forming a groove on the surface by etching the gallium oxide epitaxial layer, and then SiO is deposited in the groove 2 And Al 2 O 3 And forming a gate dielectric of the MISFET device by using the insulating dielectric, and manufacturing an Enhanced MISFET (EMISFET). Compared with a planar MISFET device, the EMISFET has normally-off characteristic because the metal gate or the polysilicon gate can completely deplete the conductive channel, and the gate electrode has a certain depth, so that the electric field during partial reverse bias can be effectively shielded, the surface electric field is reduced to a certain extent, and the leakage current is reduced. However, due to the nature of the gallium oxide material, if a large depth of gate dielectric deposition is to be achieved, it cannot be achieved by thermal oxidation, and it is necessary to form deep trenches in the gallium oxide material and then form a deposition of gate dielectric on the surfaces of the deep trenches. Because the depth of the deep groove is larger, the thickness of the gate dielectric layer is uneven, and the uniformity of the threshold voltage of the device is affected. Although the EMISFET can effectively reduce the surface electric field during the reverse direction, due to the limited depth of the groove, the peak electric field is located closer to the surface, and a part of electric field lines still pass through the grid electrode to reach the source electrode, so that the electric field of the metal-semiconductor interface is still strong, and the device can generate larger leakage current to influence the reliability of the device. More importantly, in order to realize that the thickness of the gate dielectric material selected by the enhanced device is very thin, when the peak value of an electric field is transferred from the surface to the internal groove, the gate dielectric can only bear very small voltage, and the device is more likely to break down at the gate dielectric, so that the breakdown voltage and the forward conduction characteristic of the EMISFET device are influenced by the thickness of the gate dielectric, and the advantage of high breakdown field strength of gallium oxide cannot be fully exerted. On the other hand, in order to manufacture an enhancement device, it is necessary to set the pitch of two adjacent trenches to about 0.35 μm, ensuring that the conduction channel is fully depleted at a gate voltage of 0V. To realize small line width and continue to make lithography and etching on the small line width, an expensive electron beam lithography machine needs to replace a common i-line lithography machine to complete the exposure process, which increases the production cost, reduces the productivity, and does not utilize mass production.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a double-groove gallium oxide field effect transistor structure unit and a manufacturing method thereof, which further reduce the electric field at the surface of a device, reduce the dependence of the device on the thickness of a gate dielectric material, and simultaneously reduce the manufacturing difficulty of the device so as to manufacture a gallium oxide field effect transistor device with high voltage resistance and high reliability.
In order to achieve the above purpose, the present invention adopts the following technical scheme.
The invention provides a double-groove gallium oxide field effect transistor structure, which comprises: the gallium oxide substrate is positioned on the drain electrode at the bottom side of the gallium oxide substrate, the gallium oxide epitaxial layer is positioned on the upper side of the gallium oxide substrate, and the source electrode is positioned above the gallium oxide epitaxial layer; the gallium oxide epitaxial layer consists of a pressure-resistant layer, a pbase layer and a conductive layer from bottom to top; the upper part of the gallium oxide epitaxial layer is provided with first grooves and second grooves which are distributed at intervals and extend to the pressure-resistant layer; a P-type oxide layer is deposited on the surface of the first groove, and an ohmic metal layer filling the first groove is deposited on the surface of the P-type oxide layer; a high-resistance layer is arranged at the bottom of the second groove, and an insulating layer, a gate dielectric layer and a gate electrode filling the second groove are sequentially deposited on the surface of the second groove; an interlayer dielectric layer is covered between the gate electrode and the source electrode.
Further, the voltage-resistant layer and the conductive layer are N-type semiconductors, the doping element of the voltage-resistant layer is Si, and the doping concentration is 0.1-1 multiplied by 10 16 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping element of the conductive layer is Si, and the doping concentration is 0.1-1 multiplied by 10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The pbase layer is a weak P-type semiconductor, the doping elements are Mg and N, and the doping concentration is 0.1-10 multiplied by 10 17 cm -3 。
Further, the second groove is a multistage groove.
Furthermore, the material of the P-type oxide layer is selected from NiO and Cu 2 O、TeO 2 One of them.
Furthermore, the ohmic metal layer is made of one of Ni and W.
Further, the high-resistance layer is a pressure-resistant layer at the bottom of the second groove and is formed by implanting N element through ions.
Furthermore, a high-resistance layer is arranged at the bottom of the first groove.
Further, the thickness of the pressure-resistant layer is 5-10 μm, the thickness of the pbase layer is 1-2 μm, and the thickness of the conductive layer is 0.5-1 μm.
Further, the depth of the first groove is not smaller than the depth of the second groove.
The invention also provides a manufacturing method of the double-groove gallium oxide field effect transistor structure, which comprises the following steps:
sequentially epitaxially growing a pressure-resistant layer, a pbase layer and a conductive layer on a gallium oxide substrate to form a gallium oxide epitaxial layer;
etching the gallium oxide epitaxial layer to form a first groove and a second groove which are distributed at intervals;
forming a high-resistance layer at the bottom of the second groove;
depositing drain metal on the bottom side of the gallium oxide substrate to form a drain;
sequentially depositing an insulating layer, a gate dielectric layer and a gate electrode on the surface of the second groove;
sequentially depositing a P-type oxide layer and an ohmic metal layer on the surface of the first groove;
depositing an insulating medium and patterning to form an interlayer medium layer;
and depositing source metal to form a source.
Compared with the prior art, the invention has the beneficial effects that:
(1) The epitaxial layer of the invention adopts a sandwich structure to generate a weak P-type pbase region, thereby solving the dilemma that gallium oxide cannot form a homogeneous P-type semiconductor by ion implantation at present, changing the device design of the prior narrow conductive channel and enabling the device to develop towards more diversification. When the gate-source voltage is gradually increased, electrons of an inversion layer can be generated in the pbase region, and conductivity is provided between the source and the drain; when the gate-source voltage is 0V, the heterojunction formed by the P-type oxide layer and gallium oxide in the first groove, the high-resistance layer and the insulating medium layer in the second groove can shield an electric field, and small leakage current exists between the source and the drain, so that the function of the enhanced device can be completed. When the device works at the third quadrant, the heterojunction formed by the highly doped P-type oxide layer and gallium oxide can complete the electric conduction modulation effect, reduce the on-resistance of the device and inhibit the influence of temperature on the device; the ohmic contact formed by the ohmic metal layer and the P-type oxide layer can reduce the electric conduction modulation voltage of the third quadrant, is beneficial to completing electric conduction modulation of the device as soon as possible, reduces the thermal shock capability of high current to the device, and improves the reliability of the device.
(2) The epitaxial layer sandwich structure and the double-groove structure adopted by the invention can reduce the photoetching difficulty of the existing enhanced device. The high electric field can be shielded between the double grooves of the device due to the high resistance layer, the insulating layer and the P-type oxide layer in the second groove and the first groove, and the space between the double grooves can be properly increased to reduce the photoetching resolution, so that the photoetching process can be realized by using a conventional photoetching machine without expensive electron beam photoetching.
Drawings
Fig. 1 is a schematic diagram of a dual-trench gallium oxide field effect transistor according to embodiment 1;
fig. 2 is a schematic diagram of a manufacturing process flow of a dual trench gallium oxide field effect transistor according to embodiment 1;
fig. 3 is a schematic diagram of a dual-trench gallium oxide field effect transistor according to example 2;
fig. 4 is a schematic diagram of a dual trench gallium oxide field effect transistor according to example 3.
Detailed Description
The present invention is described in further detail below in conjunction with specific embodiments to make the present invention more clearly understood by those skilled in the art. The examples are given solely for the purpose of illustration and are not intended to limit the scope of the invention. In the examples of the present invention, all raw material components are commercially available products well known to those skilled in the art unless specified otherwise; unless specifically indicated, all technical means used are conventional means well known to those skilled in the art.
The embodiment of the invention provides a double-groove gallium oxide field effect transistor structure, which comprises the following components: the gallium oxide substrate, the drain electrode located at the bottom side of the gallium oxide substrate, the gallium oxide epitaxial layer located at the upper side of the gallium oxide substrate, the source electrode located above the gallium oxide epitaxial layer; the gallium oxide epitaxial layer consists of a pressure-resistant layer, a pbase layer and a conductive layer from bottom to top; the upper part of the gallium oxide epitaxial layer is provided with a first groove and a second groove which are distributed at intervals and extend to the pressure-resistant layer; a P-type oxide layer is deposited on the surface of the first groove, and an ohmic metal layer for filling the first groove is deposited on the surface of the P-type oxide layer; a high-resistance layer is arranged at the bottom of the second groove, and an insulating layer, a gate dielectric layer and a gate electrode filling the second groove are sequentially deposited on the surface of the second groove; an interlayer dielectric layer is covered between the gate electrode and the source electrode.
In some preferred embodiments, the voltage-resistant layer and the conductive layer are N-type semiconductors, the voltage-resistant layer is doped with Si at a doping concentration of 0.1-1×10 16 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping element of the conductive layer is Si, and the doping concentration is 0.1-1 multiplied by 10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The pbase layer is a weak P-type semiconductor, the doping elements are Mg and N, and the doping concentration is 0.1-10 multiplied by 10 17 cm -3 . The doping concentration of the conductive layer is far higher than that of the voltage-resistant layer, so that a sandwich structure is formed.
In some preferred embodiments, the second trench is a multi-level trench.
In some preferred embodiments, the material of the P-type oxide layer is selected from NiO and Cu 2 O、TeO 2 One of them.
In some preferred embodiments, the ohmic metal layer is made of one of Ni and W.
In some preferred embodiments, the high-resistance layer is a voltage-resistant layer at the bottom of the second trench, and is formed by ion implantation of N element.
In some preferred embodiments, the bottom of the first trench is provided with a high-resistance layer.
In some preferred embodiments, the thickness of the voltage resistant layer is 5-10 μm, the thickness of the pbase layer is 1-2 μm, and the thickness of the conductive layer is 0.5-1 μm.
In some preferred embodiments, the depth of the first trench is not less than the depth of the second trench.
In some preferred embodiments, the material of the insulating layer is SiO 2 、Si 3 N 4 At least one of them.
In some preferred embodiments, the gate dielectric layer is made of Al 2 O 3 、SiO 2 At least one of them.
In some preferred embodiments, the gate electrode is made of metal or polysilicon.
The embodiment of the invention also provides a manufacturing method of the double-groove gallium oxide field effect transistor structure, which comprises the following steps:
sequentially epitaxially growing a pressure-resistant layer, a pbase layer and a conductive layer on a gallium oxide substrate to form a gallium oxide epitaxial layer;
etching the gallium oxide epitaxial layer to form a first groove and a second groove which are distributed at intervals;
forming a high-resistance layer at the bottom of the second groove;
depositing drain metal on the bottom side of the gallium oxide substrate to form a drain;
sequentially depositing an insulating layer, a gate dielectric layer and a gate electrode on the surface of the second groove;
sequentially depositing a P-type oxide layer and an ohmic metal layer on the surface of the first groove;
depositing an insulating medium and patterning to form an interlayer medium layer;
and depositing source metal to form a source.
Example 1
The structure of the double-trench gallium oxide field effect transistor provided in this embodiment is shown in fig. 1, a drain electrode 3 is deposited on the bottom side of a gallium oxide substrate 1, a gallium oxide epitaxial layer 2 is arranged on the upper side of the gallium oxide substrate 1, and the gallium oxide epitaxial layer 2 is composed of a voltage-resistant layer 201, a pbase layer 202 and a conductive layer 203 from bottom to top; the upper part of the gallium oxide epitaxial layer 2 is provided with single-stage grooves and secondary grooves which are distributed at intervals and extend to the pressure-resistant layer 201; the surface of the single-stage groove is sequentially deposited with a P-type oxide layer 5 and an ohmic metal Ni layer 6 filling the single-stage groove; the bottom of the second-stage groove is provided with a high-resistance layer 7 formed by injecting N element into the pressure-resistant layer 201, and the high-resistance layer 7 surrounds the second-stage sub-groove; an insulating layer 8 is deposited on the bottom of the first-stage sub-groove and the surface of the second-stage sub-groove, a gate dielectric layer 9 is deposited on the surface of the first-stage sub-groove and the surface of the insulating layer 8, and a gate electrode 10 filling the second-stage groove is deposited on the surface of the gate dielectric layer 9; an interlayer dielectric layer 11 is covered between the gate electrode 10 and the source electrode 4.
The specific manufacturing process flow of the double-trench gallium oxide field effect transistor provided in this embodiment is shown in fig. 2, and a voltage-resistant layer 201, a pbase layer 202 and a conductive layer 203 are sequentially epitaxially grown on a gallium oxide substrate 1 to form a gallium oxide epitaxial layer 2; the thickness of the voltage-resistant layer 201 is 10 μm, the doping element is Si, and the doping concentration is 1×10 16 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the pbase layer 202 was 1. Mu.m, the doping elements were Mg and N, and the doping concentration was 5X 10 17 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the conductive layer 203 was 0.5. Mu.m, the doping element was Si, and the doping concentration was 1X 10 18 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the Etching the gallium oxide epitaxial layer 2 to form single-stage grooves and secondary grooves which are distributed at intervals, wherein the depths of the single-stage grooves and the secondary grooves are 2 mu m; injecting N element into the pressure-resistant layer 201 at the bottom of the secondary groove, and annealing to obtain a doping concentration of 1×10 19 cm -3 Forming a high-resistance layer 7; depositing Ti/Au metal on the back of the gallium oxide substrate 1, and annealing to form ohmic contact between the metal and the substrate and form a device drain electrode 3; then depositing SiO on the surface of the gallium oxide epitaxial layer 2 2 The insulating medium is patterned, and the insulating medium at the bottom of the first-stage sub-groove and the surface of the second-stage sub-groove in the second-stage groove is reserved to form an insulating layer 8; deposition of Al on the surface of a secondary trench 2 O 3 Dielectric and patterning to form a gate dielectric layer 9; filling and depositing polysilicon in the second-level trench and patterning to form a gate electrode 10; next, depositing NiO on the surface of the single-stage groove and patterning to form a P-type oxide layer 5, wherein the P-type oxide layer 5 and gallium oxide form a heterojunction and are connected with a pbase layer 202; then filling and depositing metal Ni in the single-stage groove and patterning to form an ohmic metal Ni layer 6, wherein the metal Ni layer 6 and NiO of the P-type oxide layer 5 form ohmic contact; redeposition of SiO 2 Insulating medium, patterned and remained oxygen SiO above gate electrode 10 and gate dielectric layer 9 2 Forming an interlayer dielectric layer 11 isolating the gate electrode 10 and the source electrode 4; finally depositing Ti/Al/Pt metal and tempering to form ohm with the conductive layer 203Contacts form the source 4 of the device.
Example 2
The dual-trench gallium oxide field effect transistor structure provided in this embodiment is as shown in fig. 3, and is different from embodiment 1 in that the bottom of the single-stage trench is also provided with a high-resistance layer 7 formed by injecting N element into the voltage-resistant layer 201, so that the reverse electric field can be shielded.
Example 3
The difference between the structure of the double-trench gallium oxide field effect transistor provided in this embodiment and that of embodiment 1 is that the depth of the single-stage trench is 3 μm and the depth of the secondary trench is 2 μm, as shown in fig. 4; the depth of the single-stage groove with the P-type oxide layer 5 is larger than that of the secondary groove with the gate dielectric layer 9, so that the heterojunction formed by the P-type oxide layer and gallium oxide can better protect the gate dielectric layer and reduce reverse leakage current.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (10)
1. A dual trench gallium oxide field effect transistor structure comprising: the gallium oxide substrate is positioned on the drain electrode at the bottom side of the gallium oxide substrate, the gallium oxide epitaxial layer is positioned on the upper side of the gallium oxide substrate, and the source electrode is positioned above the gallium oxide epitaxial layer; the gallium oxide epitaxial layer consists of a pressure-resistant layer, a pbase layer and a conductive layer from bottom to top; the upper part of the gallium oxide epitaxial layer is provided with first grooves and second grooves which are distributed at intervals and extend to the pressure-resistant layer; a P-type oxide layer is deposited on the surface of the first groove, and an ohmic metal layer filling the first groove is deposited on the surface of the P-type oxide layer; a high-resistance layer is arranged at the bottom of the second groove, and an insulating layer, a gate dielectric layer and a gate electrode filling the second groove are sequentially deposited on the surface of the second groove; an interlayer dielectric layer is covered between the gate electrode and the source electrode.
2. The double trench gallium oxide field of claim 1The effect transistor structure is characterized in that the voltage-resistant layer and the conductive layer are N-type semiconductors, the doping element of the voltage-resistant layer is Si, and the doping concentration is 0.1-1 multiplied by 10 16 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping element of the conductive layer is Si, and the doping concentration is 0.1-1 multiplied by 10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The pbase layer is a weak P-type semiconductor, the doping elements are Mg and N, and the doping concentration is 0.1-10 multiplied by 10 17 cm -3 。
3. The dual trench gallium oxide field effect transistor structure of claim 1, wherein the second trench is a multi-level trench.
4. The dual trench gallium oxide field effect transistor structure of claim 1, wherein the P-type oxide layer is made of NiO or Cu 2 O、TeO 2 One of them.
5. The dual trench gallium oxide field effect transistor structure of claim 1, wherein the ohmic metal layer is one of Ni and W.
6. The dual trench gallium oxide field effect transistor structure according to claim 1, wherein the high-resistance layer is a voltage-resistant layer at the bottom of the second trench formed by ion implantation of N element.
7. The dual trench gallium oxide field effect transistor structure of claim 1, wherein a high resistance layer is provided at the bottom of the first trench.
8. The double trench gallium oxide field effect transistor structure according to claim 1, wherein the thickness of the voltage-resistant layer is 5 to 10 μm, the thickness of the pbase layer is 1 to 2 μm, and the thickness of the conductive layer is 0.5 to 1 μm.
9. The dual trench gallium oxide field effect transistor structure of claim 1, wherein a depth of the first trench is not less than a depth of the second trench.
10. The method for manufacturing the double-groove gallium oxide field effect transistor structure according to any one of claims 1 to 9, comprising the following steps:
sequentially epitaxially growing a pressure-resistant layer, a pbase layer and a conductive layer on a gallium oxide substrate to form a gallium oxide epitaxial layer;
etching the gallium oxide epitaxial layer to form a first groove and a second groove which are distributed at intervals;
forming a high-resistance layer at the bottom of the second groove;
depositing drain metal on the bottom side of the gallium oxide substrate to form a drain;
sequentially depositing an insulating layer, a gate dielectric layer and a gate electrode on the surface of the second groove;
sequentially depositing a P-type oxide layer and an ohmic metal layer on the surface of the first groove;
depositing an insulating medium and patterning to form an interlayer medium layer;
and depositing source metal to form a source.
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