CN116566544A - Channel coding method and device based on reconfigurable processor architecture design - Google Patents

Channel coding method and device based on reconfigurable processor architecture design Download PDF

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Publication number
CN116566544A
CN116566544A CN202310347187.1A CN202310347187A CN116566544A CN 116566544 A CN116566544 A CN 116566544A CN 202310347187 A CN202310347187 A CN 202310347187A CN 116566544 A CN116566544 A CN 116566544A
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sub
matrix
intermediate variable
information
codeword
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尹首一
王洲
位经传
胡杨
韩慧明
魏少军
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Tsinghua University
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Tsinghua University
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The application relates to a channel coding method and device based on reconfigurable processor architecture design. The method comprises the following steps: and determining intermediate variable submatrices corresponding to the row check submatrices according to each submatrix included in the information codeword to be encoded and the row check submatrices corresponding to each submatrix, determining sub-check bit codewords corresponding to each intermediate variable submatrix according to the relation between each row check submatrix and the encoded information codeword corresponding to the information codeword to be encoded and each intermediate variable submatrix, and obtaining the encoded information codeword corresponding to the information codeword to be encoded according to the sub-check bit codewords corresponding to each intermediate variable submatrix and each sub-information codeword. The method can improve the efficiency of channel coding.

Description

Channel coding method and device based on reconfigurable processor architecture design
Technical Field
The present disclosure relates to the field of channel coding technologies, and in particular, to a channel coding method and apparatus based on reconfigurable processor architecture design.
Background
For a long time, people always pursue efficient, reliable and safe information communication modes, various communication tools and means are created, and development and progress of human society are continuously promoted. In a communication system, in order to enhance the ability of data to resist various kinds of interference when transmitted in a channel of the communication system, to improve the reliability of the communication system, it is necessary to perform channel coding on the communication system.
In the traditional technology, the channel coding is carried out by adopting a check matrix coding method with quasi-cyclic characteristics, and the method utilizes the quasi-cyclic characteristics of the check matrix to carry out the channel coding, so that the operation complexity is higher, and the efficiency of realizing the channel coding is lower.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a channel coding method and apparatus based on a reconfigurable processor architecture design that can improve the efficiency of channel coding.
In a first aspect, the present application provides a channel coding method based on reconfigurable processor architecture design. The method comprises the following steps:
determining an intermediate submatrix corresponding to each row of the submatrix according to each row of the submatrix and each row of the submatrix corresponding to each row of the submatrix, wherein each row of the submatrix comprises the information codeword to be coded;
determining sub-check bit code words corresponding to the intermediate variable sub-matrixes according to the relation between the row check sub-matrixes and the code information code words corresponding to the code information code words to be coded and the intermediate variable sub-matrixes;
and obtaining the code information code word corresponding to the information code word to be coded according to the sub check bit code word corresponding to each intermediate variable sub matrix and each sub information code word.
In one embodiment, the determining the sub-check bit codeword corresponding to each intermediate variable sub-matrix according to the relationship between each row of check sub-matrix and the encoded information codeword corresponding to the information codeword to be encoded and each intermediate variable sub-matrix includes:
determining a first target expression according to the relation between each row of check sub-matrixes and the coding information code word corresponding to the information code word to be coded; the first target expression is used for representing the relation among the sub-check bit codeword corresponding to the current first intermediate variable sub-matrix, the sub-check bit codeword corresponding to the last intermediate variable sub-matrix of the first intermediate variable sub-matrix and the first intermediate variable sub-matrix, wherein the first intermediate variable sub-matrix is the first intermediate variable sub-matrix in the intermediate variable sub-matrix to be determined currently;
and determining the sub check bit code words corresponding to the intermediate variable sub matrices according to the first target expression.
In one embodiment, determining the sub-check bit codeword corresponding to each sub-information codeword according to the relationship between the row check sub-matrix corresponding to each sub-information codeword and the encoded information codeword corresponding to the information codeword to be encoded and the intermediate variable sub-matrix corresponding to each sub-information codeword includes:
Determining a second target expression value according to the relation between each row of check sub-matrix and the coding information code word corresponding to the information code word to be coded; the second target expression is used for representing the relation between the sub-check bit codeword corresponding to the current second intermediate variable sub-matrix, the last intermediate variable sub-matrix of the second intermediate variable sub-matrix and the sub-check bit codeword corresponding to the last intermediate variable sub-matrix of the second intermediate variable sub-matrix, wherein the second intermediate variable sub-matrix is the last intermediate variable sub-matrix in the intermediate variable sub-matrix to be determined currently;
and determining the sub check bit code word corresponding to each sub information code word according to the second target expression.
In one embodiment, the determining, according to each sub-information codeword included in the information codeword to be encoded and a row check sub-matrix corresponding to each sub-information codeword, an intermediate variable sub-matrix corresponding to the row check sub-matrix includes:
performing cyclic shift on each sub-information codeword according to the row check sub-matrix to obtain a cyclic shift result corresponding to each sub-information codeword;
and carrying out bitwise exclusive OR on the cyclic shift result corresponding to each sub-information codeword to determine an intermediate sub-matrix corresponding to the row of check sub-matrix.
In a second aspect, the present application also provides a channel coding device designed based on a reconfigurable processor architecture. The device comprises a first calculator, a second calculator and an output device;
the first calculator is used for determining an intermediate sub-matrix corresponding to each row of the sub-matrix according to each sub-information code word included in the information code word to be encoded and the row of the sub-matrix corresponding to each sub-information code word;
the second calculator is used for determining sub-check bit code words corresponding to the intermediate variable sub-matrixes according to the relation between the row check sub-matrixes and the coding information code words corresponding to the information code words to be coded and the intermediate variable sub-matrixes;
the output device is used for obtaining the code information code word corresponding to the information code word to be coded according to the sub check bit code word corresponding to each intermediate variable sub matrix and each sub information code word.
In one embodiment, the second calculator is configured to determine a first target expression according to a relationship between each row of the check sub-matrix and an encoded information codeword corresponding to the information codeword to be encoded; the first target expression is used for representing the relation among the sub-check bit codeword corresponding to the current first intermediate variable sub-matrix, the sub-check bit codeword corresponding to the last intermediate variable sub-matrix of the first intermediate variable sub-matrix and the first intermediate variable sub-matrix, wherein the first intermediate variable sub-matrix is the first intermediate variable sub-matrix in the intermediate variable sub-matrix to be determined currently;
The second calculator is used for determining the sub-check bit code words corresponding to the intermediate variable sub-matrixes according to the first target expression.
In one embodiment, the second calculator is configured to determine a second target expression value according to a relationship between each row of the check sub-matrix and the encoded information codeword corresponding to the information codeword to be encoded; the second target expression is used for representing the relation between the sub-check bit codeword corresponding to the current second intermediate variable sub-matrix, the last intermediate variable sub-matrix of the second intermediate variable sub-matrix and the sub-check bit codeword corresponding to the last intermediate variable sub-matrix of the second intermediate variable sub-matrix, wherein the second intermediate variable sub-matrix is the last intermediate variable sub-matrix in the intermediate variable sub-matrix to be determined currently;
the second calculator is configured to determine, according to the second target expression, a sub-parity codeword corresponding to each sub-information codeword.
In one embodiment, the first calculator is configured to perform cyclic shift on each of the sub-information codewords according to the row check sub-matrix, so as to obtain a cyclic shift result corresponding to each of the sub-information codewords;
the first calculator is configured to perform bitwise exclusive or on a cyclic shift result corresponding to each sub-information codeword, so as to determine an intermediate sub-matrix corresponding to the row of check sub-matrices.
In one embodiment, the apparatus further comprises an intermediate variable register and a controller, the intermediate variable register being connected to the first calculator, the second calculator, the controller;
the intermediate variable register is used for receiving a first instruction sent by the controller, acquiring the intermediate variable submatrix in the first calculator according to the first instruction, and storing the intermediate variable submatrix;
the second calculator is configured to obtain the intermediate variable submatrix in the intermediate variable register.
In one embodiment, the device further includes a check bit codeword register, a row check sub-matrix register, and a sub-information codeword register, where the check bit codeword register is connected to the second calculator, the output device, and the controller, the row check sub-matrix register is connected to the first calculator, and the controller, and the sub-information codeword register is connected to the controller, the first calculator, and the output device;
the check bit code word register is used for receiving a second instruction sent by the controller, acquiring the sub-check bit code word in the second calculator according to the second instruction, and sending the sub-check bit code word to the output device;
The row check sub-matrix register is used for receiving a third instruction sent by the controller and sending the row check sub-matrix to the first calculator according to the third instruction;
the sub-information code word register is used for receiving a fourth instruction sent by the controller, receiving the information code word to be encoded according to the fourth instruction, splitting the information code word to be encoded into sub-information code words, and sending the sub-information code words to the output device and the first calculator.
In a third aspect, the present application also provides a computer device. The computer device comprises a memory storing a computer program and a processor which when executing the computer program performs the steps of:
determining an intermediate submatrix corresponding to each row of the submatrix according to each row of the submatrix and each row of the submatrix corresponding to each row of the submatrix, wherein each row of the submatrix comprises the information codeword to be coded;
determining sub-check bit code words corresponding to each intermediate variable sub-matrix according to the relation between each row of check sub-matrix and the information code word to be coded and each intermediate variable sub-matrix;
and obtaining the code information code word corresponding to the information code word to be coded according to the sub check bit code word corresponding to each intermediate variable sub matrix and each sub information code word.
In a fourth aspect, the present application also provides a computer-readable storage medium. The computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of:
determining an intermediate submatrix corresponding to each row of the submatrix according to each row of the submatrix and each row of the submatrix corresponding to each row of the submatrix, wherein each row of the submatrix comprises the information codeword to be coded;
determining sub-check bit code words corresponding to the intermediate variable sub-matrixes according to the relation between the row check sub-matrixes and the code information code words corresponding to the code information code words to be coded and the intermediate variable sub-matrixes;
and obtaining the code information code word corresponding to the information code word to be coded according to the sub check bit code word corresponding to each intermediate variable sub matrix and each sub information code word.
In a fifth aspect, the present application also provides a computer program product. The computer program product comprising a computer program which, when executed by a processor, performs the steps of:
determining an intermediate submatrix corresponding to each row of the submatrix according to each row of the submatrix and each row of the submatrix corresponding to each row of the submatrix, wherein each row of the submatrix comprises the information codeword to be coded;
Determining sub-check bit code words corresponding to the intermediate variable sub-matrixes according to the relation between the row check sub-matrixes and the code information code words corresponding to the code information code words to be coded and the intermediate variable sub-matrixes;
and obtaining the code information code word corresponding to the information code word to be coded according to the sub check bit code word corresponding to each intermediate variable sub matrix and each sub information code word.
According to the channel coding method and device based on the reconfigurable processor architecture design, the intermediate variable submatrices corresponding to the row check submatrices are determined according to the submatrices included by the information code word to be coded and the row check submatrices corresponding to the submatrices, the sub-check bit code words corresponding to the intermediate variable submatrices are further determined according to the relation between the row check submatrices and the coding information code words corresponding to the information code word to be coded and the intermediate variable submatrices, and the coding information code words corresponding to the information code word to be coded are obtained according to the sub-check bit code words corresponding to the intermediate variable submatrices and the sub-information code words. In the prior art, channel coding is performed by adopting a check matrix coding method with quasi-cyclic characteristics, the method utilizes the quasi-cyclic characteristics of the check matrix to determine check bit code words, the operation complexity is higher, and the efficiency of realizing channel coding is lower.
Drawings
Fig. 1 is one of block diagrams of a channel coding apparatus provided in an embodiment of the present application;
fig. 2 is a schematic flow chart of a channel coding method according to an embodiment of the present application;
FIG. 3 is a flowchart of a method for determining a codeword of a sub-parity bit according to an embodiment of the present application;
FIG. 4 is a second flowchart of a method for determining a codeword of a sub-parity bit according to an embodiment of the present application;
FIG. 5 is a schematic flow chart of an intermediate variable sub-matrix determination method according to an embodiment of the present application;
FIG. 6 is a second block diagram of a channel coding device according to an embodiment of the present disclosure;
fig. 7 is a third block diagram of a channel coding device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
The channel coding method provided in the embodiment of the present application may be applied to the channel coding device 100 shown in fig. 1. The apparatus 100 comprises a first calculator 101, a second calculator 102, an output device 103, a controller 104, an intermediate variable register 105, a check bit codeword register 106, a row check sub-matrix register 107, a sub-information codeword register 108. The first calculator 101 is connected to the sub-information codeword register 108, the row check sub-matrix register 107, and the intermediate variable register 105, and is configured to obtain the sub-information codeword stored in the sub-information codeword register 108 and the row check sub-matrix stored in the row check sub-matrix register 107, and determine the intermediate variable sub-matrix according to the sub-information codeword and the row check sub-matrix. The intermediate variable register 105 is used to obtain the intermediate variable submatrix calculated by the first calculator 101. The second calculator 102 is connected to the intermediate variable register 105 and the check bit codeword register 106, and is configured to obtain an intermediate variable submatrix stored in the intermediate variable register, and determine a submatrix codeword according to the intermediate variable submatrix. The check bit codeword register 106 is configured to obtain the sub-check bit codeword determined by the second calculator, and store the sub-check bit codeword. The controller 104 is connected to each register and the output device 103, and is used for sending control instructions to each register and the control device 103, and the output device 103 is connected to the sub-information codeword register 108, the controller 104, and the check bit codeword register 106, and is used for obtaining the sub-information codeword stored in the sub-information codeword register 108 and the sub-check bit codeword stored in the check bit codeword register 106, and obtaining the encoded information codeword corresponding to the information codeword to be encoded according to each sub-check bit codeword and each sub-information codeword. According to the channel decoding method, the information to be coded, the check matrix and the intermediate variables are split, the sub-check bit code words corresponding to the intermediate variable sub-matrices are determined according to the relationship between each row of check sub-matrix and the information code word to be coded obtained after splitting and each intermediate variable sub-matrix, and the coded information code words corresponding to the information code word to be coded are obtained according to each sub-check bit code word and each sub-information code word. The channel decoding device 100 designed based on the method can reconstruct the first calculator and the second calculator according to the number of check sub-matrixes of each row and the number of intermediate variable sub-matrixes, further process each information code word to be encoded, determine sub-check bit code words, and has higher flexibility of channel encoding.
In one embodiment, as shown in fig. 2, fig. 2 is a schematic flow chart of a channel coding method provided in the embodiment of the present application, and the method is applied to the channel coding apparatus 100 in fig. 1 for illustration, and may include the following steps:
s201, determining an intermediate submatrix corresponding to the row check submatrix according to each sub-information codeword included in the information codeword to be encoded and the row check submatrix corresponding to each sub-information codeword.
Wherein the information code word to be encoded is an original information code word obtained from a communication device of a communication system by a channel coding device. The row check sub-matrix represents a row of sub-matrix in the check matrix corresponding to the information to be coded, and the check matrix is a matrix set in advance.
In this embodiment, the information codeword to be encoded may be split according to a first preset splitting rule, so as to determine each sub-information codeword. For example, the information codeword to be encoded is set as s, and s can be split into k according to a preset splitting rule b The sub-information codeword, which may be expressed asSetting the check matrix as H, and setting a matrix L formed by the sub-matrix of the ith+1th row of the check matrix H i,j For a row of the check sub-matrix, i has a minimum value of 0, i has a maximum value of 1, which is the total number of rows of the check matrix H minus 1, for example, the check matrix H has 20 rows in total, and i has a value range of (0, 19). The submatrices formed by the column elements in the row check submatrices correspond to the submatrices. For example, row check submatrix column j+1 i,j Sub-information codeword s j Correspondingly, the value range of j is (0, k) b -1). The intermediate variable submatrices may be represented by the following relationship:
wherein b can be i Represented as an intermediate variable sub-matrix, m b Check submatrix L for rows i,j And the total number of the intermediate variable submatrices is also the total number of the intermediate variable submatrices, and one row of the check submatrices corresponds to one intermediate variable submatrix.
Alternatively, b may also be i And multiplying the product result obtained by the first preset coefficient to obtain an intermediate variable submatrix.
S202, determining sub-check bit code words corresponding to each intermediate variable sub-matrix according to the relation between each row of check sub-matrix and the code information code words corresponding to the code information code words to be coded and each intermediate variable sub-matrix.
The above examples are used to describe the coding to be performedThe coded information codeword corresponding to the information codeword s is c, and the sub-parity codeword is p i C is formed by each sub-information codeword s j And each sub-check bit codeword p i The composition is formed. In this embodiment, it should be noted that the check matrix H and the code information codeword c satisfy a check relation h×c T =0; because H is defined by the row check sub-matrix L i,j And c is formed by each sub-information codeword s j And each sub-check bit codeword p i So, it can be based on the row check submatrix L i,j And the relation between the code words c of the code information, deducing the code words c and b of the code information i According to the relation of c and b i Relation of (c) and each intermediate variable sub-matrix b i Determining each intermediate variable sub-matrix b i Corresponding sub-check bit codeword p i 。
S203, obtaining the code information code word corresponding to the information code word to be coded according to the sub check bit code word corresponding to each intermediate variable sub matrix and each sub information code word.
The above example is used to describe the code information codeword c= [ s, p]Wherein s represents an information codeword to be encoded, s is defined by each sub-information codeword s j The composition, p, represents the parity codeword, p is defined by each sub-parity codeword p i The composition, therefore, of the encoded information codeword may also be expressed asIf the code information code word needs to be determined, only each sub check bit code word p needs to be determined i Then each sub-information codeword s j And each sub-check bit codeword p i And merging according to a preset merging rule.
According to the channel coding method, the intermediate variable submatrices corresponding to the row check submatrices are determined according to the submatrices and the row check submatrices corresponding to the submatrices included by the information codeword to be coded, the sub-check bit codewords corresponding to the intermediate variable submatrices are further determined according to the relations between the row check submatrices and the coding information codeword corresponding to the information codeword to be coded and the intermediate variable submatrices, and the coding information codeword corresponding to the information codeword to be coded is obtained according to the sub-check bit codewords corresponding to the intermediate variable submatrices and the sub-information codeword. In the prior art, channel coding is performed by adopting a check matrix coding method with quasi-cyclic characteristics, the method utilizes the quasi-cyclic characteristics of the check matrix to determine check bit code words, the operation complexity is higher, and the efficiency of realizing channel coding is lower.
Fig. 3 is one of the flow diagrams of the method for determining a sub-check bit codeword provided in the embodiment of the present application, where the embodiment relates to how to determine, according to the relationship between each row of check sub-matrices and the encoded information codeword corresponding to the information codeword to be encoded, each intermediate variable sub-matrix, one possible implementation manner of the sub-check bit codeword corresponding to each intermediate variable sub-matrix, where, based on the foregoing embodiment, as shown in fig. 3, the foregoing S201 may include:
s301, determining a first target expression according to the relation between each row of check sub-matrix and the coding information code word corresponding to the information code word to be coded; the first target expression is used for representing the relation among the sub-check bit codeword corresponding to the current first intermediate variable sub-matrix, the sub-check bit codeword corresponding to the last intermediate variable sub-matrix of the first intermediate variable sub-matrix and the first intermediate variable sub-matrix, wherein the first intermediate variable sub-matrix is the first intermediate variable sub-matrix in the intermediate variable sub-matrix to be determined currently.
The above examples are described, the check matrix H and the code information codeword c satisfy the check relation H×c T =0; because H is defined by the row check sub-matrix L i,j And c is formed by each sub-information codeword s j And each sub-check bit codeword p i The following relation can be derived from the above-described verification relation:
b i +p i +p i+1 ＝0(1≤i≤m b -2,i≠x) (2)
wherein p is 0 (1) Representing p 0 The value of l can be preset through the vector of the cyclic shift l times. The method can be obtained according to the following relation (2):
p i+1 ＝p i +b i (4)
equation (4) is taken as a first target expression.
S302, determining sub check bit code words corresponding to all intermediate variable sub matrixes according to the first target expression.
When i=0, the first target expression can be expressed as:
p 1 ＝p 0 (1) +b 0 (5)
p 0 (1) also can use each intermediate variable submatrix b i Is expressed by the sum of the sums:
determining p according to formula (6) 0 (1) Will p 0 (1) And b defined by the formula (1) 0 Substituting into (5) to determine p 1 And so on, determining a first intermediate variable submatrix b of each time according to the first target expression i+1 Corresponding sub-check bit codeword p i+1 . Alternatively, the process of determining the intermediate variable sub-matrix according to equation (1) and the process of determining the sub-check bit codeword according to the first target expression may be performed simultaneously to improve the efficiency of channel coding.
In the embodiment of the application, the first target expression is determined according to the relation between each row of check sub-matrix and the code information code word corresponding to the code information code word to be coded, and the sub-check bit code word corresponding to each intermediate variable sub-matrix is further determined according to the first target expression. Because each sub check bit code word is determined, the calculation complexity is reduced, and the efficiency of channel coding is further improved.
Fig. 4 is a second flowchart of a method for determining a sub-parity codeword according to an embodiment of the present application, which relates to how to determine a possible implementation manner of a sub-parity codeword corresponding to each sub-information codeword according to a relationship between a row check sub-matrix corresponding to each sub-information codeword and an encoded information codeword corresponding to an information codeword to be encoded and an intermediate variable sub-matrix corresponding to each sub-information codeword, where, based on the embodiment, as shown in fig. 4, the step S202 may further include:
s401, determining a second target expression value according to the relation between each row of check sub-matrix and the coding information code word corresponding to the information code word to be coded; the second target expression is used for representing the relation between the sub-check bit codeword corresponding to the current second intermediate variable sub-matrix and the sub-check bit codeword corresponding to the last intermediate variable sub-matrix of the second intermediate variable sub-matrix, and the second intermediate variable sub-matrix is the last intermediate variable sub-matrix in the intermediate variable sub-matrix to be determined currently.
S402, determining the sub check bit code word corresponding to each sub information code word according to the second target expression.
Illustratively, a second target expression may be obtained according to equation (2):
p i ＝p i+1 +b i (7)
for the followingp 0 (l) The following relationship holds:
wherein p is 0 (1) Can be based on each intermediate variable submatrix b i Is determined by the sum of the sums of (a) and (b),can be based on each sub-information codeword and row check sub-matrix +.>It is determined, therefore, that +.>At this time, let i=m b -2, based on a second target expression, obtaining:
can check the submatrix according to each submatrix code word and lineDetermine->Will->And->Substitution into the above formula to determine +.>And by analogy, sequentially performing forward recursion calculation according to the second target expression and each intermediate variable sub-matrix to determine each sub-check bit codeword.
Alternatively, a bi-directional recursive operation may be performed based on the first target expression and the second target expression to determine each sub-parity codeword. Specifically, when the above description is given in connection with the above example, p can be determined according to the formula (5) 1 Can be determined according to the formula (8)If m is b Odd, then will determine good p 1 Substituting the first target expression, sequentially recursively determining p backward 2 To->Will->Substituting the second target expression to sequentially recursively determine the code words of all the sub check bits forwards>To the point ofIf m is b Even, then a good p will be determined 1 Substituting the first target expression, sequentially recursively determining p backward 2 To the point ofWill->Substituting the second target expression to sequentially recursively determine the code words of all the sub check bits forwards>To the point ofThe backward recursion operation according to the first target expression and the forward recursion operation according to the second target expression may be performed simultaneously to improve the efficiency of determining the sub-parity bit codeword.
In this embodiment, the second target expression value is determined according to the relationship between the check sub-matrix of each row and the code information codeword corresponding to the code information codeword to be coded, and the sub-check bit codeword corresponding to each sub-information codeword is further determined according to the second target expression. Because each sub-check bit codeword is determined, the computational complexity is reduced, and the bidirectional recursive operation is performed simultaneously according to the first target expression and the second target expression, the time required for operating the sub-check bit codeword can be further reduced, and the efficiency of channel coding is improved.
Fig. 5 is a flow chart of an intermediate variable submatrix determining method provided in the embodiment of the present application, where the embodiment relates to how to determine, according to each sub-information codeword included in an information codeword to be encoded and a row check submatrix corresponding to each sub-information codeword, one possible implementation manner of the intermediate variable submatrix corresponding to the row check submatrix, where based on the foregoing embodiment, as shown in fig. 5, the foregoing S201 may include:
S501, performing cyclic shift on each sub-information codeword according to the row check sub-matrix to obtain a cyclic shift result corresponding to each sub-information codeword.
In order to reduce the resource consumption in the channel coding process and improve the operation efficiency, in the channel coding device 100 of fig. 1, the computation of the intermediate variable submatrix may be performed according to the row check submatrix L i,j For each sub-information codeword s j And performing cyclic shift, and determining a cyclic shift result corresponding to each sub-information codeword. A cyclic shift operation is used instead of a multiplication operation in calculating the intermediate variable sub-matrix using equation (1).
S502, performing bitwise exclusive OR on the cyclic shift result corresponding to each sub-information codeword to determine an intermediate sub-matrix corresponding to the row check sub-matrix.
The cyclic shift result corresponding to each sub-information codeword is bitwise exclusive-ored in the channel coding device 100, and multiplexing superposition is adopted in time sequence instead of the accumulation operation in the process of calculating the intermediate variable sub-matrix in (1) to determine the row check sub-matrix L i,x Corresponding intermediate variable sub-matrix b i 。
In the embodiment of the application, each sub-information codeword is subjected to cyclic shift according to the row check sub-matrix to obtain a cyclic shift result corresponding to each sub-information codeword, and the cyclic shift result corresponding to each sub-information codeword is further subjected to bitwise exclusive or to determine an intermediate variable sub-matrix corresponding to the row check sub-matrix. The cyclic shift operation is used for replacing multiplication operation, the bitwise exclusive OR is used for replacing accumulation operation, so that the resource consumption in the channel coding process is reduced, and the channel coding efficiency is further improved.
In one embodiment, as shown in fig. 6, a channel coding device 600 is provided, the device 600 comprising a first calculator 601, a second calculator 602 and an output device 603.
The first calculator 601 is configured to determine an intermediate variable sub-matrix corresponding to the row check sub-matrix according to each sub-information codeword included in the information codeword to be encoded and the row check sub-matrix corresponding to each sub-information codeword.
And a second calculator 602, configured to determine sub-check bit codewords corresponding to each intermediate variable sub-matrix according to the relationship between each row of check sub-matrices and the encoded information codeword corresponding to the information codeword to be encoded, and each intermediate variable sub-matrix.
And the output device 603 is configured to obtain an encoded information codeword corresponding to the information codeword to be encoded according to the sub-check bit codeword corresponding to each intermediate variable sub-matrix and each sub-information codeword.
In one embodiment, the second calculator 602 is configured to determine the first target expression according to a relationship between each row of the check sub-matrix and the information codeword to be encoded.
A second calculator 602, configured to determine, according to the first target expression, a sub-parity bit codeword corresponding to each intermediate variable sub-matrix.
In one embodiment, the second calculator 602 is configured to determine the second target expression value according to a relationship between each row of the check sub-matrix and the information codeword to be encoded.
And a second calculator 602, configured to determine, according to the second target expression, a sub-parity codeword corresponding to each sub-information codeword.
In one embodiment, the first calculator 601 is configured to perform cyclic shift on each sub-information codeword according to the row check sub-matrix, so as to obtain a cyclic shift result corresponding to each sub-information codeword.
The first calculator 601 is configured to bitwise exclusive-or the cyclic shift result corresponding to each sub-information codeword, so as to determine an intermediate sub-matrix corresponding to the row check sub-matrix.
In one embodiment, the channel encoding apparatus 600 further includes an intermediate variable register and a controller, where the intermediate variable register is connected to the first calculator 601, the second calculator 602, and the controller 603.
The intermediate variable register is configured to receive a first instruction sent by the controller, acquire an intermediate variable submatrix in the first calculator 601 according to the first instruction, and store the intermediate variable submatrix.
A second calculator 602 for obtaining an intermediate variable sub-matrix in the intermediate variable register.
In this embodiment, after the first calculator 601 determines each intermediate variable submatrix, the controller may send a first instruction to the intermediate variable register, instruct the intermediate variable register to acquire the intermediate variable submatrix in the first calculator 601, and store the intermediate variable submatrix. Alternatively, the intermediate variable submatrix may actively send the intermediate variable submatrix to the second calculator 602, and the second calculator 602 may also actively obtain the intermediate variable submatrix from the intermediate variable register.
In the embodiment of the application, the intermediate variable sub-matrix generated in the channel coding process is effectively stored by adding the intermediate variable register and the controller in the channel coding device, so that the reliability and the safety of the channel coding device are improved.
In one embodiment, the channel encoding device 600 further includes a check bit codeword register, and the check bit codeword register is connected to the second calculator 602, the output device 603, and the controller.
And the check bit code word register is used for receiving a second instruction sent by the controller, acquiring the sub check bit code word in the second calculator 602 according to the second instruction, and storing Chu Zi check bit code words.
And the output device 603 is used for acquiring the sub check bit code words in the check bit code word register.
In this embodiment, after the second calculator 602 determines the sub-parity codeword, the parity codeword register may obtain the sub-parity codeword in the second calculator 602 according to the second instruction sent by the controller and store the sub-parity codeword, and the output device 603 may obtain the sub-parity codeword from the parity codeword register. Alternatively, the output device 603 may also receive the sub-check bit codeword transmitted by the check bit codeword register.
In the embodiment of the application, the sub check bit code words generated in the channel coding process are effectively stored by adding the sub check bit code word register, so that the reliability and the safety of the channel coding device are improved.
In one embodiment, the apparatus further includes a row check sub-matrix register, and the row check sub-matrix register is connected to the first calculator 601 and the controller.
And the row check sub-matrix register is used for receiving a third instruction sent by the controller and sending the row check sub-matrix to the first calculator according to the third instruction.
The first calculator 601 is configured to receive a row check sub-matrix sent by the row check sub-matrix register.
Optionally, the row check sub-matrix register may also store a check matrix, and split the check matrix according to a second preset splitting rule to obtain a row check sub-matrix.
In the embodiment of the application, the row check sub-matrix register is arranged in the channel coding device, so that the check matrix and the row check sub-matrix which are needed in the channel coding process are effectively stored, and the reliability and the safety of the channel coding device are improved.
In one embodiment, the apparatus 600 further comprises a sub-information codeword register, which is connected to the controller, the first calculator 601, and the output means 603.
The sub-information code word register is used for receiving a fourth instruction sent by the controller, receiving an information code word to be encoded according to the fourth instruction, splitting the information code word to be encoded into sub-information code words, and sending the sub-information code words to the output device and the first calculator.
A first calculator 601 is configured to obtain each sub-information codeword in the sub-information codeword register.
In this embodiment, the first calculator 601 may obtain each sub-information codeword from the sub-information codeword register. Alternatively, the first calculator 601 may also receive the sub-information codeword transmitted by the sub-information codeword register.
In the embodiment of the application, the sub-information code word register is arranged in the channel coding device, so that the sub-information code words needed in the channel coding process are effectively stored, and the reliability and the safety of the channel coding device are improved.
Alternatively, the structure of the channel coding device may also be the structure shown in the device 700 provided in fig. 7, and includes a first calculator 701, a second calculator 702, an output device 703, a controller 704, an intermediate variable register 705, a check bit codeword register 706, a row check sub-matrix register 707, and a sub-information codeword register 708. In the channel coding apparatus 700, the first calculator 701 may include m first calculating units for calculating each intermediate variable submatrix; the second calculator 702 may include m second calculation units, which are used to calculate each sub-parity codeword, where the process of calculating the sub-parity codeword by the second calculation units may use the bidirectional recursive operation, and the multiple second calculation units may perform calculation synchronously; the intermediate variable register 705 may include m intermediate variable registering units for storing respective intermediate variable submatrices; the parity codeword register 706 may include m parity codeword registering units for storing respective sub parity codewords.
In the channel coding device, the process of calculating the intermediate variable sub-matrix by each first calculating unit and the process of checking the intermediate variable sub-matrix by each second calculating unit as a codeword can be performed simultaneously. For example, when the first calculation unit completes a part of the intermediate variable sub-matrix b i After calculation of (a), the part of the intermediate variable sub-matrix b i Sent to the intermediate variable register 705, each second calculation unit in the second calculator 702 acquires b stored in the intermediate variable register 705 i Then, the calculation of the sub-check bit code word is started, and at the same time, the first calculation unit in the first calculator continues to perform the residual intermediate variable sub-matrix b i Each calculator and registerThe memory works simultaneously, and the efficiency of channel coding is further improved. In addition, when channel coding is performed on different information code words to be coded, the number of each first computing unit and each second computing unit can be reconstructed according to the number of intermediate variable submatrices and the number of sub check bit code words, so that the flexibility of channel decoding by using the channel decoding device 700 is improved.
It should be understood that, although the steps in the flowcharts related to the above embodiments are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.
In one embodiment, a computer device is provided comprising a memory and a processor, the memory having stored therein a computer program, the processor when executing the computer program performing the steps of:
determining an intermediate sub-matrix corresponding to the row check sub-matrix according to each sub-information codeword included in the information codeword to be coded and the row check sub-matrix corresponding to each sub-information codeword;
determining sub-check bit code words corresponding to each intermediate variable sub-matrix according to the relation between each row of check sub-matrix and the code information code words corresponding to the code information code words to be coded and each intermediate variable sub-matrix;
and obtaining the code information code word corresponding to the information code word to be coded according to the sub check bit code word corresponding to each intermediate variable sub matrix and each sub information code word.
In one embodiment, the processor when executing the computer program further performs the steps of:
determining a first target expression according to the relation between each row of check sub-matrixes and the coding information code words corresponding to the information code words to be coded; the first target expression is used for representing the relation among the sub-check bit codeword corresponding to the current first intermediate variable sub-matrix, the sub-check bit codeword corresponding to the last intermediate variable sub-matrix of the first intermediate variable sub-matrix and the first intermediate variable sub-matrix, wherein the first intermediate variable sub-matrix is the first intermediate variable sub-matrix in the intermediate variable sub-matrix to be determined currently;
And determining the sub check bit code words corresponding to the intermediate variable sub matrixes according to the first target expression.
In one embodiment, the processor when executing the computer program further performs the steps of:
determining a second target expression value according to the relation between each row of check sub-matrix and the coding information code word corresponding to the information code word to be coded; the second target expression is used for representing the relation between the sub-check bit codeword corresponding to the current second intermediate variable sub-matrix, the last intermediate variable sub-matrix of the second intermediate variable sub-matrix and the sub-check bit codeword corresponding to the last intermediate variable sub-matrix of the second intermediate variable sub-matrix, and the second intermediate variable sub-matrix is the last intermediate variable sub-matrix in the intermediate variable sub-matrix to be determined currently;
and determining the sub check bit code words corresponding to the sub information code words according to the second target expression.
In one embodiment, the processor when executing the computer program further performs the steps of:
according to the row check sub-matrix, carrying out cyclic shift on each sub-information codeword to obtain a cyclic shift result corresponding to each sub-information codeword;
and carrying out bitwise exclusive OR on the cyclic shift result corresponding to each sub-information codeword to determine an intermediate sub-matrix corresponding to the row check sub-matrix.
In one embodiment, a computer readable storage medium is provided having a computer program stored thereon, which when executed by a processor, performs the steps of:
determining an intermediate sub-matrix corresponding to the row check sub-matrix according to each sub-information codeword included in the information codeword to be coded and the row check sub-matrix corresponding to each sub-information codeword;
determining sub-check bit code words corresponding to each intermediate variable sub-matrix according to the relation between each row of check sub-matrix and the code information code words corresponding to the code information code words to be coded and each intermediate variable sub-matrix;
and obtaining the code information code word corresponding to the information code word to be coded according to the sub check bit code word corresponding to each intermediate variable sub matrix and each sub information code word.
In one embodiment, the computer program when executed by the processor further performs the steps of:
determining a first target expression according to the relation between each row of check sub-matrixes and the coding information code words corresponding to the information code words to be coded; the first target expression is used for representing the relation among the sub-check bit codeword corresponding to the current first intermediate variable sub-matrix, the sub-check bit codeword corresponding to the last intermediate variable sub-matrix of the first intermediate variable sub-matrix and the first intermediate variable sub-matrix, wherein the first intermediate variable sub-matrix is the first intermediate variable sub-matrix in the intermediate variable sub-matrix to be determined currently;
And determining the sub check bit code words corresponding to the intermediate variable sub matrixes according to the first target expression.
In one embodiment, the computer program when executed by the processor further performs the steps of:
determining a second target expression value according to the relation between each row of check sub-matrix and the coding information code word corresponding to the information code word to be coded; the second target expression is used for representing the relation between the sub-check bit codeword corresponding to the current second intermediate variable sub-matrix, the last intermediate variable sub-matrix of the second intermediate variable sub-matrix and the sub-check bit codeword corresponding to the last intermediate variable sub-matrix of the second intermediate variable sub-matrix, and the second intermediate variable sub-matrix is the last intermediate variable sub-matrix in the intermediate variable sub-matrix to be determined currently;
and determining the sub check bit code words corresponding to the sub information code words according to the second target expression.
In one embodiment, the computer program when executed by the processor further performs the steps of:
according to the row check sub-matrix, carrying out cyclic shift on each sub-information codeword to obtain a cyclic shift result corresponding to each sub-information codeword;
and carrying out bitwise exclusive OR on the cyclic shift result corresponding to each sub-information codeword to determine an intermediate sub-matrix corresponding to the row check sub-matrix.
In one embodiment, a computer program product is provided comprising a computer program which, when executed by a processor, performs the steps of:
determining an intermediate sub-matrix corresponding to the row check sub-matrix according to each sub-information codeword included in the information codeword to be coded and the row check sub-matrix corresponding to each sub-information codeword;
determining sub-check bit code words corresponding to each intermediate variable sub-matrix according to the relation between each row of check sub-matrix and the code information code words corresponding to the code information code words to be coded and each intermediate variable sub-matrix;
and obtaining the code information code word corresponding to the information code word to be coded according to the sub check bit code word corresponding to each intermediate variable sub matrix and each sub information code word.
In one embodiment, the computer program when executed by the processor further performs the steps of:
determining a first target expression according to the relation between each row of check sub-matrixes and the coding information code words corresponding to the information code words to be coded; the first target expression is used for representing the relation among the sub-check bit codeword corresponding to the current first intermediate variable sub-matrix, the sub-check bit codeword corresponding to the last intermediate variable sub-matrix of the first intermediate variable sub-matrix and the first intermediate variable sub-matrix, wherein the first intermediate variable sub-matrix is the first intermediate variable sub-matrix in the intermediate variable sub-matrix to be determined currently;
And determining the sub check bit code words corresponding to the intermediate variable sub matrixes according to the first target expression.
In one embodiment, the computer program when executed by the processor further performs the steps of:
determining a second target expression value according to the relation between each row of check sub-matrix and the coding information code word corresponding to the information code word to be coded; the second target expression is used for representing the relation between the sub-check bit codeword corresponding to the current second intermediate variable sub-matrix, the last intermediate variable sub-matrix of the second intermediate variable sub-matrix and the sub-check bit codeword corresponding to the last intermediate variable sub-matrix of the second intermediate variable sub-matrix, and the second intermediate variable sub-matrix is the last intermediate variable sub-matrix in the intermediate variable sub-matrix to be determined currently;
and determining the sub check bit code words corresponding to the sub information code words according to the second target expression.
In one embodiment, the computer program when executed by the processor further performs the steps of:
according to the row check sub-matrix, carrying out cyclic shift on each sub-information codeword to obtain a cyclic shift result corresponding to each sub-information codeword;
and carrying out bitwise exclusive OR on the cyclic shift result corresponding to each sub-information codeword to determine an intermediate sub-matrix corresponding to the row check sub-matrix.
It should be noted that, user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, presented data, etc.) referred to in the present application are information and data authorized by the user or sufficiently authorized by each party.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, database, or other medium used in the various embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high density embedded nonvolatile Memory, resistive random access Memory (ReRAM), magnetic random access Memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric Memory (Ferroelectric Random Access Memory, FRAM), phase change Memory (Phase Change Memory, PCM), graphene Memory, and the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, and the like. By way of illustration, and not limitation, RAM can be in the form of a variety of forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), and the like. The databases referred to in the various embodiments provided herein may include at least one of relational databases and non-relational databases. The non-relational database may include, but is not limited to, a blockchain-based distributed database, and the like. The processors referred to in the embodiments provided herein may be general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic units, quantum computing-based data processing logic units, etc., without being limited thereto.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the present application. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application shall be subject to the appended claims.

Claims (10)

1. A channel coding method based on reconfigurable processor architecture design, the method comprising:
determining an intermediate variable sub-matrix corresponding to each row of the sub-matrix according to each sub-information code word included in the information code word to be coded and the row of the sub-matrix corresponding to each sub-information code word;
determining sub-check bit code words corresponding to the intermediate variable sub-matrices according to the relation between the row check sub-matrices and the coding information code words corresponding to the information code words to be coded and the intermediate variable sub-matrices;
And obtaining the coding information code word corresponding to the information code word to be coded according to the sub check bit code word corresponding to each intermediate variable sub matrix and each sub information code word.
2. The method according to claim 1, wherein determining the sub-check bit codeword corresponding to each intermediate variable sub-matrix according to the relationship between each row check sub-matrix and the encoded information codeword corresponding to the information codeword to be encoded and each intermediate variable sub-matrix comprises:
determining a first target expression according to the relation between each row of check sub-matrix and the coding information code word corresponding to the information code word to be coded; the first target expression is used for representing the relation among a sub-check bit codeword corresponding to a current first intermediate variable sub-matrix, a sub-check bit codeword corresponding to a last intermediate variable sub-matrix of a first intermediate variable sub-matrix and the first intermediate variable sub-matrix, wherein the first intermediate variable sub-matrix is a first intermediate variable sub-matrix in the intermediate variable sub-matrix to be determined currently;
and determining the sub-check bit code words corresponding to the intermediate variable sub-matrixes according to the first target expression.
3. The method according to claim 1, wherein the determining the sub-check bit codeword corresponding to each sub-information codeword according to the relation between the row check sub-matrix corresponding to each sub-information codeword and the encoded information codeword corresponding to the information codeword to be encoded and the intermediate variable sub-matrix corresponding to each sub-information codeword comprises:
determining a second target expression value according to the relation between each row of check sub-matrix and the coding information code word corresponding to the information code word to be coded; the second target expression is used for representing the relation between a sub-check bit codeword corresponding to a current second intermediate variable sub-matrix, a last intermediate variable sub-matrix of the second intermediate variable sub-matrix and a sub-check bit codeword corresponding to a last intermediate variable sub-matrix of the second intermediate variable sub-matrix, wherein the second intermediate variable sub-matrix is the last intermediate variable sub-matrix in the intermediate variable sub-matrix to be determined currently;
and determining the sub check bit code word corresponding to each sub information code word according to the second target expression.
4. A method according to any one of claims 1-3, wherein the determining an intermediate variable sub-matrix corresponding to the row check sub-matrix according to each sub-information codeword included in the information codeword to be encoded and the row check sub-matrix corresponding to each sub-information codeword includes:
Performing cyclic shift on each sub-information codeword according to the row check sub-matrix to obtain a cyclic shift result corresponding to each sub-information codeword;
and carrying out bitwise exclusive OR on the cyclic shift result corresponding to each sub-information codeword to determine an intermediate sub-matrix corresponding to the row check sub-matrix.
5. A channel coding device designed based on a reconfigurable processor architecture, the device comprising a first calculator, a second calculator, and an output device;
the first calculator is used for determining an intermediate variable sub-matrix corresponding to the row check sub-matrix according to each sub-information codeword included in the information codeword to be coded and the row check sub-matrix corresponding to each sub-information codeword;
the second calculator is configured to determine sub-check bit codewords corresponding to the intermediate variable sub-matrices according to a relationship between the row check sub-matrices and the encoded information codeword corresponding to the information codeword to be encoded, and the intermediate variable sub-matrices;
and the output device is used for obtaining the code information code word corresponding to the information code word to be coded according to the sub check bit code word corresponding to each intermediate variable sub matrix and each sub information code word.
6. The apparatus of claim 5, wherein the second calculator is configured to determine a first target expression based on a relationship between each of the row check sub-matrices and the information codeword to be encoded; the first target expression is used for representing the relation among a sub-check bit codeword corresponding to a current first intermediate variable sub-matrix, a sub-check bit codeword corresponding to a last intermediate variable sub-matrix of a first intermediate variable sub-matrix and the first intermediate variable sub-matrix, wherein the first intermediate variable sub-matrix is a first intermediate variable sub-matrix in the intermediate variable sub-matrix to be determined currently;
the second calculator is configured to determine, according to the first target expression, a sub-parity bit codeword corresponding to each intermediate variable sub-matrix.
7. The apparatus of claim 5, wherein the second calculator is configured to determine a second target expression value based on a relationship between each of the row check sub-matrices and the information codeword to be encoded; the second target expression is used for representing the relation between a sub-check bit codeword corresponding to a current second intermediate variable sub-matrix, a last intermediate variable sub-matrix of the second intermediate variable sub-matrix and a sub-check bit codeword corresponding to a last intermediate variable sub-matrix of the second intermediate variable sub-matrix, wherein the second intermediate variable sub-matrix is the last intermediate variable sub-matrix in the intermediate variable sub-matrix to be determined currently;
And the second calculator is used for determining the sub check bit code words corresponding to the sub information code words according to the second target expression.
8. The apparatus of claim 5, wherein the first calculator is configured to perform cyclic shift on each of the sub-information codewords according to the row check sub-matrix to obtain a cyclic shift result corresponding to each of the sub-information codewords;
the first calculator is configured to bitwise exclusive-or the cyclic shift result corresponding to each sub-information codeword, so as to determine an intermediate sub-matrix corresponding to the row check sub-matrix.
9. The apparatus of claim 5, further comprising an intermediate variable register and a controller, the intermediate variable register being coupled to the first calculator, the second calculator, the controller;
the intermediate variable register is used for receiving a first instruction sent by the controller, acquiring the intermediate variable submatrix in the first calculator according to the first instruction, and storing the intermediate variable submatrix;
the second calculator is configured to obtain the intermediate variable submatrix in the intermediate variable register.
10. The apparatus of claim 5, further comprising a check bit codeword register, a row check sub-matrix register, and a sub-information codeword register, the check bit codeword register coupled to the second calculator, the output device, the controller, the row check sub-matrix register coupled to the first calculator, the controller, the sub-information codeword register coupled to the controller, the first calculator, the output device;
the check bit code word register is used for receiving a second instruction sent by the controller, acquiring the sub-check bit code words in the second calculator according to the second instruction, and sending the sub-check bit code words to the output device;
the row check sub-matrix register is used for receiving a third instruction sent by the controller and sending the row check sub-matrix to the first calculator according to the third instruction;
the sub-information code word register is configured to receive a fourth instruction sent by the controller, receive the information code word to be encoded according to the fourth instruction, split the information code word to be encoded into sub-information code words, and send the sub-information code words to the output device and the first calculator.
CN202310347187.1A 2023-04-03 2023-04-03 Channel coding method and device based on reconfigurable processor architecture design Pending CN116566544A (en)

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