CN116565002A - High gate lock threshold split gate power MOSFET structure and manufacturing method - Google Patents

High gate lock threshold split gate power MOSFET structure and manufacturing method Download PDF

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Publication number
CN116565002A
CN116565002A CN202310676040.7A CN202310676040A CN116565002A CN 116565002 A CN116565002 A CN 116565002A CN 202310676040 A CN202310676040 A CN 202310676040A CN 116565002 A CN116565002 A CN 116565002A
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gate
semiconductor layer
field plate
layer
oxide layer
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焦世龙
黄子伦
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Suzhou Juqian Semiconductor Co ltd
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Suzhou Juqian Semiconductor Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
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Abstract

The invention discloses a split gate power MOSFET structure with high gate locking threshold and a manufacturing method, wherein the split gate power MOSFET structure comprises the following components: the doped semiconductor layer, the second semiconductor layer and the third semiconductor layer are sequentially arranged on the substrate from bottom to top, and the doping concentration of the second semiconductor layer is higher than that of the first semiconductor layer and the third semiconductor layer; and a plurality of gate trenches arranged in the first semiconductor layer to the third semiconductor layer, wherein a field plate structure, an isolation layer and a gate structure are formed in the gate trenches from bottom to top, the top transverse dimension of a field plate electrode in the field plate structure is larger than the bottom transverse dimension, and the thickness of a field plate oxide layer is larger than the thickness of the gate oxide layer. The invention can obviously improve the anti-gate locking capability of the device, and can further reduce the on-resistance under the condition of obtaining the same reverse voltage resistance, thereby improving the comprehensive performance of the SGT device.

Description

High gate lock threshold split gate power MOSFET structure and manufacturing method
Technical Field
The invention relates to the technical field of semiconductors, in particular to a split gate power MOSFET structure with a high gate locking threshold and a manufacturing method thereof.
Background
Split gate power MOSFETs (SGTs) have low on-resistance and high power density characteristics, and dynamic latch up (latch up) performance enhancement has been a focus of research.
The most remarkable structural characteristic of the split gate power MOSFET is that an upper layer of polycrystal and a lower layer of polycrystal are arranged in the groove, and an oxide layer is arranged between the upper layer and the lower layer of polycrystal. Wherein, the upper layer polycrystal is used as a gate electrode, and is combined with gate oxide at the side wall of the upper part of the groove to form a conductive channel (channel) under proper bias; the lower layer polycrystal is zero potential and forms a polycrystal field plate with the oxide layer at the side wall of the bottom of the groove. Under the condition of high potential of the drain electrode, a depletion region is generated in an epitaxial material region between the polycrystalline electrodes at the bottom of the adjacent trenches, so that potential drop is borne, namely reverse withstand voltage utilizes the charge balance principle. Therefore, an epitaxial layer with higher doping concentration than that of a common trench MOSFET can be adopted, and the epitaxial layer has lower on-resistance or higher current density under the condition of obtaining the same voltage resistance, thereby being beneficial to high-power application.
On the other hand, thermal effects in the device operating state will become prominent due to the increase in current density. The most important is that in the high power switch conversion state, the voltage superposed by the inductive load causes avalanche breakdown and potential gate lock effect, and the latter can lead to the current to be increased sharply, so that the device is permanently damaged by heat.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a high gate lock threshold split gate power MOSFET structure and a manufacturing method thereof.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
the invention provides a split gate power MOSFET structure with a high gate lock threshold, which comprises the following components:
the semiconductor device comprises a substrate, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer, wherein the first semiconductor layer, the second semiconductor layer and the third semiconductor layer are sequentially arranged on the substrate from bottom to top, and the doping concentration of the second semiconductor layer is larger than that of the first semiconductor layer and the third semiconductor layer;
the gate trenches are downwards arranged in the first semiconductor layer to the third semiconductor layer from the surface of the third semiconductor layer, a field plate structure, an isolation layer and a gate structure are formed in the gate trenches from bottom to top, the field plate structure comprises a field plate electrode and a field plate oxide layer, the gate structure comprises a gate electrode and a gate oxide layer, the top transverse dimension of the field plate electrode is larger than the bottom transverse dimension, and the thickness of the field plate oxide layer is larger than that of the gate oxide layer.
Further, the method further comprises the following steps: and the band-shaped doped region is formed between the adjacent gate trenches and is formed by diffusing doped impurities in the second semiconductor layer into the first semiconductor layer and the third semiconductor layer, a body region of a second doping type is arranged in the third semiconductor layer between the adjacent gate trenches, the top of the band-shaped doped region is positioned below the bottom of the body region at intervals, and the bottom of the band-shaped doped region is higher than the bottom of the gate trench in the longitudinal direction.
Further, the band-shaped doped region has an impurity concentration distribution decreasing from the second semiconductor layer to both sides of the first semiconductor layer and the third semiconductor layer, and a highest impurity concentration in the band-shaped doped region is lower than a critical concentration; the critical concentration satisfies: when the highest impurity concentration in the band-shaped doped region is in the critical concentration state, avalanche breakdown simultaneously occurs in the band-shaped doped region and a corner region between the bottom and the side surface of the gate trench under the action of back pressure.
Further, the field plate electrode comprises a T shape with a wide upper part and a narrow lower part, and the thickness of the field plate oxide layer corresponding to the horizontal upper part of the T shape is smaller than that of the field plate oxide layer corresponding to the vertical lower part of the T shape.
Further, in the longitudinal direction, the top of the field plate electrode is lower than the top of the band-shaped doped region, and the bottom of the field plate electrode is lower than the bottom of the band-shaped doped region.
The invention also provides a manufacturing method of the split gate power MOSFET structure with the high gate locking threshold value, which comprises the following steps:
providing a substrate;
sequentially forming a first semiconductor layer, a second semiconductor layer and a third semiconductor layer with a first doping type on the substrate, wherein the doping concentration of the second semiconductor layer is larger than that of the first semiconductor layer and the third semiconductor layer;
forming a plurality of gate trenches in the first to third semiconductor layers downward from the surface of the third semiconductor layer;
and forming a field plate structure, an isolation layer and a gate structure in the gate groove from bottom to top, wherein the field plate structure comprises a field plate electrode and a field plate oxide layer, the gate structure comprises a gate electrode and a gate oxide layer, the top transverse dimension of the field plate electrode is larger than the bottom transverse dimension, and the thickness of the field plate oxide layer is larger than the thickness of the gate oxide layer.
Further, an epitaxial process is adopted to sequentially form the first semiconductor layer to the third semiconductor layer which are in the same quality as the substrate material on the substrate, and the doping concentration in the third semiconductor layer is equal to or higher than that in the first semiconductor layer.
Further, the forming a field plate structure, an isolation layer and a gate structure in the gate trench from bottom to top specifically includes:
forming a first oxide layer on the inner wall of the gate trench;
filling a first field plate electrode material layer in the gate trench inside the first oxide layer;
firstly partially back-etching the first field plate electrode material layer and the first oxide layer, and then removing the rest first field plate electrode material layer;
forming a second oxide layer on the exposed side wall of the gate trench and the surface of the rest first oxide layer, so as to form a T-shaped cavity with wide upper part and narrow lower part in the gate trench inside the second oxide layer;
filling a second field plate electrode material layer in the T-shaped cavity;
partially back-etching the second field plate electrode material layer and the second oxide layer until the top of the residual first oxide layer is exposed, forming a T-shaped field plate electrode by the residual second field plate electrode material layer, and forming a field plate oxide layer by the residual first oxide layer and the residual second oxide layer, thereby forming the field plate structure;
forming a third oxide layer on the exposed side wall of the gate trench and on the top of the field plate structure;
filling a gate electrode material layer in the gate trench inside the third oxide layer;
and removing the redundant third oxide layer and the gate electrode material layer at the top of the gate trench, forming a gate electrode by the gate electrode material layer, forming a gate oxide layer by the third oxide layer on the side wall of the gate trench, thereby forming the gate structure, and forming an isolation layer by the third oxide layer on the top of the field plate structure.
Further, the method further comprises the following steps:
forming a body region of a second doping type in the third semiconductor layer between adjacent gate trenches by ion implantation of the second doping type and annealing;
forming a source region of a first doping type in the third semiconductor layer above the body region by ion implantation of the first doping type and annealing;
forming an interlayer dielectric layer on the surface of the third semiconductor layer;
forming a conductive contact hole connected to the body region on the surface of the interlayer dielectric layer;
forming a metal layer which is contacted with the top of the conductive contact hole on the surface of the interlayer dielectric layer;
wherein the impurity doped in the second semiconductor layer is diffused into the first semiconductor layer and the third semiconductor layer by a thermal action in the manufacturing process to form a band-shaped doped region between adjacent gate trenches, and the band-shaped doped region has an impurity concentration distribution decreasing from the second semiconductor layer to both sides of the first semiconductor layer and the third semiconductor layer, and the top of the band-shaped doped region is spaced below the bottom of the body region and is higher than the top of the field plate electrode in the longitudinal direction, and the bottom of the band-shaped doped region is higher than the bottom of the gate trench and is higher than the bottom of the field plate electrode in the longitudinal direction.
Further, the highest impurity concentration in the band-shaped doped region is set to be the upper limit that the band-shaped doped region does not undergo avalanche breakdown before the corner region between the bottom and the side surface of the gate trench under the action of back pressure.
According to the technical scheme, the doped first semiconductor layer to the third semiconductor layer with the sandwich structure are formed on the substrate between the adjacent gate trenches, so that the doping concentration of the second semiconductor layer is higher than that of the first semiconductor layer and the third semiconductor layer at two sides, and the gate trenches are arranged in the first semiconductor layer to the third semiconductor layer, so that the field plate electrode at the lower part of the gate trench is of a T-shaped structure with the top transverse dimension being higher than the bottom transverse dimension, and the anti-gate locking capability (namely the high gate locking threshold) of the split gate power MOSFET device can be remarkably improved; meanwhile, since the second semiconductor layer having a high doping concentration is in a current path in a forward conduction state, the resistivity on the region can be reduced, and the on-resistance can be further reduced under the condition that the same reverse withstand voltage is obtained. Thus, the present invention can improve the overall performance of SGT devices.
Drawings
FIG. 1 is a schematic diagram of a split-gate power MOSFET structure with a high gate lock threshold in accordance with a preferred embodiment of the present invention;
fig. 2-7 are process flow diagrams of a method for fabricating a split-gate power MOSFET structure with a high gate lock threshold in accordance with a preferred embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. Unless otherwise defined, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and the like means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof without precluding other elements or items.
The various portions of the MOSFET device can be constructed of materials well known to those skilled in the art unless specifically indicated below. The semiconductor material may include, for example, group III-V semiconductors such as GaAs, inP, gaN, siC, and group IV semiconductors such as Si, ge, and the like. The gate electrode material may be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a laminated gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, tiN, taSiN, hfSiN, tiSiN, tiCN, taAlC, tiAlN, taN, ptSi x 、Ni 3 Si, pt, ru, W, combinations of the various conductive materials, and the like. The gate oxide layer material can be made of SiO 2 Or dielectric constant greater than SiO 2 For example, oxide, nitride, oxynitride, silicate, aluminate, titanate, and the like. Further, the gate oxide layer may be formed of not only a material known to those skilled in the art but also a material for a gate oxide layer developed in the future.
The first doping type may be one of N-type and P-type, and the second doping type may be the other of N-type and P-type. The N-type may be formed by implanting N-type dopants (e.g., P, as, etc.) into the semiconductor material. The P-type may be formed by implanting a P-type dopant (e.g., B, etc.) into the semiconductor material. The above may be understood by reference to known techniques.
The following describes the embodiments of the present invention in further detail with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 is a schematic diagram of a split-gate power MOSFET structure with a high gate lock threshold according to a preferred embodiment of the invention. As shown in fig. 1, a high gate lock threshold split gate power MOSFET structure of the present invention includes: a first semiconductor layer 10, a second semiconductor layer 11, a third semiconductor layer 12 and a gate trench 21 provided on a substrate (Si Sub).
The first semiconductor layer 10 to the third semiconductor layer 12 are semiconductor materials of a first doping type, and are sequentially disposed on the substrate from bottom to top. Taking the first doping type as N-type and the second doping type as P-type as an example, the N-type doping concentration of the second semiconductor layer 11 is greater than the N-type doping concentration of the first semiconductor layer 10 and the N-type doping concentration of the third semiconductor layer 12. Thereby forming the N-type doped first to third semiconductor layers 10 to 12 of the sandwich structure.
Further, the N-type doping concentration in the third semiconductor layer 12 is equal to or higher than the N-type doping concentration in the first semiconductor layer 10.
The gate trenches 21 are plural. The gate trench 21 is provided in the first semiconductor layer 10 to the third semiconductor layer 12 downward from the surface of the third semiconductor layer 12. The gate trench 21 has field plate structures (32, 31), isolation layers 43 and gate structures (42, 41) formed therein from bottom to top; a field plate structure is located in a lower portion of the gate trench 21 and a gate structure is located in an upper portion of the gate trench 21, the field plate structure being separated from the gate structure by an isolation layer 43. Wherein the field plate structure comprises a field plate electrode 32 and a field plate oxide layer 31, and the gate structure comprises a gate electrode 42 and a gate oxide layer 41. Also, the field plate electrode 32 has a structural feature of being wide at the top (upper) lateral dimension (width) of the field plate electrode 32 being larger than the bottom (lower) lateral dimension (width). In other words, the thickness of the field plate oxide layer 31 corresponding to the top position of the field plate electrode 32 is smaller than the thickness of the field plate oxide layer 31 corresponding to the bottom position of the field plate electrode 32. But the overall thickness of the field plate oxide layer 31 is greater than the thickness of the gate oxide layer 41.
In some embodiments, a band-shaped doped region 112 is also provided in the first to third semiconductor layers 10 to 12 between adjacent gate trenches 21. The band-shaped doped region 112 is a continuous region, and the top boundary of the band-shaped doped region 112 is located in the third semiconductor layer 12, and the bottom boundary of the band-shaped doped region 112 is located in the first semiconductor layer 10. The band-shaped doped region 112 is formed by diffusing the doped impurities in the second semiconductor layer 11 into the first semiconductor layer 10 and the third semiconductor layer 12, that is, the range of the band-shaped doped region 112 is defined by the boundary of the diffusion regions formed by diffusing the doped impurities in the second semiconductor layer 11 into the first semiconductor layer 10 and the third semiconductor layer 12 on both sides. Such diffusion of the dopant impurities is formed under the effect of heat, that is, the band-shaped dopant region 112 is formed by the extent of diffusion of the dopant impurities due to the effect of heat generated on the second semiconductor layer 11.
In some embodiments, a P-doped body region 51 is also provided in the third semiconductor layer 12 between adjacent gate trenches 21; the top of the band-shaped doped region 112 is spaced below the bottom of the body region 51, and the bottom of the band-shaped doped region 112 is longitudinally higher than the bottom of the gate trench 21.
In some embodiments, the band-shaped doped region 112 has an impurity concentration distribution decreasing from the second semiconductor layer 11 to both sides of the first semiconductor layer 10 and the third semiconductor layer 12, and the highest impurity concentration in the band-shaped doped region 112 is lower than the critical concentration and is kept at a certain difference from the critical concentration. Wherein, the critical concentration satisfies: when the highest impurity concentration in the band-shaped doped region 112 is in the critical concentration state, avalanche breakdown will occur simultaneously when the band-shaped doped region 112 and the corner region 211 between the bottom and the side of the gate trench 21 are under high back pressure. I.e., the highest impurity concentration in the band-shaped doped region 112, is such that under back pressure the band-shaped doped region 112 does not undergo avalanche breakdown prior to the corner region 211 between the bottom and the sides of the gate trench 21. Further, by providing the band-shaped doped region 112 with an impurity concentration distribution which decreases from the second semiconductor layer 11 to both sides of the first semiconductor layer 10 and the third semiconductor layer 12, on-resistance in the current path can be further reduced, and thus the avalanche breakdown and gate lock effect resistance can be further improved.
Please refer to fig. 1. In some embodiments, the field plate electrode 32 includes a T-shaped structure with a wide top and a narrow bottom, and the width of the field plate electrode 32 corresponding to the horizontal upper portion of the T-shape is greater than the width of the field plate electrode 32 corresponding to the vertical lower portion of the T-shape, and the thickness of the field plate oxide layer 31 corresponding to the horizontal upper portion of the T-shape is less than the thickness of the field plate oxide layer 31 corresponding to the vertical lower portion of the T-shape.
In some embodiments, the top of the field plate electrode 32 is lower than the top of the band-shaped doped region 112 in the longitudinal direction, and the bottom of the field plate electrode 32 is lower than the bottom of the band-shaped doped region 112.
In some embodiments, an N-doped source region 52 is also provided in the third semiconductor layer 12 over the body region 51.
Further, an interlayer dielectric layer 53 (ILD) is provided on the surface of the third semiconductor layer 12. The interlayer dielectric layer 53 may be made of, for example, NSG (undoped silicate glass) or BPSG (borophosphosilicate glass).
Further, a conductive contact hole with a bottom connected to the body region 51 is also provided on the surface of the interlayer dielectric layer 53. A tungsten plug (tungsten plug) 62, for example, may be provided in the contact hole.
Further, a front metal layer 61 (pattern) is provided on the surface of the interlayer dielectric layer 53. The metal layer 61 is in contact with the top of the tungsten plug 62 of the conductive contact hole.
Further, a passivation layer (not shown) is further provided on the surface of the interlayer dielectric layer 53, and the passivation layer covers the metal layer 61 to protect the device.
In some embodiments, the first to third semiconductor layers 10 to 12 may be formed using a material that is homogenous with the substrate. For example, the substrate may be a silicon substrate (Si Sub), and the first to third semiconductor layers 10 to 12 may be epitaxial layers of a homogeneous silicon material having respective doping concentrations and thicknesses formed on the silicon substrate.
The following describes a method for manufacturing a split-gate power MOSFET structure with high gate lock threshold in detail by means of the following detailed description and the accompanying drawings.
Referring to fig. 2-7, fig. 2-7 are process flow diagrams of a method for fabricating a split-gate power MOSFET structure with a high gate lock threshold according to a preferred embodiment of the invention. As shown in fig. 2-7, a method of manufacturing a high gate lock threshold split gate power MOSFET structure of the present invention may be used to manufacture a high gate lock threshold split gate power MOSFET structure such as that shown in fig. 1, and may include the steps of:
step S1: a substrate is provided, on which a first semiconductor layer 10, a second semiconductor layer 11 and a third semiconductor layer 12 of a first doping type are sequentially formed, and the doping concentration of the second semiconductor layer 11 is made larger than the doping concentrations of the first semiconductor layer 10 and the third semiconductor layer 12.
Please refer to fig. 2. A silicon substrate (Si Sub) may be used, and an epitaxial process may be used to sequentially form the first to third semiconductor layers 10 to 12 on the silicon substrate, which are homogeneous with the silicon substrate material. For example, a first semiconductor layer 10 having a certain N-type doping concentration and thickness may be first epitaxially grown on the surface of an N-type silicon substrate. Then, a second semiconductor layer 11 having a higher N-type doping concentration with respect to the first semiconductor layer 10 continues to be epitaxial on the surface of the first semiconductor layer 10. Subsequently, a third semiconductor layer 12 having a doping concentration smaller than that of the N-type doping of the second semiconductor layer 11 is further epitaxially grown on the surface of the second semiconductor layer 11, and the doping concentration of the third semiconductor layer 12 may be made equal to or higher than that of the first semiconductor layer 10.
Step S2: a plurality of gate trenches 21 in the first to third semiconductor layers 10 to 12 are formed downward from the surface of the third semiconductor layer 12.
Please refer to fig. 3. Next, a plurality of parallel gate trenches 21 may be formed downward on the surface of the third semiconductor layer 12 using photolithography and etching processes, and the formed gate trenches 21 are located in the first to third semiconductor layers 10 to 12.
Step S3: a field plate structure, an isolation layer 43, and a gate structure are formed in the gate trench 21 from bottom to top, such that the field plate structure includes the field plate electrode 32 and the field plate oxide layer 31, such that the gate structure includes the gate electrode 42 and the gate oxide layer 41, such that the top lateral dimension of the field plate electrode 32 is greater than the bottom lateral dimension, and such that the thickness of the field plate oxide layer 31 is greater than the thickness of the gate oxide layer 41.
Then, a deposition process may be used to form a first oxide layer 22 on the inner wall of the gate trench 21, and to fill a first field plate electrode material layer (not shown) in the gate trench 21 within the first oxide layer 22.
Next, the first field plate electrode material layer and the first oxide layer 22 are partially etched back, and etched back to a position where the top portions of the first oxide layer 22 and the first field plate electrode material layer are flush (or substantially flush) with the top portion of the second semiconductor layer 11.
Then, the remaining first field plate electrode material layer may be removed by continuing the etch back, leaving the remaining first oxide layer 22 with top level with the top of the second semiconductor layer 11, as shown in fig. 3.
Please refer to fig. 4. Next, a deposition process may be used to form a second oxide layer on the exposed sidewalls of the gate trench 21 and on the remaining surface of the first oxide layer 22. With the first oxide layer 22 protruding on a portion of the sidewall of the gate trench 21, a protruding second oxide layer step morphology can be created on the sidewall of the gate trench 21 after the second oxide layer deposition, thereby forming a T-shaped cavity with a wide upper portion and a narrow lower portion in the gate trench 21 within the second oxide layer.
A deposition process may then be used to fill the T-shaped cavity with a second layer of field plate electrode material.
Then, the second field plate electrode material layer and the second oxide layer are partially etched back until the top of the original remaining first oxide layer 22 is exposed by etching back the second oxide layer, so that the field plate oxide layer 31 having a step shape (i.e., a T-shaped reverse shape) with a narrow top and a wide bottom in the lateral thickness is formed by the remaining first oxide layer 22 and the remaining second oxide layer together. Meanwhile, after the second field plate electrode material layer is etched back, the top of the second field plate electrode material layer is located at a position slightly lower than the top of the field plate oxide layer 31, namely, a certain step height difference is formed between the top of the second field plate electrode material layer and the top of the field plate oxide layer 31, so that a field plate electrode 32 which is surrounded in the field plate oxide layer 31 and has a T-shaped form with wide upper part and narrow lower part is formed by the remaining second field plate electrode material layer, and a field plate structure is formed at the lower part of the gate trench 21.
The first field plate electrode material layer and the second field plate electrode material layer can be made of doped polysilicon. The first oxide layer 22 and the second oxide layer may be made of SiO 2 。
Please refer to fig. 5. Then, an oxidation process may be used to expose the upper side of the gate trench 21SiO formation on the walls and on top of the field plate structure 2 And a third oxide layer. Wherein it is desirable to make the thickness of the third oxide layer on the sidewalls of the gate trench 21 smaller than the minimum thickness of the field plate oxide layer 31 on the sidewalls of the gate trench 21 (i.e., smaller than the thickness of the field plate oxide layer 31 at the T-shaped horizontal portion corresponding to the field plate electrode 32).
A deposition process may then be used to fill the gate trench 21 with a layer of gate electrode material within the third oxide layer.
Next, a chemical mechanical polishing process may be used to remove the excess third oxide layer and gate electrode material layer material on top of the gate trench 21, so that the top surfaces of the third oxide layer and gate electrode material layer exposed on top of the gate trench 21 are flush with the surface of the third semiconductor layer 12. Thus, a gate oxide layer 41 is formed from the third oxide layer located at the upper side wall in the gate trench 21, and a gate electrode 42 is formed from the gate electrode material layer inside the gate oxide layer 41, thereby forming a gate structure; and spacer 43 is formed from a third oxide layer located between the top of the field plate structure and the bottom of gate electrode 42.
The gate electrode material layer may be doped polysilicon. The third oxide layer material can be SiO 2 。
Step S4: ion implantation of the second doping type is used and annealed to form body regions 51 of the second doping type in the third semiconductor layer 12 between adjacent gate trenches 21.
Please refer to fig. 6. Then, ion implantation may be performed downward from the surface of the third semiconductor layer 12 between the adjacent gate trenches 21 using P-type ions B, and annealed to form a P-type body region 51 in the third semiconductor layer 12.
Step S5: ion implantation of the first doping type is used and annealed to form source regions 52 of the first doping type in the third semiconductor layer 12 over the body regions 51.
Please refer to fig. 6. An N-type source region 52 may be formed in the third semiconductor layer 12 above the body region 51 by ion implantation of N-type ions As down from the surface of the third semiconductor layer 12 between adjacent gate trenches 21 and annealing.
Thereafter, the following steps may also be continued:
step S6: an interlayer dielectric layer 53 is formed on the surface of the third semiconductor layer 12.
Please refer to fig. 6. An interlayer dielectric layer (ILD) 53 may be formed by depositing NSG and BPSG and reflow on the surface of the third semiconductor layer 12.
Step S7: conductive contact holes connected to the body region 51 are formed on the surface of the interlayer dielectric layer 53.
Please refer to fig. 7. Then, a contact hole may be formed on the surface of the interlayer dielectric layer 53 over the body region 51 and the source region 52 using photolithography and etching processes, and the bottom of the contact hole may be brought into contact with the top of the body region 51. Next, ti and TiN layers may be sequentially formed on the inner walls of the contact holes, tungsten may be filled in the contact holes inside the TiN layers, and then, by chemical mechanical polishing, the excessive Ti, tiN and tungsten materials on the surface of the interlayer dielectric layer 53 outside the contact holes may be removed, and a tungsten plug 62 may be formed in the contact holes, thereby forming conductive contact holes of the bottom connection body region 51.
Step S8: a metal layer 61 is formed on the surface of the interlayer dielectric layer 53 in contact with the top of the conductive contact hole.
Please refer to fig. 7. Finally, a sputtering process may be used to form, for example, an AlSiCu metal layer 61 on the surface of the interlayer dielectric layer 53, and to bring the AlSiCu metal layer 61 into contact with the top of the tungsten plug 62 of the conductive contact hole. Subsequently, the AlSiCu metal layer 61 may be patterned by photolithography and etching processes, and a passivation layer pattern (not shown) may be formed on the surface of the interlayer dielectric layer 53. The metal layer 61 is covered with a passivation layer to protect the device.
Note that the dopant impurities in the second semiconductor layer 11 are diffused into the first semiconductor layer 10 and the third semiconductor layer 12 by the thermal effects of the above-described gate oxide oxidation, P-type and N-type ion implantation, annealing, ILD dielectric deposition and reflow, and other thermal processing processes in the device manufacturing process, thereby forming the band-shaped dopant regions 112 between the adjacent gate trenches 21.
It can be seen that the intermediate layer of the second semiconductor layer 11, which is originally relatively thin in fig. 2, is thermally subjected to annealing or the like, and is developed into a band-shaped doped region 112 having a concentration gradient and spatial distribution in the longitudinal direction, as shown in fig. 6 and 7. The band-shaped doped region 112 has an impurity concentration distribution which decreases from the second semiconductor layer 11 to both sides of the first semiconductor layer 10 and the third semiconductor layer 12, and the top of the band-shaped doped region 112 is spaced below the bottom of the body region 51 and higher than the top of the field plate electrode 32 in the longitudinal direction, while the bottom of the band-shaped doped region 112 is higher than the bottom of the gate trench 21 in the longitudinal direction and higher than the bottom of the field plate electrode 32. The highest impurity concentration in the band-shaped doped region 112 is such that the band-shaped doped region 112 does not undergo avalanche breakdown before the corner region 211 (refer to fig. 1) between the bottom and the side of the gate trench 21 under the back pressure.
By controlling the thermal budget in the processing process, impurities in the middle layer of the second semiconductor layer 11 with higher doping concentration in the sandwich structure can not excessively diffuse, and the problems of reduced device withstand voltage or overlarge leakage current are avoided.
In summary, the doping concentration of the second semiconductor layer 11 is greater than the doping concentrations of the first semiconductor layer 10 and the third semiconductor layer 12 on both sides by forming the first semiconductor layer 10 to the third semiconductor layer 12 with a sandwich structure on the substrate between the adjacent gate trenches 21, and the gate trench 21 is arranged in the first semiconductor layer 10 to the third semiconductor layer 12, so that the field plate electrode 32 at the lower part of the gate trench 21 has a T-shaped structure with a top transverse dimension greater than a bottom transverse dimension, and the gate locking resistance of the split gate power MOSFET device can be remarkably improved; meanwhile, since the second semiconductor layer 11 having a high doping concentration is in a current path in a forward on state, the resistivity on the region can be reduced, and the on-resistance can be further reduced under the condition that the same reverse withstand voltage is obtained. Therefore, the invention improves the comprehensive performance of SGT devices, is beneficial to high-power application, and is particularly suitable for the scene of high inductance load.
While embodiments of the present invention have been described in detail hereinabove, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. It is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention described herein is capable of other embodiments and of being practiced or of being carried out in various ways.

Claims (10)

1. A high gate lock threshold split gate power MOSFET structure comprising:
the semiconductor device comprises a substrate, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer, wherein the first semiconductor layer, the second semiconductor layer and the third semiconductor layer are sequentially arranged on the substrate from bottom to top, and the doping concentration of the second semiconductor layer is larger than that of the first semiconductor layer and the third semiconductor layer;
the gate trenches are downwards arranged in the first semiconductor layer to the third semiconductor layer from the surface of the third semiconductor layer, a field plate structure, an isolation layer and a gate structure are formed in the gate trenches from bottom to top, the field plate structure comprises a field plate electrode and a field plate oxide layer, the gate structure comprises a gate electrode and a gate oxide layer, the top transverse dimension of the field plate electrode is larger than the bottom transverse dimension, and the thickness of the field plate oxide layer is larger than that of the gate oxide layer.
2. The Gao Shan lock threshold split gate power MOSFET structure of claim 1, further comprising: and the band-shaped doped region is formed between the adjacent gate trenches and is formed by diffusing doped impurities in the second semiconductor layer into the first semiconductor layer and the third semiconductor layer, a body region of a second doping type is arranged in the third semiconductor layer between the adjacent gate trenches, the top of the band-shaped doped region is positioned below the bottom of the body region at intervals, and the bottom of the band-shaped doped region is higher than the bottom of the gate trench in the longitudinal direction.
3. The Gao Shan threshold split gate power MOSFET structure of claim 2, wherein the band-shaped doped region has an impurity concentration profile that decreases from the second semiconductor layer to both sides of the first and third semiconductor layers, and a highest impurity concentration in the band-shaped doped region is below a critical concentration; the critical concentration satisfies: when the highest impurity concentration in the band-shaped doped region is in the critical concentration state, avalanche breakdown simultaneously occurs in the band-shaped doped region and a corner region between the bottom and the side surface of the gate trench under the action of back pressure.
4. The Gao Shan lock threshold split gate power MOSFET structure of claim 1, wherein said field plate electrode comprises a T-shape having a wide top and a narrow bottom, and wherein a thickness of said field plate oxide layer corresponding to a horizontal upper portion of said T-shape is less than a thickness of said field plate oxide layer corresponding to a vertical lower portion of said T-shape.
5. The Gao Shan threshold split gate power MOSFET structure of claim 2, wherein in a longitudinal direction, a top of the field plate electrode is lower than a top of the band-shaped doped region and a bottom of the field plate electrode is lower than a bottom of the band-shaped doped region.
6. A method for fabricating a high gate lock threshold split gate power MOSFET structure comprising:
providing a substrate;
sequentially forming a first semiconductor layer, a second semiconductor layer and a third semiconductor layer with a first doping type on the substrate, wherein the doping concentration of the second semiconductor layer is larger than that of the first semiconductor layer and the third semiconductor layer;
forming a plurality of gate trenches in the first to third semiconductor layers downward from the surface of the third semiconductor layer;
and forming a field plate structure, an isolation layer and a gate structure in the gate groove from bottom to top, wherein the field plate structure comprises a field plate electrode and a field plate oxide layer, the gate structure comprises a gate electrode and a gate oxide layer, the top transverse dimension of the field plate electrode is larger than the bottom transverse dimension, and the thickness of the field plate oxide layer is larger than the thickness of the gate oxide layer.
7. The method of claim 6, wherein the first semiconductor layer to the third semiconductor layer are sequentially formed on the substrate with a same material as the substrate by using an epitaxial process, and a doping concentration in the third semiconductor layer is equal to or higher than a doping concentration in the first semiconductor layer.
8. The method for manufacturing the Gao Shan threshold split gate power MOSFET structure of claim 6, wherein forming the field plate structure, the isolation layer and the gate structure in the gate trench from bottom to top comprises:
forming a first oxide layer on the inner wall of the gate trench;
filling a first field plate electrode material layer in the gate trench inside the first oxide layer;
firstly partially back-etching the first field plate electrode material layer and the first oxide layer, and then removing the rest first field plate electrode material layer;
forming a second oxide layer on the exposed side wall of the gate trench and the surface of the rest first oxide layer, so as to form a T-shaped cavity with wide upper part and narrow lower part in the gate trench inside the second oxide layer;
filling a second field plate electrode material layer in the T-shaped cavity;
partially back-etching the second field plate electrode material layer and the second oxide layer until the top of the residual first oxide layer is exposed, forming a T-shaped field plate electrode by the residual second field plate electrode material layer, and forming a field plate oxide layer by the residual first oxide layer and the residual second oxide layer, thereby forming the field plate structure;
forming a third oxide layer on the exposed side wall of the gate trench and on the top of the field plate structure;
filling a gate electrode material layer in the gate trench inside the third oxide layer;
and removing the redundant third oxide layer and the gate electrode material layer at the top of the gate trench, forming a gate electrode by the gate electrode material layer, forming a gate oxide layer by the third oxide layer on the side wall of the gate trench, thereby forming the gate structure, and forming an isolation layer by the third oxide layer on the top of the field plate structure.
9. The method of fabricating a Gao Shan lock threshold split gate power MOSFET structure of claim 6, further comprising:
forming a body region of a second doping type in the third semiconductor layer between adjacent gate trenches by ion implantation of the second doping type and annealing;
forming a source region of a first doping type in the third semiconductor layer above the body region by ion implantation of the first doping type and annealing;
forming an interlayer dielectric layer on the surface of the third semiconductor layer;
forming a conductive contact hole connected to the body region on the surface of the interlayer dielectric layer;
forming a metal layer which is contacted with the top of the conductive contact hole on the surface of the interlayer dielectric layer;
wherein the impurity doped in the second semiconductor layer is diffused into the first semiconductor layer and the third semiconductor layer by a thermal action in the manufacturing process to form a band-shaped doped region between adjacent gate trenches, and the band-shaped doped region has an impurity concentration distribution decreasing from the second semiconductor layer to both sides of the first semiconductor layer and the third semiconductor layer, and the top of the band-shaped doped region is spaced below the bottom of the body region and is higher than the top of the field plate electrode in the longitudinal direction, and the bottom of the band-shaped doped region is higher than the bottom of the gate trench and is higher than the bottom of the field plate electrode in the longitudinal direction.
10. The method of claim 9, wherein the highest impurity concentration in the strip doped region is such that under back-pressure, the strip doped region does not undergo avalanche breakdown prior to the corner region between the bottom and the sides of the gate trench.
CN202310676040.7A 2023-06-08 2023-06-08 High gate lock threshold split gate power MOSFET structure and manufacturing method Pending CN116565002A (en)

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