CN116545389A

CN116545389A - Dual-path noise cancellation circuit and noise cancellation method based on transformer structure

Info

Publication number: CN116545389A
Application number: CN202310603031.5A
Authority: CN
Inventors: 洪祥; 刘志哲; 曹玉雄; 陈林辉; 程帅; 田帆; 陈宇铮
Original assignee: Tuowei Electronic Technology Shanghai Co ltd
Current assignee: Tuowei Electronic Technology Shanghai Co ltd
Priority date: 2023-05-25
Filing date: 2023-05-25
Publication date: 2023-08-04

Abstract

The embodiment of the disclosure provides a double-path noise cancellation circuit and a noise cancellation method based on a transformer structure. The method comprises an input port, a transformer, a common-source differential amplifier, a common-gate differential amplifier, a first matching network and a second matching network; wherein, the transformer includes: a primary winding, a first secondary winding, a second secondary winding, a third secondary winding and a fourth secondary winding; the common source differential amplifier includes: the first MOS tube and the second MOS tube; the common-gate differential amplifier includes: the third MOS tube and the fourth MOS tube. In this way, the noise coefficient of the amplifier can be effectively reduced in the millimeter wave frequency band, the sensitivity of the receiver is improved, the complexity of the circuit is reduced, and the reliability of the circuit is improved.

Description

Dual-path noise cancellation circuit and noise cancellation method based on transformer structure

Technical Field

The disclosure relates to the technical field of integrated circuits, and further relates to the technical field of low-noise amplifier circuits, in particular to a two-way noise cancellation circuit based on a transformer structure and a noise cancellation method.

Background

The low noise amplifier is used as the first stage circuit of the radio frequency receiving system and has decisive effect on the noise performance of the receiving system. The low noise amplifier is mainly used for amplifying weak signals for reprocessing by a later-stage circuit. However, the noise of the low noise amplifier is amplified by the post-stage circuit together with the signal at the same time of amplifying the signal, so that the noise figure of the low noise amplifier needs to be optimized. In addition, in addition to noise reduction, corresponding optimization is required in terms of input impedance matching, gain, bandwidth, power consumption, linearity, and the like.

Because it is difficult to realize broadband and low noise simultaneously by using a low noise amplifier with a common gate amplification or common source amplification architecture, a noise cancellation technique has been developed in recent years that uses the phase difference between noise and signals between different modules of a circuit to enhance the superposition of output signals and cancel the superposition of noise.

Noise cancellation techniques have been shown to achieve low noise amplification over a wide frequency range at the same time, the basic principle being to introduce an additional signal path to replicate the thermal noise introduced by the cascode or common source amplifier head stage and cancel it at the amplifier output. But this also presents a new problem in that the noise introduced by the extra signal path cannot be removed.

The following are several common noise cancellation schemes:

1. a one-way noise cancellation scheme based on resistive feedback. The main channel noise that utilizes auxiliary amplifier branch road to offset main amplifier MOS pipe, and the shortcoming of this scheme lies in:

the auxiliary amplifier generates additional noise, and the noise cancellation benefit is not obvious; a feedback branch is constructed using resistors, but the resistors are a very noisy device, which worsens the noise figure.

2. And a single-path noise cancellation scheme based on a cascode structure. The disadvantage of this solution, which mainly relies on the coincidence of the gains of the two branches, the opposite phase cancellation of the noise, is:

only channel noise of one MOS tube can be counteracted, noise can be deteriorated by the additionally introduced other amplifier, and the gain of noise counteraction is not obvious; and the scheme tends to be ideal and is difficult to realize in practical application.

3. A two-way noise cancellation scheme based on a resistive feedback structure. According to the scheme, channel noises of the MOS transistors of the two paths of amplifiers are respectively counteracted by introducing the two noise counteraction branches, and the gain and the phase of the two branches are adjustable mainly by introducing the driving amplifier, so that the noise counteraction effect is improved, and the scheme has the defects that:

the MOS tube is of a common source stage structure with feedback, and the introduced resistor device can generate extra noise; meanwhile, the two introduced driving amplifiers can additionally increase the power consumption and the complexity of the circuit, and in addition, the robustness of the whole circuit structure can be reduced along with the improvement of the complexity of the circuit.

Disclosure of Invention

The disclosure provides a two-way noise cancellation circuit and a noise cancellation method based on a transformer structure.

According to a first aspect of the present disclosure, a two-way noise cancellation circuit based on a transformer structure is provided. The circuit comprises:

the device comprises an input port, a transformer, a common-source differential amplifier, a common-gate differential amplifier, a first matching network and a second matching network; wherein,,

the transformer includes: a primary winding, a first secondary winding, a second secondary winding, a third secondary winding and a fourth secondary winding;

the common source differential amplifier includes: the first MOS tube and the second MOS tube;

the common-gate differential amplifier includes: the third MOS tube and the fourth MOS tube;

one end of the primary winding is electrically connected with the input port, and the other end of the primary winding is grounded;

one end of the first auxiliary winding is electrically connected with the grid electrode of the first MOS tube, and the other end of the first auxiliary winding is electrically connected with the grid electrode of the second MOS tube;

one end of the third auxiliary winding is electrically connected with the source electrode of the first MOS tube, and the other end of the third auxiliary winding is electrically connected with the source electrode of the second MOS tube;

one end of the second auxiliary winding is electrically connected with the source electrode of the third MOS tube, and the other end of the second auxiliary winding is electrically connected with the source electrode of the fourth MOS tube;

one end of the fourth auxiliary winding is electrically connected with the grid electrode of the third MOS tube, and the other end of the fourth auxiliary winding is electrically connected with the grid electrode of the fourth MOS tube;

drains of the first MOS tube and the second MOS tube are respectively connected to a first matching network;

and the drains of the third MOS tube and the fourth MOS tube are respectively connected into a second matching network.

In some implementations of the first aspect, the first secondary winding is provided with a tap for providing a dc bias for the gates of the first MOS transistor and the second MOS transistor; the fourth auxiliary winding is provided with a tap and is used for providing direct current bias for the grid electrodes of the third MOS tube and the fourth MOS tube; the connecting terminals in the middle of the coil of the second auxiliary winding and the third auxiliary winding are grounded.

In some implementations of the first aspect, the circuit further includes:

vout-port, vout-port being connected with the first matching network;

and the Vout+ port is connected with the second matching network.

In some implementations of the first aspect, the first matching network is configured to convert a differential signal output by the common source differential amplifier to a single-ended signal; the differential signals output by the drains of the first MOS tube and the second MOS tube in the common source differential amplifier are converted into single-ended signals by the first matching network and then output from the Vout-port. The second matching network is used for converting the differential signal output by the common-gate differential amplifier into a single-ended signal; and differential signals output by the drains of the third MOS tube and the fourth MOS tube in the common-gate differential amplifier are converted into single-ended signals by the second matching network and then output from the Vout+ port.

In some implementations of the first aspect, the third and fourth auxiliary windings forward couple noise N1 generated by the first MOS transistor to the gate of the third MOS transistor, such that noise N1' appears in the third MOS transistor; noise N1' is reversely transmitted to the drain electrode of the third MOS tube and is output from the drain electrode of the third MOS tube; the noise N1 output by the drain electrode of the first MOS tube is the same as the noise N1' output by the drain electrode of the third MOS tube in the transmission direction and the phase. The third auxiliary winding and the fourth auxiliary winding forward couple noise N2 generated by the second MOS tube to the grid electrode of the fourth MOS tube, so that noise N2' appears in the fourth MOS tube; noise N2' is reversely transmitted to the drain electrode of the fourth MOS tube and is output from the drain electrode of the fourth MOS tube; the noise N2 output by the drain electrode of the second MOS tube is the same as the noise N2' output by the drain electrode of the fourth MOS tube in the transmission direction and in the same phase.

In some implementations of the first aspect, the first auxiliary winding and the second auxiliary winding forward couple noise N3 generated by the third MOS transistor to the gate of the first MOS transistor, so that noise N3' appears in the first MOS transistor; noise N3' is reversely transmitted to the drain electrode of the first MOS tube and is output from the drain electrode of the first MOS tube; the noise N3 output by the drain electrode of the third MOS tube is the same as the noise N3' output by the drain electrode of the first MOS tube in the transmission direction and the phase. The first auxiliary winding and the second auxiliary winding forward couple noise N4 generated by the fourth MOS tube to the grid electrode of the second MOS tube, so that noise N4' appears in the second MOS tube; noise N4' is reversely transmitted to the drain electrode of the second MOS tube and is output from the drain electrode of the second MOS tube; the transmission direction of noise N4 output by the drain electrode of the fourth MOS tube is the same as that of noise N4' output by the drain electrode of the second MOS tube, and the phases are the same.

In some implementations of the first aspect, the input signal is transmitted to the first secondary winding via the primary winding and to the common source differential amplifier via the first secondary winding; in the common source differential amplifier, the first MOS tube and the second MOS tube are input from the grid electrode, and output from the drain electrode; the input signal is transmitted to the second auxiliary winding through the primary winding and is transmitted to the common-gate differential amplifier through the second auxiliary winding; in the common-gate differential amplifier, the common-gate differential amplifier is input from the source electrode of the third MOS tube and the source electrode of the fourth MOS tube, and is output from the drain electrode; the signal transmission directions of the drain electrodes of the first MOS tube and the third MOS tube are the same, and the phases are opposite; the signal transmission directions of the drain electrodes of the second MOS tube and the fourth MOS tube are the same, and the phases are opposite.

In some implementations of the first aspect, the primary winding and the first secondary winding forward couple the input signal to gates of the first MOS transistor and the second MOS transistor; the primary winding and the third secondary winding reversely couple input signals to sources of the first MOS tube and the second MOS tube; to increase the voltage difference between the gate and the source and the gain of the common-source differential amplifier; the primary winding and the fourth secondary winding are used for coupling input signals to the grid electrodes of the third MOS tube and the fourth MOS tube in the forward direction; the primary winding and the second secondary winding reversely couple input signals to sources of the third MOS tube and the fourth MOS tube; so as to increase the voltage difference between the gate and the source and the gain of the common-gate differential amplifier.

According to a second aspect of the present disclosure, there is provided a noise cancellation method applying the two-way noise cancellation circuit based on the transformer structure as described above. The method comprises the following steps:

the input signal is transmitted to a first auxiliary winding through a primary winding of a transformer, is transmitted to a common source differential amplifier through the first auxiliary winding, and is output to a first matching network after being processed by the common source differential amplifier;

the input signal is transmitted to a second winding subgroup through the primary winding of the transformer, is transmitted to the common-gate differential amplifier through the second auxiliary winding, and is output to a second matching network after being processed by the common-gate differential amplifier;

noise N1 generated by a first MOS tube in the common-source differential amplifier is transmitted to a grid electrode of a third MOS tube in the common-gate differential amplifier through forward coupling of a third auxiliary winding and a fourth auxiliary winding in a transformer, is reversely transmitted to a drain electrode of the common-gate differential amplifier through the third MOS tube, and is output from the drain electrode of the common-gate differential amplifier;

noise N2 generated by the second MOS tube in the common-source differential amplifier is transmitted to the grid electrode of the fourth MOS tube in the common-gate differential amplifier through the forward coupling of the third auxiliary winding and the fourth auxiliary winding in the transformer, is reversely transmitted to the drain electrode of the fourth MOS tube and is output from the drain electrode of the fourth MOS tube;

noise N3 generated by a third MOS tube in the common-gate differential amplifier is transmitted to the grid electrode of the first MOS tube in the common-source differential amplifier through forward coupling of a first auxiliary winding and a second auxiliary winding in the transformer, is reversely transmitted to the drain electrode of the first MOS tube and is output from the drain electrode of the first MOS tube;

noise N4 generated by a fourth MOS tube in the common-gate differential amplifier is transmitted to the grid electrode of a second MOS tube in the common-source differential amplifier through forward coupling of a first auxiliary winding and a second auxiliary winding in a transformer, is reversely transmitted to the drain electrode of the common-gate differential amplifier through the second MOS tube, and is output from the drain electrode of the common-gate differential amplifier; wherein,,

the signals output by the drains of the first MOS tube and the third MOS tube are in opposite phase, and the noise is in phase;

the signals output by the drains of the second MOS tube and the fourth MOS tube are in opposite phase, and the noise is in phase;

signals and noise output by the first MOS tube and the second MOS tube are converted into single-ended signals in the first matching network and then output from the Vout-port;

the signals and noise output by the third MOS tube and the fourth MOS tube are converted into single-ended signals in the second matching network and then output from the Vout+ port;

according to the phase characteristics, the signals output by the Vout-port and the Vout+ port are in anti-phase, and the noise is in-phase, so that the noise is mutually counteracted.

In some implementations of the second aspect, the method further includes:

the primary winding and the first secondary winding in the transformer forward couple input signals to the grid electrodes of the first MOS tube and the second MOS tube in the common source differential amplifier; a primary winding and a third secondary winding in the transformer reversely couple input signals to sources of the first MOS tube and the second MOS tube; to increase the voltage difference between the gate and the source and the gain of the common-source differential amplifier;

the primary winding and the fourth secondary winding in the transformer forward couple input signals to the gates of the third MOS tube and the fourth MOS tube in the common-gate differential amplifier; the primary winding and the second secondary winding in the transformer reversely couple input signals to sources of the third MOS tube and the fourth MOS tube; so as to increase the voltage difference between the gate and the source and the gain of the common-gate differential amplifier.

In the method, the transformer with completely symmetrical structure is matched with the common-source differential amplifier and the common-gate differential amplifier to realize double-path noise cancellation, and compared with a double-path noise cancellation method in the prior art, the method does not depend on a feedback resistor, does not need to additionally introduce a driving amplifier to adjust amplitude and phase, does not additionally introduce noise, can effectively reduce noise coefficient and improves the performance of a receiver; meanwhile, the circuit structure is simplified, and the circuit complexity is reduced.

It should be understood that what is described in this summary is not intended to limit the critical or essential features of the embodiments of the disclosure nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. For a better understanding of the present disclosure, and without limiting the disclosure thereto, the same or similar reference numerals denote the same or similar elements, wherein:

fig. 1 shows an exemplary circuit diagram of a two-way noise cancellation circuit based on a transformer structure provided by an embodiment of the present disclosure;

fig. 2 shows an exemplary layout of a transformer in a two-way noise cancellation circuit based on a transformer structure provided by an embodiment of the present disclosure.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments in this disclosure without inventive faculty, are intended to be within the scope of this disclosure.

In addition, the term "and/or" herein is merely an association relationship describing an association object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

In view of the problems mentioned in the background art, the present disclosure provides a two-way noise cancellation circuit and a noise cancellation method based on a transformer structure.

Specifically, the passive transformer with completely symmetrical structure is used for connecting the common-source differential amplifier and the common-gate differential amplifier, so that the double-path noise cancellation is realized, and the gain effect of the amplifier is improved.

Compared with the prior art, the method does not depend on a feedback resistor, does not need to additionally introduce a driving amplifier to adjust amplitude and phase, does not additionally introduce noise, can effectively reduce noise coefficient, and improves the performance of a receiver; meanwhile, the circuit structure is simplified, and the circuit complexity is reduced.

The following describes a two-way noise cancellation circuit and a noise cancellation method based on a transformer structure according to a preferred embodiment of the present disclosure in detail with reference to the accompanying drawings.

Fig. 1 shows an exemplary circuit diagram of a two-way noise cancellation circuit based on a transformer structure provided by an embodiment of the present disclosure; as shown in fig. 1, the two-way noise cancellation circuit based on the transformer structure may include:

the transformer includes: a primary winding L0, a first secondary winding L1, a second secondary winding L2, a third secondary winding L3 and a fourth secondary winding L4.

The common source differential amplifier includes: the first MOS tube M1 and the second MOS tube M2.

The common-gate differential amplifier includes: the third MOS tube M3 and the fourth MOS tube M4.

One end of the primary winding is electrically connected with the input port, and the other end of the primary winding is grounded.

One end of the first auxiliary winding L1 is electrically connected with the grid electrode of the first MOS tube M1, and the other end of the first auxiliary winding L1 is electrically connected with the grid electrode of the second MOS tube M2.

One end of the third auxiliary winding L3 is electrically connected with the source electrode of the first MOS tube M1, and the other end of the third auxiliary winding L3 is electrically connected with the source electrode of the second MOS tube M2.

One end of the second auxiliary winding L2 is electrically connected with the source electrode of the third MOS tube M3, and the other end of the second auxiliary winding L2 is electrically connected with the source electrode of the fourth MOS tube M4.

One end of the fourth auxiliary winding L4 is electrically connected with the grid electrode of the third MOS tube M3, and the other end of the fourth auxiliary winding L4 is electrically connected with the grid electrode of the fourth MOS tube M4.

Drains of the first MOS tube M1 and the second MOS tube M2 are respectively connected to a first matching network; drains of the third MOS transistor M3 and the fourth MOS transistor M4 are respectively connected to the second matching network.

Further, the first auxiliary winding L1 is provided with a tap for providing dc bias for the gates of the first MOS transistor M1 and the second MOS transistor M2. The fourth secondary winding L4 is provided with a tap for providing dc bias for the gates of the third MOS transistor M3 and the fourth MOS transistor M4.

Further, the wiring terminals in the middle of the coils of the second auxiliary winding L2 and the third auxiliary winding L3 are grounded, so that the potential requirements of the common source amplifier and MOS tubes in the common gate amplifier during normal operation are met.

It should be noted that, the transformer shown in fig. 1 is a multi-coil coupled transformer, and the primary winding and the secondary winding in the transformer may be composed of five corresponding inductance coils.

According to the embodiment of the disclosure, the feedback resistor is not needed, the drive amplifier is not needed to be additionally introduced for adjusting the amplitude and the phase, noise is not additionally introduced, the noise coefficient can be effectively reduced, the circuit power consumption is reduced, and the circuit structure is simplified.

In some embodiments, the two-way noise cancellation circuit based on the transformer structure may further include:

vout-port, vout-port being connected with the first matching network.

And the Vout+ port is connected with the second matching network.

Further, the first matching network is configured to convert a differential signal output by the common source differential amplifier into a single-ended signal; the differential signals output by the drains of the first MOS tube M1 and the second MOS tube M2 in the common source differential amplifier are converted into single-ended signals by the first matching network and then output from the Vout-port.

Further, the second matching network is configured to convert the differential signal output by the common-gate differential amplifier into a single-ended signal; the differential signals output by the drains of the third MOS tube M3 and the fourth MOS tube M4 in the common-gate differential amplifier are converted into single-ended signals by the second matching network and then output from the Vout+ port.

When signals are output in a difference mode between the Vout-port and the Vout plus port, the signals are overlapped, and due to the phase characteristics, noise in the signals can be offset. In particular, the method comprises the steps of,

channel noise in the MOS transistor can be equivalent to a noise current source connected across the drain and source of the transistor.

As shown In fig. 1, the channel noise In the first MOS transistor M1 may be equivalent to a noise current source In1, where the noise current source In1 generates noise N1 In the first MOS transistor M1, and the noise N1 is output from the drain of the first MOS transistor M1 to the first matching network along with the input signal.

A third auxiliary winding L3 and a fourth auxiliary winding L4 in the transformer forward couple noise N1 generated by the first MOS tube M1 to the grid electrode of the third MOS tube M3, so that noise N1' appears in the third MOS tube M3; at this time, the third MOS transistor M3 is equivalent to a common source amplifying circuit, so that the noise N1' is reversely transmitted to the drain thereof by the third MOS transistor M3 and is outputted to the first matching network from the drain thereof along with the input signal; the noise N1 output by the drain electrode of the first MOS tube M1 and the noise N1' output by the drain electrode of the third MOS tube M3 have the same transmission direction and the same phase. According to the phase characteristics, the noise N1 and the noise N1' will cancel each other at Vout-port, vout+ port.

As shown In fig. 1, the channel noise In the second MOS transistor M2 may be equivalent to a noise current source In2, where the noise current source In2 generates noise N2 In the second MOS transistor M2, and the noise N2 is output from the drain of the second MOS transistor M2 to the first matching network along with the input signal.

The third auxiliary winding L3 and the fourth auxiliary winding L4 in the transformer forward couple the noise N2 generated by the second MOS tube M2 to the grid electrode of the fourth MOS tube M4, so that the noise N2' appears in the fourth MOS tube M4; at this time, the fourth MOS transistor M4 is equivalent to a common source amplifying circuit, so that the noise N2' is reversely transmitted to the drain thereof by the fourth MOS transistor M4 and is output to the first matching network along with the input signal from the drain thereof; the noise N2 output by the drain electrode of the second MOS tube M2 is the same as the noise N2' output by the drain electrode of the fourth MOS tube M4 in the transmission direction and in the same phase. According to the phase characteristics, the noise N2 and the noise N2' will cancel each other at Vout-port, vout+ port.

As shown In fig. 1, the channel noise In the third MOS transistor M3 may be equivalent to a noise current source In3, where the noise current source In3 generates noise N3 In the third MOS transistor M3, and the noise N3 is output from the drain of the third MOS transistor M3 to the second matching network along with the input signal.

The first auxiliary winding L1 and the second auxiliary winding L2 in the transformer forward couple the noise N3 generated by the third MOS tube M3 to the grid electrode of the first MOS tube M1, so that the noise N3' appears in the first MOS tube M1; at this time, the first MOS transistor M1 is equivalent to a common source amplifying circuit, so that the noise N3' is reversely transmitted to the drain thereof by the first MOS transistor M1, and is output to the second matching network from the drain thereof along with the input signal; the noise N3 output by the drain electrode of the third MOS tube M3 is the same as the noise N3' output by the drain electrode of the first MOS tube M1 in transmission direction and in the same phase. According to the phase characteristics, the noise N3 and the noise N3' will cancel each other at Vout-port, vout+ port.

As shown In fig. 1, the channel noise In the fourth MOS transistor M4 may be equivalent to a noise current source In4, where the noise current source In4 generates noise N4 In the fourth MOS transistor M4, and the noise N4 is output from the drain of the fourth MOS transistor M4 to the second matching network along with the input signal.

The first auxiliary winding L1 and the second auxiliary winding L2 in the transformer forward couple the noise N4 generated by the fourth MOS tube M4 to the grid electrode of the second MOS tube M2, so that the noise N4' appears in the second MOS tube M2; at this time, the second MOS transistor M2 is equivalent to a common source amplifying circuit, so that the noise N4' is reversely transmitted to the drain thereof by the second MOS transistor M2, and is output to the second matching network from the drain thereof along with the input signal; the transmission direction of noise N4 output by the drain electrode of the fourth MOS tube M4 is the same as that of noise N4' output by the drain electrode of the second MOS tube M2, and the phases are the same. According to the phase characteristics, the noise N4 and the noise N4' will cancel each other at Vout-port, vout+ port.

According to the embodiment of the disclosure, the transformer with the complete symmetrical structure, the common-source differential amplifier and the common-gate differential amplifier which are symmetrically arranged at two sides of the transformer are utilized to realize double-path noise cancellation, so that the noise coefficient is effectively reduced, the complexity of a circuit is reduced, and the robustness of the circuit is improved.

It should be noted that, when noise cancellation is achieved, the dual-path noise cancellation circuit based on the transformer structure provided by the disclosure further has a function of improving the gain of the amplifier.

The gain of the booster amplifier is described in detail below in connection with fig. 1.

First, a transmission process of an input signal will be described.

As shown in fig. 1, an input signal is transmitted to a first auxiliary winding L1 through a primary winding L0, and is transmitted to a common source differential amplifier through the first auxiliary winding L1; in the common source differential amplifier, the first MOS tube M1 and the second MOS tube M2 are input from the grid electrode and output from the drain electrode; the input signal is transmitted from the drains of the first MOS tube M1 and the second MOS tube M2 to the first matching network, converted into a single-ended signal in the first matching network, and then transmitted to the Vout-port.

As shown in fig. 1, an input signal is transmitted to the second auxiliary winding L2 through the primary winding L0, and is transmitted to the common-gate differential amplifier through the second auxiliary winding L2; in the common-gate differential amplifier, the source electrode input and the drain electrode output of the third MOS tube M3 and the fourth MOS tube M4 are carried out; the input signal is transmitted to the second matching network from the drains of the third MOS tube M3 and the fourth MOS tube M4, and is converted into a single-ended signal in the second matching network and then transmitted to the Vout+ port.

The signal transmission directions output by the drains of the first MOS tube M1 and the third MOS tube M3 are the same, and the phases are opposite; the signal transmission directions of the drain electrodes of the second MOS tube M2 and the fourth MOS tube M4 are the same, and the phases are opposite.

The signal transmission process is clarified, and the gain boosting process of the amplifier is described below. The improvement of the gain of the common-source differential amplifier and the common-gate differential amplifier specifically includes:

a primary winding L0 and a first secondary winding L1 in the transformer forward couple input signals to the grid electrodes of a first MOS tube MI and a second MOS tube M2; the primary winding L0 and the third secondary winding L3 reversely couple input signals to sources of the first MOS tube MI and the second MOS tube M2; so as to increase the voltage difference between the gate and the source and the gain of the common-source differential amplifier.

A primary winding L0 and a fourth secondary winding L4 in the transformer forward couple input signals to the grids of the third MOS tube M3 and the fourth MOS tube M4; the primary winding L0 and the second secondary winding L2 reversely couple input signals to sources of the third MOS tube M3 and the fourth MOS tube M4; so as to increase the voltage difference between the gate and the source and the gain of the common-gate differential amplifier.

According to the embodiment of the disclosure, the effect of improving the voltage difference between the gate and the source and the gain of the amplifier is achieved by utilizing the phase characteristic of the amplifier and the coupling of the transformer and adopting a circuit structure with low complexity and easy realization.

As shown in fig. 1, the MOS transistors used in the preferred embodiment are all N-type MOS transistors.

It will be appreciated that P-type MOS transistors or other transistors capable of achieving the same effect may also be used.

The transformer mentioned in the above preferred embodiment is described in detail below with reference to fig. 2 in an exemplary layout.

As shown in fig. 2, the upper and lower parts of the transformer layout are in mirror symmetry structures, the left side of the upper part of the layout is one end of the positive pole of the primary winding L0, and the right side of the upper part of the layout is one end of the positive pole of the secondary windings L1, L2, L4 and L3 in sequence; the left side terminal of the lower part of the layout is the negative electrode end of the primary winding L0, and the right side terminal is the negative electrode end of the secondary windings L3, L4, L2 and L1 in sequence. Wherein,,

one end of the positive electrode of L0 is electrically connected with the input port, and one end of the negative electrode is grounded.

One end of the positive electrode of the L1 is electrically connected with the grid electrode of the first MOS tube M1, and one end of the negative electrode is electrically connected with the grid electrode of the second MOS tube M2.

One end of the positive electrode of the L2 is electrically connected with the source electrode of the third MOS tube M3, and one end of the negative electrode is electrically connected with the source electrode of the fourth MOS tube M4.

One end of the positive electrode of the L4 is electrically connected with the grid electrode of the fourth MOS tube M4, and one end of the negative electrode is electrically connected with the grid electrode of the third MOS tube M3.

One end of the positive electrode of the L3 is electrically connected with the source electrode of the second MOS tube M2, and one end of the negative electrode is electrically connected with the source electrode of the second MOS tube M1.

Further, as shown in fig. 2, at the position of the layout center line, the positive electrode wirings of the secondary winding L1 and the secondary winding L2 are exchanged, and the negative electrode wirings are also exchanged. This is to keep the coupling strengths of L0:L1 and L0:L2 consistent.

Further, as shown in fig. 2, at the position of the layout center line, the positive electrode wirings of the secondary winding L3 and the secondary winding L4 are exchanged, and the negative electrode wirings are also exchanged. Similarly, this is to keep the coupling strengths of L0:L3 and L0:L4 uniform.

While maintaining consistent coupling strengths of L0:L1, L0:L2, L0:L3, L0:L4, it is desirable to utilize both L2:L4, L1:L3 to make up the transformers mentioned in the preferred embodiments of the present disclosure. The fully symmetrical transformer structure can solve the problems of errors and inconsistent amplitude and phase caused by the transformer.

According to the embodiment of the disclosure, the following technical effects are achieved:

the noise coefficient of the amplifier can be effectively reduced in the millimeter wave frequency band, and the sensitivity of the receiver is improved. Compared with the single-channel noise offset circuit and the method in the prior art, the double-channel noise offset circuit and the noise offset method based on the transformer structure can realize the mutual offset of channel noise of the main channel and the auxiliary channel, and further reduce the noise coefficient of the low-noise amplifier.

Compared with the two-way noise coefficient offset circuit and the two-way noise coefficient offset method in the prior art, the two-way noise offset circuit and the noise offset method based on the transformer structure provided by the disclosure are based on a multi-way transformer scheme, so that the complete symmetry of the circuit structures of the main and auxiliary two paths is realized, the circuit structure is simplified, the circuit robustness is improved, and the unbalance of the main and auxiliary two paths caused by introducing a driving stage is avoided.

The foregoing description of the embodiments of the circuit is provided for further explanation of the aspects of the present disclosure by way of the method embodiments.

The two-way noise cancellation method based on the transformer structure can comprise the following steps:

In some embodiments, the method further comprises:

It can be understood that each step in the two-way noise cancellation method based on the transformer structure applies the two-way noise cancellation circuit based on the transformer structure provided by the embodiment of the present disclosure, and can achieve a corresponding technical effect, and the specific circuit structure can refer to the corresponding content in the foregoing circuit embodiment, so that the description is convenient and concise, and will not be repeated here.

It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present disclosure is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present disclosure. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all alternative embodiments, and that the acts and modules referred to are not necessarily required by the present disclosure.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel, sequentially, or in a different order, provided that the desired results of the disclosed aspects are achieved, and are not limited herein.

The above detailed description should not be taken as limiting the scope of the present disclosure. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.

Claims

1. A two-way noise cancellation circuit based on a transformer structure, the circuit comprising:

the common gate differential amplifier includes: the third MOS tube and the fourth MOS tube;

drains of the first MOS tube and the second MOS tube are respectively connected to the first matching network;

and the drains of the third MOS tube and the fourth MOS tube are respectively connected into the second matching network.

2. The circuit of claim 1, wherein the circuit comprises a plurality of capacitors,

the first auxiliary winding is provided with a tap and is used for providing direct current bias for the grid electrodes of the first MOS tube and the second MOS tube;

the fourth auxiliary winding is provided with a tap and is used for providing direct current bias for the grid electrodes of the third MOS tube and the fourth MOS tube;

and the connecting terminals at the middle parts of the second auxiliary winding and the third auxiliary winding coil are grounded.

3. The circuit of claim 1, wherein the circuit further comprises:

vout-port, said Vout-port being connected with said first matching network;

and the Vout+ port is connected with the second matching network.

4. The circuit of claim 3, wherein the circuit comprises a plurality of transistors,

the first matching network is used for converting the differential signal output by the common-source differential amplifier into a single-ended signal;

the differential signals output by the drains of the first MOS tube and the second MOS tube in the common source differential amplifier are converted into single-ended signals by the first matching network and then output from the Vout-port;

the second matching network is used for converting the differential signal output by the common-gate differential amplifier into a single-ended signal;

and differential signals output by the drains of the third MOS tube and the fourth MOS tube in the common-gate differential amplifier are converted into single-ended signals by the second matching network and then output from the Vout plus port.

5. The circuit of claim 1, wherein the circuit comprises a plurality of capacitors,

the third auxiliary winding and the fourth auxiliary winding are used for coupling noise N1 generated by the first MOS tube to the grid electrode of the third MOS tube in a forward direction, so that noise N1' appears in the third MOS tube; the noise N1' is reversely transmitted to the drain electrode of the third MOS tube and is output from the drain electrode of the third MOS tube;

the noise N1 output by the drain electrode of the first MOS tube and the noise N1' output by the drain electrode of the third MOS tube have the same transmission direction and the same phase;

the third auxiliary winding and the fourth auxiliary winding are used for coupling noise N2 generated by the second MOS tube to the grid electrode of the fourth MOS tube in a forward direction, so that noise N2' appears in the fourth MOS tube; the noise N2' is reversely transmitted to the drain electrode of the fourth MOS tube and is output from the drain electrode of the fourth MOS tube;

the noise N2 output by the drain electrode of the second MOS tube is the same as the noise N2' output by the drain electrode of the fourth MOS tube in transmission direction and in phase.

6. The circuit of claim 1, wherein the circuit comprises a plurality of capacitors,

the first auxiliary winding and the second auxiliary winding are used for coupling noise N3 generated by the third MOS tube to the grid electrode of the first MOS tube in a forward direction, so that noise N3' appears in the first MOS tube; the noise N3' is reversely transmitted to the drain electrode of the first MOS tube and is output from the drain electrode of the first MOS tube;

the noise N3 output by the drain electrode of the third MOS tube is the same as the noise N3' output by the drain electrode of the first MOS tube in transmission direction and in the same phase;

the first auxiliary winding and the second auxiliary winding forward couple noise N4 generated by the fourth MOS tube to the grid electrode of the second MOS tube, so that noise N4' appears in the second MOS tube; the noise N4' is reversely transmitted to the drain electrode of the second MOS tube and is output from the drain electrode of the second MOS tube;

the transmission direction of the noise N4 output by the drain electrode of the fourth MOS tube is the same as that of the noise N4' output by the drain electrode of the second MOS tube, and the phases are the same.

7. The circuit of claim 1, wherein the circuit comprises a plurality of capacitors,

an input signal is transmitted to the first auxiliary winding through the primary winding and is transmitted to the common-source differential amplifier through the first auxiliary winding; in the common source differential amplifier, the common source differential amplifier is input from the grid electrodes of the first MOS tube and the second MOS tube, and is output from the drain electrode;

an input signal is transmitted to the second auxiliary winding through the primary winding and is transmitted to the common-gate differential amplifier through the second auxiliary winding; in the common-gate differential amplifier, the common-gate differential amplifier is input from the sources of the third MOS tube and the fourth MOS tube, and is output from the drains; wherein,,

the signal transmission directions output by the drains of the first MOS tube and the third MOS tube are the same, and the phases are opposite;

the signal transmission directions of the drain electrodes of the second MOS tube and the fourth MOS tube are the same, and the phases are opposite.

8. The circuit of claim 7, wherein the circuit further comprises a logic circuit,

the primary winding and the first secondary winding forward couple an input signal to the gates of the first MOS tube and the second MOS tube; the primary winding and the third secondary winding reversely couple input signals to sources of the first MOS tube and the second MOS tube; to increase the voltage difference between the gate and the source, and to increase the gain of the common source differential amplifier;

the primary winding and the fourth secondary winding forward couple an input signal to gates of the third MOS transistor and the fourth MOS transistor; the primary winding and the second secondary winding reversely couple input signals to sources of the third MOS tube and the fourth MOS tube; to increase the voltage difference between the gate and the source and to increase the gain of the common gate differential amplifier.

9. A noise cancellation method applying the transformer structure-based two-way noise cancellation circuit as claimed in any one of claims 1 to 8, the method comprising:

an input signal is transmitted to a first auxiliary winding through a primary winding of a transformer, is transmitted to a common-source differential amplifier through the first auxiliary winding, and is output to a first matching network after being processed by the common-source differential amplifier;

the input signal is transmitted to a second winding subgroup through a primary winding of the transformer, is transmitted to a common-gate differential amplifier through the second auxiliary winding, and is output to a second matching network after being processed by the common-gate differential amplifier;

noise N1 generated by a first MOS tube in the common-source differential amplifier is transmitted to a grid electrode of a third MOS tube in the common-gate differential amplifier through forward coupling of a third auxiliary winding and a fourth auxiliary winding in a transformer, is reversely transmitted to a drain electrode of the common-gate differential amplifier by the third MOS tube, and is output from the drain electrode of the common-gate differential amplifier;

noise N2 generated by a second MOS tube in the common-source differential amplifier is transmitted to a grid electrode of a fourth MOS tube in the common-gate differential amplifier through forward coupling of a third auxiliary winding and a fourth auxiliary winding in a transformer, is reversely transmitted to a drain electrode of the fourth MOS tube by the fourth MOS tube, and is output from the drain electrode of the fourth MOS tube;

noise N3 generated by a third MOS tube in the common-gate differential amplifier is transmitted to a grid electrode of a first MOS tube in the common-source differential amplifier through forward coupling of a first auxiliary winding and a second auxiliary winding in a transformer, is reversely transmitted to a drain electrode of the first MOS tube, and is output from the drain electrode of the first MOS tube;

noise N4 generated by a fourth MOS tube in the common-gate differential amplifier is transmitted to a grid electrode of a second MOS tube in the common-source differential amplifier through forward coupling of a first auxiliary winding and a second auxiliary winding in a transformer, is reversely transmitted to a drain electrode of the second MOS tube, and is output from the drain electrode of the second MOS tube; wherein,,

signals and noise output by the first MOS tube and the second MOS tube are converted into single-ended signals in the first matching network and then output from Vout-ports;

10. The circuit of claim 9, wherein the method further comprises:

the primary winding and the first secondary winding in the transformer forward couple an input signal to gates of a first MOS tube and a second MOS tube in the common source differential amplifier; the primary winding and the third secondary winding in the transformer reversely couple input signals to sources of the first MOS tube and the second MOS tube; to increase the voltage difference between the gate and the source, and to increase the gain of the common source differential amplifier;

the primary winding and the fourth secondary winding in the transformer forward couple input signals to gates of a third MOS tube and a fourth MOS tube in the common-gate differential amplifier; the primary winding and the second secondary winding in the transformer reversely couple input signals to sources of the third MOS tube and the fourth MOS tube; to increase the voltage difference between the gate and the source and to increase the gain of the common gate differential amplifier.