CN116544320A - Method for improving ITO ohmic contact and LED chip - Google Patents
Method for improving ITO ohmic contact and LED chip Download PDFInfo
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- CN116544320A CN116544320A CN202310811662.6A CN202310811662A CN116544320A CN 116544320 A CN116544320 A CN 116544320A CN 202310811662 A CN202310811662 A CN 202310811662A CN 116544320 A CN116544320 A CN 116544320A
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- 238000000034 method Methods 0.000 title claims abstract description 71
- 229910052751 metal Inorganic materials 0.000 claims abstract description 46
- 239000002184 metal Substances 0.000 claims abstract description 46
- 238000000137 annealing Methods 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000000151 deposition Methods 0.000 claims abstract description 22
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 12
- 230000002708 enhancing effect Effects 0.000 claims description 10
- 230000000903 blocking effect Effects 0.000 claims description 9
- 238000002161 passivation Methods 0.000 claims description 9
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 7
- 229910052804 chromium Inorganic materials 0.000 claims description 4
- 238000011161 development Methods 0.000 claims description 4
- 238000005566 electron beam evaporation Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 claims 41
- 239000011229 interlayer Substances 0.000 claims 1
- 229910002601 GaN Inorganic materials 0.000 description 67
- 229910052594 sapphire Inorganic materials 0.000 description 10
- 239000010980 sapphire Substances 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 5
- 238000009616 inductively coupled plasma Methods 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 description 2
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 2
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 2
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- UOSXPFXWANTMIZ-UHFFFAOYSA-N cyclopenta-1,3-diene;magnesium Chemical compound [Mg].C1C=CC=C1.C1C=CC=C1 UOSXPFXWANTMIZ-UHFFFAOYSA-N 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 239000000395 magnesium oxide Substances 0.000 description 1
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 1
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The invention provides a method for improving ITO ohmic contact and an LED chip, the method comprises the steps of providing an epitaxial wafer, wherein the epitaxial wafer comprises a substrate, an n-GaN layer, a light-emitting layer and a p-GaN layer which are sequentially deposited on the substrate, sequentially depositing a metal Ti layer and an ITO transparent conductive film layer on the p-GaN layer, and finally annealing the epitaxial wafer with the metal Ti layer and the ITO transparent conductive film layer to form a TiN intermediate layer between the p-GaN layer and the ITO transparent conductive film layer.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for improving ITO ohmic contact and an LED chip.
Background
The light emitting diode (Light Emitting Diode, simply referred to as LED) is a semiconductor electronic device capable of emitting light, and attracts more and more researchers' attention due to its small size, high brightness, low power consumption, and the like.
Compared with the traditional light source, the GaN-based light emitting diode has the advantages of long service life, energy conservation, low power consumption and the like, and optimizing the current expansion uniformity in an LED active area is a key for improving the performance of an LED device, and in general cases, an Indium Tin Oxide (ITO) transparent electrode can effectively improve the current expansion uniformity of GaN, but because the work function of GaN is about 4.3eV, and the work function of ITO is about 5.1 eV, the work function of the ITO is obviously larger than that of GaN, when the GaN and the ITO are contacted, a barrier layer is easy to form, so that good ohmic contact between the transparent electrode ITO and the GaN is difficult to realize, and the voltage of an LED chip is higher.
Disclosure of Invention
Based on the above, the invention aims to provide a method for improving ITO ohmic contact and an LED chip, which aim to solve the problem that in the prior art, good ohmic contact between transparent electrode ITO and GaN is difficult to realize, so that the voltage of the LED chip is higher.
According to one embodiment of the invention, a method for improving ITO ohmic contact comprises the following steps:
providing an epitaxial wafer, wherein the epitaxial wafer comprises a substrate, and an n-GaN layer, a light-emitting layer and a p-GaN layer which are sequentially deposited on the substrate;
sequentially depositing a metal Ti layer and an ITO transparent conductive film layer on the p-GaN layer;
and annealing the epitaxial wafer with the metal Ti layer and the ITO transparent conductive film layer to form a TiN intermediate layer between the p-GaN layer and the ITO transparent conductive film layer.
Further, in the step of annealing the epitaxial wafer with the metal Ti layer and the ITO transparent conductive film layer, the annealing temperature is 500-700 ℃.
Further, in the step of annealing the epitaxial wafer with the metal Ti layer and the ITO transparent conductive film layer, the annealing time is 10-30 min.
Further, in the step of sequentially depositing the metal Ti layer and the ITO transparent conductive film layer on the p-GaN layer, the metal Ti layer and the ITO transparent conductive film layer are prepared in a magnetron sputtering mode.
Further, in the step of sequentially depositing the metal Ti layer and the ITO transparent conductive film layer on the p-GaN layer, the thickness of the metal Ti layer is controlled to be 10nm-30nm.
Further, the step of sequentially depositing a metal Ti layer and an ITO transparent conductive film layer on the p-GaN layer includes:
exposing the morphology part of the n-GaN layer by adopting an ICP etching technology;
deposition of SiO by PECVD technique 2 Sequentially performing yellow light treatment and spin exposure development to retain part of SiO on the p-GaN layer 2 To form a current blocking layer.
Further, the annealing treatment of the epitaxial wafer with the metal Ti layer and the ITO transparent conductive film layer comprises the following steps:
placing the annealed epitaxial wafer into an electron beam evaporation device, sequentially evaporating Cr, al, ti, ni, pt, ni, pt and Au layers at positions corresponding to the P-GaN layers to form P-type electrodes, and sequentially evaporating Cr, al, ti, ni, pt, ni, pt and Au layers at positions corresponding to the N-GaN layers to form N-type electrodes;
deposition of SiO on surfaces by PECVD technique 2 And forming passivation layers and forming holes at positions corresponding to the P-type electrode and the N-type electrode respectively.
Further, the thickness of the current blocking layer is controlled to be 250nm-350nm.
Further, the thickness of the passivation layer is controlled to be 70nm-90nm.
According to the LED chip, the LED chip is manufactured by the method for improving ITO ohmic contact, wherein a TiN intermediate layer is arranged between the p-GaN layer and the ITO transparent conductive film layer.
The method has the beneficial effects that the epitaxial wafer comprises a substrate, an n-GaN layer, a luminescent layer and a p-GaN layer which are sequentially deposited on the substrate, then a metal Ti layer and an ITO transparent conductive film layer are sequentially deposited on the p-GaN layer, finally the epitaxial wafer with the metal Ti layer and the ITO transparent conductive film layer is annealed to form a TiN intermediate layer between the p-GaN layer and the ITO transparent conductive film layer, and particularly, the metal Ti layer which is close to the GaN work function is inserted between the ITO transparent conductive film layer and the GaN, and the reaction between Ti and GaN is accelerated by utilizing a rapid thermal annealing process, so that the contact between ITO/Ti/GaN is gradually converted into ohmic contact, and the purpose of reducing the voltage of the LED chip is achieved.
Drawings
FIG. 1 is a flowchart of a method for improving ITO ohmic contact according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a portion of an LED chip according to an embodiment of the present invention.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Several embodiments of the invention are presented in the figures. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "mounted" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1 and fig. 2, fig. 1 is a flowchart illustrating an implementation of a method for improving ITO ohmic contact according to an embodiment of the present invention, and fig. 2 is a schematic diagram illustrating a portion of an LED chip according to an embodiment of the present invention, where the embodiment of the present invention provides a method for improving ITO ohmic contact, which specifically includes the following steps:
s100: providing an epitaxial wafer, wherein the epitaxial wafer comprises a substrate, and an n-GaN layer, a light-emitting layer and a p-GaN layer which are sequentially deposited on the substrate;
specifically, the substrate can be sapphire substrate or SiO 2 In this embodiment, the substrate is selected from one of a sapphire composite substrate, a silicon carbide substrate, a gallium nitride substrate and a zinc oxide substrate, and sapphire is the most commonly used GaN-based LED substrate material at present, and most GaN-based LEDs in the market use sapphire as the substrate material. The sapphire substrate has the greatest advantages of mature technology, good stability and low production cost.
Further, an epitaxial layer is grown on the sapphire substrate, specifically, an MOCVD (Metal Organic Chemical Vapor Deposition, metal chemical vapor deposition) method may be used to grow an epitaxial layer on the sapphire substrate, wherein high purity hydrogen is used as a carrier gas, high purity ammonia is used as a nitrogen source, trimethylgallium and triethylgallium are used as gallium sources, trimethylindium is used as an indium source, silane is used as an N-type dopant, trimethylaluminum is used as an aluminum source, and magnesium oxide is used as a P-type dopant, in this embodiment, the N-GaN layer 1 is an N-type semiconductor layer, the P-GaN layer 3 is a P-type semiconductor layer, the light emitting layer 2 is a multiple quantum well active layer, it is to be noted that the thickness of the N-GaN layer 1 is 1 μm-3 μm, and the thickness of the N-GaN layer 1 is 1.5 μm, 2 μm, 2.5 μm, or 3 μm, which is exemplary, but not limited thereto; si doping concentration of 5×10 18 cm -3 -1×10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the p-GaN layer 3 is 200nm to 300nm, and exemplary thicknesses of the p-GaN layer 3 are 200nm, 220nm, 250nm, 280nm, or 300nm, but are not limited thereto; mg doping concentration of 5×10 17 cm -3 -1×10 20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The molar ratio of the In component In the multi-quantum well active layer is 10% -35%, examplesThe molar ratio of the In component In the multi-quantum well active layer is 10%, 15%, 20%, 25%, 30% or 35%, but is not limited thereto.
S200: sequentially depositing a metal Ti layer and an ITO transparent conductive film layer on the p-GaN layer;
specifically, before sequentially depositing a metal Ti layer and an ITO transparent conductive film layer on a p-GaN layer, firstly exposing the morphology part of the n-GaN layer on an epitaxial layer by adopting an ICP (Inductively Coupled Plasma ) etching technology, and then depositing SiO (Plasma Enhance Chemical Vapour Deposition, plasma enhanced chemical vapor deposition) technology 2 Sequentially performing yellow light treatment and spin exposure development to retain part of SiO on the p-GaN layer 2 To form a current blocking layer 5. Wherein the thickness of the current blocking layer 5 is controlled to be 250nm to 350nm, and exemplary, but not limited to, the thickness of the current blocking layer 5 is 250nm, 280nm, 300nm, 320nm or 350nm.
Further, the metal Ti layer and the ITO transparent conductive film layer 6 are prepared in a magnetron sputtering mode, and the principle is that the target is bombarded by Ar gas ionization, so that the target is sputtered on the surface of a wafer, and the deposition of the metal Ti and the ITO is completed. Wherein the thickness of the metal Ti layer is controlled to be 10nm to 30nm, and exemplary, but not limited thereto, the thickness of the metal Ti layer is 10nm, 15nm, 20nm, 25nm or 30nm.
S300: and annealing the epitaxial wafer with the metal Ti layer and the ITO transparent conductive film layer to form a TiN intermediate layer between the p-GaN layer and the ITO transparent conductive film layer.
Specifically, the annealing process is to put the epitaxial wafer plated with the ITO transparent conductive film layer into a chamber with the temperature of 500-700 ℃ for annealing for 10-30 min. It can be understood that the metal Ti reacts with GaN under the action of high-temperature annealing to generate the TiN intermediate layer 4, and the generation of the TiN intermediate layer 4 can effectively improve ohmic contact between the ITO transparent conductive film layer and the epitaxial layer.
Further, the annealed epitaxial wafer is placed into an electron beam evaporation device, cr, al, ti, ni, pt, ni, pt and Au layers are sequentially evaporated on the corresponding positions of the P-GaN layers to form P-type electrodes 71, cr, al, ti, ni, pt, ni, pt and Au layers are sequentially evaporated on the corresponding positions of the N-GaN layers to form N-type electrodes 72;
deposition of SiO on surfaces by PECVD technique 2 To form the passivation layer 8 and open holes at positions corresponding to the P-type electrode 71 and the N-type electrode 72, respectively, specifically, the thickness of the passivation layer 8 is controlled to be 70nm to 90nm, and exemplary, the thickness of the passivation layer 8 is 70nm, 75nm, 80nm, 85nm or 90nm, but is not limited thereto.
The invention is further illustrated by the following examples:
example 1
The method for improving ITO ohmic contact in the embodiment comprises the following steps:
(1) Providing an epitaxial wafer, wherein the epitaxial wafer comprises a substrate, and an n-GaN layer, a light-emitting layer and a p-GaN layer which are sequentially deposited on the substrate;
in this embodiment, a sapphire substrate is used as the substrate, an epitaxial layer is grown on the sapphire substrate, specifically, an MOCVD (Metal Organic Chemical Vapor Deposition, metal chemical vapor deposition) method is used to grow an epitaxial layer on the sapphire substrate, wherein high-purity hydrogen is used as a carrier gas, high-purity ammonia gas is used as a nitrogen source, trimethylgallium and triethylgallium are used as a gallium source, trimethylindium is used as an indium source, silane is used as an N-type dopant, trimethylaluminum is used as an aluminum source, and magnesium-dicyclopentadiene is used as a P-type dopant, wherein the N-GaN layer is an N-type semiconductor layer, the P-GaN layer is a P-type semiconductor layer, the light emitting layer is a multiple quantum well active layer, and it is to be noted that the thickness of the N-GaN layer is 2 μm, and the Si doping concentration is 5.5x10 18 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The p-GaN layer had a thickness of 220nm and a doping concentration of Mg of 7.5X10 17 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The molar ratio of the In component In the multi-quantum well active layer is 12%.
(2) Sequentially depositing a metal Ti layer and an ITO transparent conductive film layer on the p-GaN layer;
specifically, before sequentially depositing a metal Ti layer and an ITO transparent conductive film layer on a p-GaN layer, the metal Ti layer and the ITO transparent conductive film layer are first epitaxially grownOn the layer, an ICP (Inductively Coupled Plasma ) etching technology is adopted to expose the morphology part of the n-GaN layer, and then a PECVD (Plasma Enhance Chemical Vapour Deposition, plasma enhanced chemical vapor deposition) technology is adopted to deposit SiO 2 Sequentially performing yellow light treatment and spin exposure development to retain part of SiO on the p-GaN layer 2 To form a current blocking layer. Wherein the thickness of the current blocking layer is controlled to be 300nm.
Further, a metal Ti layer and an ITO transparent conductive film layer are prepared by adopting a magnetron sputtering mode, wherein the thickness of the metal Ti layer is controlled to be 10nm.
(3) And annealing the epitaxial wafer with the metal Ti layer and the ITO transparent conductive film layer to form a TiN intermediate layer between the p-GaN layer and the ITO transparent conductive film layer.
Specifically, the annealing process is to put the epitaxial wafer plated with the ITO transparent conductive film layer into a chamber with the temperature of 500 ℃ for annealing for 10min.
Further, the annealed epitaxial wafer is placed into an electron beam evaporation device, cr, al, ti, ni, pt, ni, pt and Au layers are sequentially evaporated on the corresponding positions of the P-GaN layers to form P-type electrodes, cr, al, ti, ni, pt, ni, pt and Au layers are sequentially evaporated on the corresponding positions of the N-GaN layers to form N-type electrodes;
deposition of SiO on surfaces by PECVD technique 2 And forming a passivation layer, and opening holes at positions corresponding to the P-type electrode and the N-type electrode respectively, wherein the thickness of the passivation layer is controlled to be 80nm.
Example 2
The present embodiment also provides a method for improving ITO ohmic contact, which is different from embodiment 1 in that in the method for improving ITO ohmic contact of embodiment 2, the thickness of the metal Ti layer is controlled to be 15nm, the annealing temperature is 550 ℃, and the annealing time is 15min.
Example 3
The present embodiment also provides a method for improving an ITO ohmic contact, which is different from embodiment 1 in that in the method for improving an ITO ohmic contact of embodiment 3, the thickness of the metal Ti layer is controlled to be 20nm, the annealing temperature is 600 ℃, and the annealing time is 20min.
Example 4
The present embodiment also provides a method for improving ITO ohmic contact, which is different from embodiment 1 in that in the method for improving ITO ohmic contact of embodiment 4, the thickness of the metal Ti layer is controlled to be 25nm, the annealing temperature is 650 ℃, and the annealing time is 25min.
Example 5
The present embodiment also provides a method for improving ITO ohmic contact, which is different from embodiment 1 in that in the method for improving ITO ohmic contact of embodiment 5, the thickness of the metal Ti layer is controlled to be 30nm, the annealing temperature is 700 ℃, and the annealing time is 30min.
Example 6
The present embodiment also provides a method for improving an ITO ohmic contact, which is different from embodiment 1 in that in the method for improving an ITO ohmic contact of embodiment 6, an annealing temperature is controlled to be 510 ℃.
Example 7
The present embodiment also provides a method of enhancing ITO ohmic contact, which is different from embodiment 1 in that in the method of enhancing ITO ohmic contact in embodiment 7, the annealing temperature is controlled to 520 ℃.
Example 8
The present embodiment also provides a method of enhancing ITO ohmic contact, which is different from embodiment 1 in that in the method of enhancing ITO ohmic contact in embodiment 8, the annealing temperature is controlled to 530 ℃.
Example 9
The present embodiment also provides a method for improving an ITO ohmic contact, which is different from embodiment 1 in that in the method for improving an ITO ohmic contact of embodiment 9, an annealing temperature is controlled to 540 ℃.
Example 10
The present embodiment also provides a method of enhancing ITO ohmic contact, which is different from embodiment 1 in that in the method of enhancing ITO ohmic contact in embodiment 10, the annealing temperature is controlled to 550 ℃.
Example 11
This embodiment also provides a method of enhancing an ITO ohmic contact, which is different from embodiment 3 in that in the method of enhancing an ITO ohmic contact in embodiment 11, the annealing temperature is controlled to be 580 ℃.
Example 12
The present embodiment also provides a method for improving an ITO ohmic contact, which is different from embodiment 3 in that in the method for improving an ITO ohmic contact in embodiment 12, the annealing temperature is controlled to be 620 ℃.
Example 13
The present embodiment also provides a method for improving ITO ohmic contact, which is different from embodiment 3 in that in the method for improving ITO ohmic contact in embodiment 13, the annealing time is controlled to be 18min.
Example 14
The present embodiment also provides a method for improving ITO ohmic contact, which is different from embodiment 3 in that in the method for improving ITO ohmic contact in embodiment 14, the annealing time is controlled to be 22min.
Comparative example 1
The preparation method provided in this comparative example is different from that of example 1 in that the ITO transparent conductive film layer was formed only on the p-GaN layer, and annealing treatment was not performed.
The chips prepared in the methods of example 1 to example 14, comparative example 1 were tested under the same conditions (120 mA), and the specific results were as follows:
as can be seen from the table, the chips prepared by the method for improving the ohmic contact of ITO in the examples of the present invention have a test voltage smaller than that of comparative example 1 (conventional preparation method) under the same test conditions, and specifically, the chips prepared by the methods in examples 3, 13 and 14 of the present invention have a test voltage smaller than that of the conventional method of comparative example 1 by only 3.01mV. It is noted that, as the annealing temperature increases, the test voltage of the chip gradually decreases, but the decrease in the test voltage is limited, as can be seen from examples 1, 6 to 10; it was found from examples 3, 11 to 14 that when the thickness of the metal Ti layer was fixed, the annealing temperature was optimal at 600 ℃, and the performance was poor below or above 600 ℃, and when the thickness of the metal Ti layer and the annealing temperature were fixed, the annealing time was in the range of 18min to 22min, and the performance was not affected.
The embodiment of the invention further provides an LED chip, which is prepared by the method for improving ITO ohmic contact, wherein a TiN intermediate layer is arranged between the p-GaN layer and the ITO transparent conductive film layer.
In summary, the method for improving the ohmic contact of the ITO and the LED chip in the embodiment of the invention comprises the steps of providing an epitaxial wafer, wherein the epitaxial wafer comprises a substrate, an n-GaN layer, a light-emitting layer and a p-GaN layer which are sequentially deposited on the substrate, sequentially depositing a metal Ti layer and an ITO transparent conductive film layer on the p-GaN layer, and finally annealing the epitaxial wafer with the metal Ti layer and the ITO transparent conductive film layer to form a TiN intermediate layer between the p-GaN layer and the ITO transparent conductive film layer, and particularly, accelerating the reaction between Ti and GaN by utilizing a rapid thermal annealing process, so that the contact between ITO/Ti/GaN is gradually converted into ohmic contact, thereby achieving the purpose of reducing the voltage of the LED chip.
The foregoing examples illustrate only a few embodiments of the invention and are described in detail herein without thereby limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. A method of enhancing an ITO ohmic contact, the method comprising:
providing an epitaxial wafer, wherein the epitaxial wafer comprises a substrate, and an n-GaN layer, a light-emitting layer and a p-GaN layer which are sequentially deposited on the substrate;
sequentially depositing a metal Ti layer and an ITO transparent conductive film layer on the p-GaN layer;
and annealing the epitaxial wafer with the metal Ti layer and the ITO transparent conductive film layer to form a TiN intermediate layer between the p-GaN layer and the ITO transparent conductive film layer.
2. The method for improving an ohmic contact to ITO according to claim 1, wherein in the step of annealing the epitaxial wafer with the metallic Ti layer and the ITO transparent conductive film layer, an annealing temperature is 500 ℃ to 700 ℃.
3. The method for improving the ohmic contact of the ITO according to claim 2, wherein in the step of annealing the epitaxial wafer with the metal Ti layer and the ITO transparent conductive film layer, the annealing time is 10min-30min.
4. The method for improving the ohmic contact of the ITO according to claim 1, wherein in the step of sequentially depositing the metal Ti layer and the ITO transparent conductive film layer on the p-GaN layer, the metal Ti layer and the ITO transparent conductive film layer are prepared by adopting a magnetron sputtering mode.
5. The method for improving an ohmic contact to ITO according to claim 1, wherein in the step of sequentially depositing the metallic Ti layer and the transparent conductive film layer of ITO on the p-GaN layer, the thickness of the metallic Ti layer is controlled to be 10nm to 30nm.
6. The method of claim 1, wherein the step of sequentially depositing a metallic Ti layer and an ITO transparent conductive film layer on the p-GaN layer comprises:
exposing the morphology part of the n-GaN layer by adopting an ICP etching technology;
deposition of SiO by PECVD technique 2 Sequentially performing yellow light treatment and spin exposure development to retain part of SiO on the p-GaN layer 2 To form a current blocking layer.
7. The method for improving an ohmic contact to ITO according to claim 6, wherein the step of annealing the epitaxial wafer with the metallic Ti layer and the transparent conductive film layer to ITO includes:
placing the annealed epitaxial wafer into an electron beam evaporation device, sequentially evaporating Cr, al, ti, ni, pt, ni, pt and Au layers at positions corresponding to the P-GaN layers to form P-type electrodes, and sequentially evaporating Cr, al, ti, ni, pt, ni, pt and Au layers at positions corresponding to the N-GaN layers to form N-type electrodes;
deposition of SiO on surfaces by PECVD technique 2 And forming passivation layers and forming holes at positions corresponding to the P-type electrode and the N-type electrode respectively.
8. The method of claim 6, wherein the thickness of the current blocking layer is controlled to be 250nm-350nm.
9. The method of claim 7, wherein the passivation layer is controlled to have a thickness of 70nm-90nm.
10. An LED chip, characterized in that it is prepared by the method for enhancing ITO ohmic contact according to any one of claims 1 to 9, wherein a TiN interlayer is provided between the p-GaN layer and the ITO transparent conductive film layer.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108511574A (en) * | 2017-02-28 | 2018-09-07 | 山东浪潮华光光电子股份有限公司 | A kind of preparation method of GaN base light emitting chip |
| CN116344601A (en) * | 2023-02-17 | 2023-06-27 | 徐州金沙江半导体有限公司 | Manufacturing method of ohmic contact of gallium nitride device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108511574A (en) * | 2017-02-28 | 2018-09-07 | 山东浪潮华光光电子股份有限公司 | A kind of preparation method of GaN base light emitting chip |
| CN116344601A (en) * | 2023-02-17 | 2023-06-27 | 徐州金沙江半导体有限公司 | Manufacturing method of ohmic contact of gallium nitride device |
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| Title |
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| 卫新发: ""氧化铟锡与掺 Fe 半绝缘 GaN 的接触特性"", 《半导体技术》, pages 474 - 478 * |
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