CN116544300A - Preparation method of InAs/GaSb II superlattice infrared detector - Google Patents
Preparation method of InAs/GaSb II superlattice infrared detector Download PDFInfo
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- CN116544300A CN116544300A CN202310303911.0A CN202310303911A CN116544300A CN 116544300 A CN116544300 A CN 116544300A CN 202310303911 A CN202310303911 A CN 202310303911A CN 116544300 A CN116544300 A CN 116544300A
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- 229910005542 GaSb Inorganic materials 0.000 title claims abstract description 50
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 title claims abstract description 33
- 229910000673 Indium arsenide Inorganic materials 0.000 title claims abstract description 31
- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 38
- 238000005530 etching Methods 0.000 claims abstract description 32
- 229910004298 SiO 2 Inorganic materials 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims abstract description 7
- 238000004544 sputter deposition Methods 0.000 claims abstract description 7
- 238000004140 cleaning Methods 0.000 claims description 14
- 238000001035 drying Methods 0.000 claims description 14
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 12
- 239000008367 deionised water Substances 0.000 claims description 11
- 229910021641 deionized water Inorganic materials 0.000 claims description 11
- 230000008569 process Effects 0.000 claims description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 238000011161 development Methods 0.000 claims description 5
- 238000011010 flushing procedure Methods 0.000 claims description 5
- 230000007797 corrosion Effects 0.000 claims description 4
- 238000005260 corrosion Methods 0.000 claims description 4
- 238000004528 spin coating Methods 0.000 claims description 4
- 238000004506 ultrasonic cleaning Methods 0.000 claims description 4
- 238000005566 electron beam evaporation Methods 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 238000000861 blow drying Methods 0.000 claims description 2
- 238000001816 cooling Methods 0.000 claims description 2
- 238000000265 homogenisation Methods 0.000 claims description 2
- 238000005406 washing Methods 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims 1
- 239000000126 substance Substances 0.000 abstract description 5
- 230000006872 improvement Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 61
- 239000000463 material Substances 0.000 description 13
- 238000006243 chemical reaction Methods 0.000 description 8
- 239000002344 surface layer Substances 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
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- 238000001020 plasma etching Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910000661 Mercury cadmium telluride Inorganic materials 0.000 description 2
- 239000003153 chemical reaction reagent Substances 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
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- 239000007800 oxidant agent Substances 0.000 description 2
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- 238000011160 research Methods 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 1
- MCMSPRNYOJJPIZ-UHFFFAOYSA-N cadmium;mercury;tellurium Chemical compound [Cd]=[Te]=[Hg] MCMSPRNYOJJPIZ-UHFFFAOYSA-N 0.000 description 1
- 230000000536 complexating effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
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- 238000001534 heteroepitaxy Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02366—Special surface textures of the substrate or of a layer on the substrate, e.g. textured ITO/glass substrate or superstrate, textured polymer layer on glass substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035236—Superlattices; Multiple quantum well structures
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention provides a preparation method of an InAs/GaSb II superlattice infrared detector, which comprises the following steps: s1, sputtering SiO on GaSb substrate 2 A layer; s2, at SiO 2 Adhering a photoresist layer on the layer, and exposing the photoresist layer through a mask plate; s3, patterning the exposed photoresist layer; s4, to SiO 2 Etching the layer and removing the photoresist layer; s5, at SiO 2 InAs/GaSb II superlattice platforms grow in gaps of the layers; s6, removing SiO by etching 2 A layer; and S7, preparing a metal electrode on the table surface and the side wall of the InAs/GaSb II superlattice table. The invention provides an improvement for the traditional method of etching after the substrate is externally extended, and provides the method of etching and patterning the substrate and then carrying out epitaxial growth, thereby greatly avoiding the breakage of chemical bonds of an epitaxial part and effectively inhibitingThe large surface dark current existing in the traditional II-type superlattice infrared detector is overcome.
Description
Technical Field
The invention relates to the technical field of semiconductor photoelectronic devices, in particular to a preparation method of an InAs/GaSb II superlattice infrared detector.
Background
Any object of non-absolute zero will radiate an electromagnetic wave from outside at any moment. At lower temperatures, such as 300K at room temperature, the wavelength of the electromagnetic radiation is in the infrared band, i.e., the wavelength is about 0.72-1000 μm. Such electromagnetic waves are called infrared light and cannot be directly observed by the human eye. For a general object on the earth's surface, infrared light is radiated both from living (animal body) and from inanimate (mountain, lake, etc.). Particularly, for some military equipment such as warplanes, tanks, warships and the like, which have a certain high-temperature part, a strong infrared radiation source can be formed, and infrared light cannot be directly observed by eyes, so that the infrared research has become an important position in the military field.
The infrared detector with high sensitivity and high resolution is one of the important directions of the development of the third-generation detector in the present stage, wherein the InAs/GaSb II superlattice infrared detector has the advantages of flexible adjustment of band gap, high yield and the like, and the performance of the infrared detector is hopeful to be comparable with that of mercury cadmium telluride (HgCdTe) materials, and has great development potential. The most important parameter for restricting the performance of the InAs/GaSb II superlattice infrared detector is dark current density, a commercial reading circuit is difficult to be matched and connected with the dark current density due to the higher dark current density, the dark current mainly comprises a bulk dark current part and a surface dark current part, along with optimization of a heteroepitaxy process and the proposal of a novel structure in recent years, the quality of the material is greatly improved, the bulk dark current is greatly inhibited, and the surface leakage current is a main part of the dark current.
The traditional InAs/GaSb II superlattice infrared detector is generally prepared by adopting a mesa structure, and when the mesa is etched, semiconductor chemical bonds are broken to generate a large number of dangling bonds, so that the performance of a pn junction region is affected, and surface leakage current is generated. In addition, the side wall of the mesa is also affected by multiple factors such as etching cleanliness, roughness, element proportion and the like, so that the quality of the side wall of the mesa junction has great influence on the surface leakage characteristics of the device.
In the conventional etching process, according to a designed structure, a complete epitaxial film required by a chip is prepared on a substrate (usually 2 inches or 4 inches) with a certain size by adopting a molecular beam epitaxy method, a vapor phase epitaxy method and the like, and then partial areas of the semiconductor film are selectively removed by a physical or chemical method to form a specific shape. Currently, the main stream etching techniques for GaSb materials include dry and wet etching. The dry etching refers to an etching method related to plasma under low pressure, and mainly comprises ion beam etching, reactive ion etching, ionization coupling plasma etching, plasma etching and the like. Wet etching refers to immersing the etched substrate material into a prepared solution, and the effect of removing the surface layer material is achieved by utilizing the chemical reaction of the material and the reagent. The dry etching has the advantages of good anisotropy, good repeatability and the like, but can generate obvious etching damage to influence the performance of the device, compared with the dry etching, the wet etching has the advantages of small etching damage, low production cost, clean surface, short experimental period and the like, has unique advantages in the aspect of GaSb devices, and is an important direction in the research of the current GaSb etching technology.
Disclosure of Invention
In order to solve the technical problem of large dark current after etching of InAs/GaSb II superlattice infrared detectors in the prior art, the invention aims to provide a preparation method of the InAs/GaSb II superlattice infrared detectors, which comprises the following steps:
s1, sputtering SiO on GaSb substrate 2 A layer;
s2, at SiO 2 Adhering a photoresist layer on the layer, and exposing the photoresist layer through a mask plate;
s3, patterning the exposed photoresist layer;
s4, to SiO 2 Etching the layer and removing the photoresist layer;
s5, at SiO 2 InAs/GaSb II superlattice platforms grow in gaps of the layers;
s6, removing SiO by etching 2 A layer;
and S7, preparing a metal electrode on the table surface and the side wall of the InAs/GaSb II superlattice table.
Preferably, in step S1, after cleaning and drying the GaSb substrate, siO is sputtered 2 A layer.
Preferably, prior to step S2, siO is reacted with 2 The ultrasonic cleaning is carried out on the surface of the layer, and the cleaning method comprises the following steps:
SiO was cleaned using deionized water using standard RCA cleaning process 2 Repeatedly flushing the surface of the layer for a plurality of times, and using nitrogen to carry out SiO treatment 2 Drying the surface of the layer;
after blow-drying, the sample was dried in a 150 ℃ oven for 2 minutes.
Preferably, the following method steps are included in step S2:
and (3) homogenizing: for SiO 2 Photoresist layers adhered on the layers are subjected to photoresist homogenization;
pre-baking: after spin coating, placing the sample in a culture dish, covering, pre-drying in a drying oven at 100 ℃ for 2min, and then cooling;
exposure: and aligning the geometric figure on the mask plate with the position of the photoresist layer for exposure.
Preferably, the following method steps are included in step S3:
developing: immersing the exposed sample in a beaker containing a developing solution, continuously shaking, fully dissolving the exposed photoresist layer, controlling the development time, then flushing with deionized water, and displaying geometric figures on the photoresist layer;
hardening: the sample is baked for 120-150s by a hot plate at 120 ℃ and the photoresist layer is hardened.
Preferably, in step S4 the following method steps are included:
sputtering SiO with HF buffer 2 Layer corrosion, repeatedly washing or ultrasonically cleaning a sample with deionized water for a plurality of times after corrosion;
SiO removal by desmutting 2 Photoresist on the layer.
Preferably, in step S7, a metal electrode is prepared on the mesa and the sidewall of the InAs/GaSb II superlattice by using an electron beam evaporation Ti/Pt/Au deposition method.
According to the preparation method of the InAs/GaSb II superlattice infrared detector, provided by the invention, the process of epitaxial growth is performed after photoetching is selected on the GaSb substrate in advance, the patterned substrate reduces surface dangling bonds, the heterostructure is naturally grown through the patterned substrate, the surface deterioration caused by cutting of an epitaxial wafer is avoided, and the surface dark current existing in the infrared detector is effectively inhibited by means of the patterned GaSb substrate.
The preparation method of the InAs/GaSb II superlattice infrared detector provided by the invention provides an improvement on the traditional method of etching after the substrate is externally extended, and provides that the substrate is etched and patterned before epitaxial growth, so that the breakage of chemical bonds of an epitaxial part is avoided greatly, and the larger surface dark current of the traditional II superlattice infrared detector is effectively inhibited.
The preparation method of the InAs/GaSb II superlattice infrared detector comprises the steps of carrying out photoetching exposure on photoresist through a photoetching technology, and removing uncovered areas of the photoresist from the surface of a material by a physical or chemical method so as to transfer a mask pattern to the surface of the material. The patterned GaSb substrate with low cost, low roughness and high cleanliness is realized by regulating and controlling the etching rate, the infrared detector with low surface dark current is realized, and the InAs/GaSb II superlattice infrared detector with smaller surface leakage current is realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 schematically shows a process flow diagram of a method for manufacturing an InAs/GaSb class II superlattice infrared detector in an embodiment of the invention.
Detailed Description
To further clarify the above and other features and advantages of the present invention, a further description of the invention will be rendered by reference to the appended drawings. It should be understood that the specific embodiments presented herein are for purposes of explanation to those skilled in the art and are intended to be illustrative only and not limiting.
In the long-wave and very-long-wave InAs/GaSb II superlattice infrared detectors, surface leakage current is one of main mechanisms of dark current, and in order to solve the technical problem of large dark current after etching of the InAs/GaSb II superlattice infrared detectors in the prior art, as shown in a process flow chart of a preparation method of the InAs/GaSb II superlattice infrared detectors in an embodiment of the invention in fig. 1, according to the embodiment of the invention, the preparation method of the InAs/GaSb II superlattice infrared detectors is provided, and comprises the following method steps:
step S1, sputtering SiO on GaSb substrate 100 2 Layer 200.
Specifically, after cleaning and drying the GaSb substrate 100, siO is sputtered 2 Layer 200.
Step S2, at SiO 2 A photoresist layer 300 is adhered to the layer 200 and the photoresist layer 300 is exposed through a mask 400.
In SiO 2 Before adhering the photoresist layer 300 on the layer 200, to ensure SiO 2 Layer 200 surface cleanliness, for SiO 2 Ultrasonic cleaning is carried out on the surface of the layer 200 to remove SiO 2 Surface contaminants such as oil stains and minute particles that may be present on the surface of layer 200.
For SiO 2 The surface of the layer 200 is subjected to ultrasonic cleaning, and the cleaning method comprises the following steps:
SiO was cleaned using deionized water using standard RCA cleaning process 2 Repeatedly flushing the surface of the layer for a plurality of times, and using nitrogen to carry out SiO treatment 2 Drying the surface of the layer;
drying the sample in a drying oven at 150 ℃ for 2 minutes to remove SiO 2 Water vapor remaining on the surface of layer 200 increases SiO 2 Adhesion of layer 200 to photoresist.
After cleaning, the sample is stored in a clean dry box or the photolithography process is completed as soon as possible in order to maintain the hydrophobic surface.
For SiO 2 After cleaning and drying the surface of the layer 200, the surface of the layer is coated with SiO 2 The photoresist layer 300 is adhered to the layer 200, and the photoresist layer 300 is exposed through the mask 400, comprising the following method steps:
and (3) homogenizing: for SiO 2 Photoresist layer 300, which is adhered to layer 200, is spin coated.
In a specific embodiment, a spin coater is turned on, and the spin speed and time of spin coating are set. And placing the cleaned and dried sample in the center of the object stage, dripping a proper amount of photoresist in the center of the sample, determining the using amount of the photoresist according to the size of the substrate and the type of the photoresist, and checking whether the photoresist on the surface of the sample is completely covered after the photoresist is uniformly mixed.
Pre-baking: after spin coating, the samples were placed in petri dishes and covered, pre-baked in a drying oven at 100deg.C for 2min, and then cooled. The purpose of this step is to evaporate most of the solvent in the photoresist (the photoresist contains 10-30% solvent without pre-baking, and the pre-baking is reduced to about 5%).
Exposure: the geometry on reticle 400 is aligned with the position of photoresist layer 300 and then exposed.
Step S3, patterning the exposed photoresist layer 300.
The patterning process comprises the following method steps:
developing: the exposed sample is immersed in a beaker containing a developing solution, and is continuously shaken to fully dissolve the exposed photoresist layer, the development time is controlled, and then the photoresist layer is rinsed with deionized water, so that geometric figures are displayed on the photoresist layer 300.
Hardening: the samples were baked on a hot plate at 120 c for 120-150s and cured on photoresist layer 300.
Step S4, for SiO 2 Layer 200 is etched and the photoresist layer is removed.
After patterning the photoresist layer 300, siO is performed 2 Layer 200 is etched comprising the following method steps:
sputtering SiO with HF buffer 2 The layer 200 is etched, and after etching, the sample is repeatedly rinsed or ultrasonically cleaned with deionized water to prevent the residue of chemical reagents and contaminants.
SiO removal by desmutting 2 Photoresist on layer 200.
SiO of the invention 2 Layer 200 is etched using HF buffer, siO 2 The etching solution is typically composed of HF, NH4F, and deionized water (DI). HF vs. SiO 2 And GaSb have extremely high selectivity, and the selective etching capacity can be generally more than 100:1. The reaction process of GaSb in etching liquid essentially belongs to electrochemical reaction. This reaction mainly involves two processes:
(1) Oxidizing the GaSb surface layer;
(2) The oxidation product dissolves.
Therefore, the etching solution needs to contain two basic components of an oxidant and a complexing agent, and the etching reaction process can only smoothly occur. When the GaSb surface layer is contacted with etching liquid, a microelectrode region formed by a large number of micro-anode regions and micro-cathode regions is generated on the surface of the GaSb surface layer, and the reaction interface between the material surface and the etching liquid is still electrically neutral macroscopically. In the reaction process, the micro anode region is subjected to oxidation reaction, namely GaSb generates oxides (Ga 2O3 and Sb2O 3) under the action of an oxidant, and the oxides are further complexed and dissolved in the micro cathode region. The reaction process can be divided into the following three basic steps:
A. the components such as oxide, complexing agent and the like are ionized in the etching liquid to different degrees, and ions and free radicals with reactivity are ionized and are contacted with the surface of the material after being diffused in the solution;
B. after the chemical reaction of the interface between the material and the solution, the surface layer of the material begins to dissolve;
C. the soluble oxidation product diffuses into the solution, a part of insoluble product diffuses into the solution after complexing with the complexing agent, and a part of insoluble product may be deposited on the surface of the material.
Step S5, at SiO 2 InAs/GaSb class II superlattice mesa 500 is grown in the gap of layer 200. I.e. at SiO 2 Epitaxial growth of InAs/GaSb type II superlattice is performed in the gaps after etching of the layer 200.
S6, removing SiO by etching 2 Layer 200.
SiO using HF buffer 2 After etching the layer 200 to a certain thickness, cleaning is performed to remove SiO 2 Layer 200.
And S7, preparing a metal electrode on the table surface and the side wall of the InAs/GaSb II superlattice table 500.
And preparing a metal electrode on the table top and the side wall of the InAs/GaSb II superlattice table by adopting a method of electron beam evaporation deposition Ti/Pt/Au. In an embodiment, a first metal electrode 501 is fabricated on the mesa of the InAs/GaSb type II superlattice mesa 500 and a second metal electrode 502 is fabricated on the sidewall of the InAs/GaSb type II superlattice mesa 500.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (7)
1. The preparation method of the InAs/GaSb II superlattice infrared detector is characterized by comprising the following steps of:
s1, sputtering SiO on GaSb substrate 2 A layer;
s2, at SiO 2 Adhering a photoresist layer on the layer, and exposing the photoresist layer through a mask plate;
s3, patterning the exposed photoresist layer;
s4, to SiO 2 Etching the layer and removing the photoresist layer;
s5, at SiO 2 InAs/GaSb II type super crystal grown in gap of layerA grid;
s6, removing SiO by etching 2 A layer;
and S7, preparing a metal electrode on the table surface and the side wall of the InAs/GaSb II superlattice table.
2. The method according to claim 1, wherein in step S1, after cleaning and drying the GaSb substrate, siO is sputtered 2 A layer.
3. The method according to claim 1, wherein prior to step S2, siO 2 The ultrasonic cleaning is carried out on the surface of the layer, and the cleaning method comprises the following steps:
SiO was cleaned using deionized water using standard RCA cleaning process 2 Repeatedly flushing the surface of the layer for a plurality of times, and using nitrogen to carry out SiO treatment 2 Drying the surface of the layer;
after blow-drying, the sample was dried in a 150 ℃ oven for 2 minutes.
4. The preparation method according to claim 1, characterized in that in step S2 the following method steps are included:
and (3) homogenizing: for SiO 2 Photoresist layers adhered on the layers are subjected to photoresist homogenization;
pre-baking: after spin coating, placing the sample in a culture dish, covering, pre-drying in a drying oven at 100 ℃ for 2min, and then cooling;
exposure: and aligning the geometric figure on the mask plate with the position of the photoresist layer for exposure.
5. The preparation method according to claim 1, characterized in that in step S3 the following method steps are included:
developing: immersing the exposed sample in a beaker containing a developing solution, continuously shaking, fully dissolving the exposed photoresist layer, controlling the development time, then flushing with deionized water, and displaying geometric figures on the photoresist layer;
hardening: the sample is baked for 120-150s by a hot plate at 120 ℃ and the photoresist layer is hardened.
6. The preparation method according to claim 1, characterized in that in step S4 the following method steps are included:
sputtering SiO with HF buffer 2 Layer corrosion, repeatedly washing or ultrasonically cleaning a sample with deionized water for a plurality of times after corrosion;
SiO removal by desmutting 2 Photoresist on the layer.
7. The method according to claim 1, wherein in step S7, metal electrodes are formed on the mesa and the sidewall of the InAs/GaSb II superlattice by electron beam evaporation to deposit Ti/Pt/Au.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310303911.0A CN116544300A (en) | 2023-03-27 | 2023-03-27 | Preparation method of InAs/GaSb II superlattice infrared detector |
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| CN202310303911.0A CN116544300A (en) | 2023-03-27 | 2023-03-27 | Preparation method of InAs/GaSb II superlattice infrared detector |
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