CN204680649U - For the compound mask that energetic ion injects - Google Patents

For the compound mask that energetic ion injects Download PDF

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Publication number
CN204680649U
CN204680649U CN201520371989.7U CN201520371989U CN204680649U CN 204680649 U CN204680649 U CN 204680649U CN 201520371989 U CN201520371989 U CN 201520371989U CN 204680649 U CN204680649 U CN 204680649U
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mask
layer
chip
photoresist
compound
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施长治
林春
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Shanghai Institute of Technical Physics of CAS
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Shanghai Institute of Technical Physics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/18, H10D48/04 and H10D48/07, with or without impurities, e.g. doping materials
    • H01L21/42—Bombardment with radiation
    • H01L21/423—Bombardment with radiation with high-energy radiation
    • H01L21/425—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/426—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)

Abstract

This patent discloses a kind of compound mask injected for energetic ion.Mask in this patent is a kind of compound photoresist mask with three-decker, and photoresist mask pattern is produced between implant blocking layer deielectric-coating and top layer sacrificial dielectric film by this mask, injects mask as energetic ion.The compound mask of this patent can avoid the chap denaturing problem of photoresist mask under high-energy ion bombardment, and mask removes noresidue, ensures chip surface cleanliness factor, improves device performance.

Description

For the compound mask that energetic ion injects
Technical field
This patent relates to the mask technique in microelectronic technique, specifically refers to a kind of compound mask structure injected for energetic ion.
Background technology
Infrared focal plane array seeker based on HgCdTe photodiode has been widely used in the fields such as military security, resource exploration, marine monitoring and space remote sensing.Divide by device architecture, HgCdTe photodiode can be divided into n-on-p type and p-on-n type.The technological accumulation that n-on-p technique goes through decades has been tending towards ripe, has had higher performance based on the short-wave infrared (SWIR) of this technique and medium-wave infrared (MWIR) HgCdTe FPA device.But, for long wave (LW) and very long wave (VLW) device, in order to obtain the spectral response of corresponding spectral coverage, the energy gap of HgCdTe base material must be reduced (< 90meV) further.Under energy gap narrow like this, the tunnelling current component in device dark electric current will become very remarkable.P-on-n type device significantly can suppress tunnelling current, reduces dark current and reduce the series resistance of light absorbing zone, has the incomparable advantage of n-on-p type device at long wave/very long wave and large area HgCdTe infrared focal plane detector array application aspect.Compared with plane pn knot technique in p-on-n type detector ties technique with table top pn, there is the advantage that technique easily realizes, surface passivation technology simple, device consistency is good.One of its core technology is exactly the ion implantation technique of p-type impurity, and dopant is V group element, the most conventional with arsenic element.The atomic mass of arsenic is large, diffusion coefficient is very little, and in order to arsenic ion being injected into the applicable degree of depth meeting device performance requirements, high-energy must be adopted to carry out ion implantation, and Implantation Energy is higher than 300KeV.Under high-octane like this heavy nucleus Ions Bombardment, not only mercury cadmium telluride top layer can produce damage defect, and conventional photoresist mask also cannot bear, and sex change can occur and chap, thus thoroughly cannot remove the problem of mask after causing technique failure and injection.
At present, in silicon-based semiconductor devices technique, the soft mask sex change under Ions Bombardment such in order to avoid photoresist and the problem easily remained, some semiconductor device manufacturer proposes hard mask scheme, namely using patterned hard dielectric film as injection mask.As, BOE science and technology proposes to prepare graphite film at substrate surface, by patterning processes formed graphite mask layer (list of references: a kind of method of ion implantation. Chinese invention patent, CN103972062A); China's power microelectronics proposes at substrat structure surface deposition amorphous state carbon-coating as injection masking layer, deposit hard mask layer thereon, cover photoresist again, by photoetching with repeatedly graphically etch, acquisition amorphous state carbon-coating mask (list of references: a kind of manufacture method of ion implantation barrier layer. Chinese invention patent, CN102683184A).Although hard mask avoids photoresist mask by bombardment sex change and easily residual problem, it needs to deposit extra deielectric-coating, and carries out multistep photoetching and etching, complex process.The reason that hard mask is not suitable for HgCdTe device is: 1) depositing temperature of hard mask layer far exceedes the temperature range (lower than 70 DEG C) that mercury cadmium telluride can bear, and the dielectric film of low-temperature epitaxy (< 100 DEG C) mostly is columnar-shaped polycrystalline structure, there is pin hole in surface, has a strong impact on the mask blocks effect of film; 2) the hard mask layer (SiO of existing technique employing 2, graphite, amorphous carbon etc.) there is larger lattice mismatch with mercury cadmium telluride, the tack of film is poor; 3) hard mask needs multistep photoetching and graphically etches, and the dimension of picture fabrication error of introducing is many, makes the pattern precision of small size injection region be difficult to ensure.Therefore, must consider that the energetic ion adopting the process program beyond prior art to solve mercury cadmium telluride injects preparation and the removal problem of mask.
Summary of the invention
The object of this patent is to provide a kind of compound mask structure injected for energetic ion.
In this patent, mask comprises implant blocking layer 1, photoresist mask layer 2, sacrificial dielectric layer 3; Its structure is: the bottom of compound mask is implant blocking layer 1, and middle part is for having the photoresist mask layer 2 of mask pattern, and upper strata is sacrificial dielectric layer 3;
Described implant blocking layer 1 is the media coating that 20 ~ 200nm is thick, adopts tellurium zinc cadmium, zinc telluridse or the cadmium telluride material little with mercury cadmium telluride lattice mismatch;
Described sacrificial dielectric layer 3 is the silicon dioxide or zinc sulfide film layer that 20 ~ 200nm is thick.
The preparation method of the compound mask structure described in this patent refers to and obtain injection region mask pattern after growth has the mercury cadmium telluride chip surface of implant blocking layer deielectric-coating to adopt positive photoresist exposure photo-etching, adopt positive negative incidence deposition process in injection region, photoresist mask sidewalls and deposited atop sacrificial dielectric film, obtain compound and inject mask.The minimizing technology of the compound mask described in this patent refers to and adopts the method for wet etching, exposure imaging, wet etching to remove sacrificial dielectric film, photoresist and implant blocking layer successively successively.
The processing step of the preparation method of mask is specific as follows:
1) chip depositing implant blocking layer deielectric-coating cleaned up and dry, at chip surface rotary coating one deck positive photoresist, with lithography mask version, exposure imaging and rear baking post bake are carried out to chip, prepare photoresist injection region mask pattern;
2) chip preparing mask pattern is loaded on sample stage, first with 0 ° of inclination angle specimen rotating holder, the sacrificial dielectric film of deposition gross thickness 20% ~ 80%; Again with ﹢ 20 ° ~ ﹢ 50 ° of inclination angle specimen rotating holders, the sacrificial dielectric film of deposition gross thickness 10% ~ 40%; Last with ﹣ 20 ° ~ ﹣ 50 ° of inclination angle specimen rotating holders, the sacrificial dielectric film of deposition gross thickness 10% ~ 40%; Final acquisition thickness is the sacrificial dielectric film of 20 ~ 200nm.
The processing step of the minimizing technology of mask is specific as follows:
1) chip after ion implantation is clean by washed with de-ionized water, then immerse in sacrificial dielectric layer 3 corrosive liquid and corrode, until sacrificial dielectric film is removed clean, use deionized water rinsed clean;
2) with ultraviolet lithography machine to chip maskless lithography 60 ~ 120 seconds, then soak 1 ~ 3 minute with developer solution, remove photoresist mask layer 2, then use deionized water rinsed clean;
3) chip is immersed in implant blocking layer 1 corrosive liquid and corrode, until implant blocking layer deielectric-coating is removed clean, use deionized water rinsed clean.
This patent tool has the following advantages:
1. the sacrificial dielectric film of soft photoresist mask pattern by positive negative incidence deposition is protected by the compound mask that prepared by this patent; effectively prevent photoresist mask surface; the particularly sex change of marginal portion under high-energy ion bombardment and the generation of crack, avoids the problem that the device technology failure that causes therefrom and mask easily remain.
2. photoresist mask adopts exposure imaging method to remove, and shortens the time of removing photoresist, and mask is removed completely, noresidue.
Accompanying drawing explanation
Fig. 1 is the structural representation of compound mask.
Fig. 2 is the preparation of compound mask and removes process chart, wherein, figure (1) is deposition implant blocking layer, figure (2) is positive photoresist photoetching, figure (3) is positive negative incidence deposited sacrificial deielectric-coating, and figure (4) is ion implantation, and figure (5) sacrifices barrier layer for corroding, figure (6) removes photoresist for exposure imaging, schemes (7) for corrosion implant blocking layer.
Embodiment
Below in conjunction with accompanying drawing, with pixel dimension be 30 microns, array scale be 20 × 3 mercury cadmium telluride chip be that the execution mode of example to this patent elaborates:
The embodiment of this patent adopts the tellurium cadmium mercury epitaxial material chip having deposited cadmium telluride implant blocking layer to prepare the compound mask of sandwich structure.The preparation method of the compound mask described in this patent refers to the implant blocking layer depositing specific thicknesses on tellurium cadmium mercury epitaxial material chip, then injection region mask pattern is obtained after utilizing positive photoresist exposure imaging, adopt positive negative incidence deposition process at top, injection region, photoresist mask sidewalls and deposited atop sacrificial dielectric film, obtain the compound mask with sandwich structure, as shown in Figure 1.
Embodiment 1:
Adopt the mask preparation method described in this patent, carry out hydatogenesis, photoetching and positive negative incidence hydatogenesis at tellurium cadmium mercury epitaxial material chip surface, preparation technology's flow process as shown in Figure 2.First the cadmium telluride implant blocking layer (as Suo Shi Fig. 2 (1)) that the tellurium cadmium mercury epitaxial material chip surface thermal evaporation deposition ~ 60nm after carrying out annealing in process and surface corrosion process is thick, chip is cleaned up, at the positive photoresist of chip surface rotary coating a layer thickness 2 ~ 3 micron thickness, by reticle, ultraviolet photoetching is carried out to chip, after developing and be fixing, obtain photoresist and inject mask (as Suo Shi Fig. 2 (2)).
The chip preparing mask pattern is loaded on the sample stage of high vacuum thermal evaporation apparatus, first with 0 ° of inclination angle specimen rotating holder, the zinc sulfide film that deposition ~ 20nm is thick; Again with 45 ° of inclination angle specimen rotating holders, the zinc sulfide film that deposition ~ 20nm is thick; Last with ﹣ 45 ° of inclination angle specimen rotating holders, the zinc sulfide film that deposition ~ 20nm is thick; Final acquisition thickness is ~ the zinc sulphide sacrificial dielectric film of 60nm, obtain the compound mask (as Suo Shi Fig. 2 (3)) with sandwich structure.
The mercury cadmium telluride chip of this injection mask is had with the energy injection As of 300KeV to preparation +ion (as Suo Shi Fig. 2 (4)).Carry out sediments microscope inspection to the chip after injecting, mask is intact, and mask sex change and crack do not occur.Adopt the mask minimizing technology described in this patent, mercury cadmium telluride chip surface after ion implantation carries out wet etching, uv-exposure and development, and mask removes technological process as shown in Figure 2.By clean for the chip washed with de-ionized water after ion implantation, and dry up with nitrogen, then immerse in hcl corrosion liquid and corrode 3 ~ 4 seconds, until sacrificial dielectric film is removed clean, use deionized water rinsed clean, and dry up (as Suo Shi Fig. 2 (5)) with nitrogen.
With ultraviolet lithography machine to chip maskless lithography 90 ~ 120 seconds, then soak 2 ~ 3 minutes with developer solution, remove photoresist mask layer, then use deionized water rinsed clean (as Suo Shi Fig. 2 (6)).Chip is immersed in the aqueous solution of SPA, hydrogen peroxide, corrode 4 ~ 5 seconds, until cadmium telluride barrier layer deielectric-coating is removed clean, with deionized water rinsed clean (as Suo Shi Fig. 2 (7)).Sediments microscope inspection is carried out to chip surface, remains without mask.
Embodiment 2:
Adopt the mask preparation method described in this patent, carry out hydatogenesis, photoetching and positive negative incidence sputtering sedimentation at tellurium cadmium mercury epitaxial material chip surface, preparation technology's flow process as shown in Figure 2.First the cadmium telluride implant blocking layer (as Suo Shi Fig. 2 (1)) that the tellurium cadmium mercury epitaxial material chip surface thermal evaporation deposition ~ 20nm after carrying out annealing in process and surface corrosion process is thick, chip is cleaned up, at the positive photoresist of chip surface rotary coating a layer thickness 2 ~ 3 micron thickness, by reticle, ultraviolet photoetching is carried out to chip, after developing and be fixing, obtain photoresist and inject mask (as Suo Shi Fig. 2 (2)).
The chip preparing mask pattern is loaded on the sample stage of magnetron sputtering apparatus, first with 0 ° of inclination angle specimen rotating holder, the silica membrane that sputtering ~ 10nm is thick; Again with 45 ° of inclination angle specimen rotating holders, the silica membrane that sputtering ~ 5nm is thick; Last with ﹣ 45 ° of inclination angle specimen rotating holders, the silica membrane that sputtering ~ 5nm is thick; Final acquisition thickness is ~ the silicon dioxide sacrificial dielectric film of 20nm, obtain the compound mask (as Suo Shi Fig. 2 (3)) with sandwich structure.
The mercury cadmium telluride chip of this injection mask is had with the energy injection As of 300KeV to preparation +ion (as Suo Shi Fig. 2 (4)).Carry out sediments microscope inspection to the chip after injecting, mask is intact, and mask sex change and crack do not occur.Adopt the mask minimizing technology described in this patent, mercury cadmium telluride chip surface after ion implantation carries out wet etching, uv-exposure and development, and mask removes technological process as shown in Figure 2.Chip after ion implantation is clean by washed with de-ionized water, and dry up with nitrogen, then immerse in HF buffered etch liquid and corrode 6 ~ 8 seconds, until sacrificial dielectric film is removed clean, with deionized water rinsed clean (as Suo Shi Fig. 2 (5)).
With ultraviolet lithography machine to chip maskless lithography 90 ~ 120 seconds, then soak 2 ~ 3 minutes with developer solution, remove photoresist mask layer, then use deionized water rinsed clean (as Suo Shi Fig. 2 (6)).Chip is immersed in the aqueous solution of SPA, hydrogen peroxide, corrode 4 ~ 5 seconds, until cadmium telluride barrier layer deielectric-coating is removed clean, with deionized water rinsed clean (as Suo Shi Fig. 2 (7)).Sediments microscope inspection is carried out to chip surface, remains without mask.
Embodiment 3:
Adopt the mask preparation method described in this patent, carry out hydatogenesis, photoetching and positive negative incidence hydatogenesis at tellurium cadmium mercury epitaxial material chip surface, preparation technology's flow process as shown in Figure 2.First the cadmium telluride implant blocking layer (as Suo Shi Fig. 2 (1)) that the tellurium cadmium mercury epitaxial material chip surface thermal evaporation deposition ~ 200nm after carrying out annealing in process and surface corrosion process is thick, chip is cleaned up, at the positive photoresist of chip surface rotary coating a layer thickness 2 ~ 3 micron thickness, by reticle, ultraviolet photoetching is carried out to chip, after developing and be fixing, obtain photoresist and inject mask (as Suo Shi Fig. 2 (2)).
The chip preparing mask pattern is loaded on the sample stage of high vacuum thermal evaporation apparatus, first with 0 ° of inclination angle specimen rotating holder, the zinc sulfide film that deposition ~ 80nm is thick; Again with 45 ° of inclination angle specimen rotating holders, the zinc sulfide film that deposition ~ 60nm is thick; Last with ﹣ 45 ° of inclination angle specimen rotating holders, the zinc sulfide film that deposition ~ 60nm is thick; Final acquisition thickness is ~ the zinc sulphide sacrificial dielectric film of 200nm, obtain the compound mask (as Suo Shi Fig. 2 (3)) with sandwich structure.
The mercury cadmium telluride chip of this injection mask is had with the energy injection As of 300KeV to preparation +ion (as Suo Shi Fig. 2 (4)).Carry out sediments microscope inspection to the chip after injecting, mask is intact, and mask sex change and crack do not occur.Adopt the mask minimizing technology described in this patent, mercury cadmium telluride chip surface after ion implantation carries out wet etching, uv-exposure and development, and mask removes technological process as shown in Figure 2.Chip after ion implantation is clean by washed with de-ionized water, and dry up with nitrogen, then immerse in hcl corrosion liquid and corrode 5 ~ 7 seconds, until sacrificial dielectric film is removed clean, with deionized water rinsed clean (as Suo Shi Fig. 2 (5)).
With ultraviolet lithography machine to chip maskless lithography 90 ~ 120 seconds, then soak 2 ~ 3 minutes with developer solution, remove photoresist mask layer, then use deionized water rinsed clean (as Suo Shi Fig. 2 (6)).Chip is immersed in the aqueous solution of SPA, hydrogen peroxide, corrode 4 ~ 5 seconds, until cadmium telluride barrier layer deielectric-coating is removed clean, with deionized water rinsed clean (as Suo Shi Fig. 2 (7)).Sediments microscope inspection is carried out to chip surface, remains without mask.

Claims (1)

1., for the compound mask that energetic ion injects, it comprises implant blocking layer (1), photoresist mask layer (2), sacrificial dielectric layer (3); It is characterized in that:
The bottom of described compound mask is implant blocking layer (1), and middle part is for having the photoresist mask layer (2) of mask pattern, and upper strata is sacrificial dielectric layer (3);
Described implant blocking layer (1) is the media coating that 20 ~ 200nm is thick, adopts tellurium zinc cadmium, zinc telluridse or the cadmium telluride material little with mercury cadmium telluride lattice mismatch;
Described sacrificial dielectric layer (3) is the silicon dioxide or zinc sulfide film layer that 20 ~ 200nm is thick.
CN201520371989.7U 2015-01-21 2015-06-02 For the compound mask that energetic ion injects Active CN204680649U (en)

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CN107622940B (en) * 2017-09-01 2019-09-27 中国科学院上海技术物理研究所 A kind of preparation method of the energetic ion injection layered mask easily to remove photoresist
US10937869B2 (en) 2018-09-28 2021-03-02 General Electric Company Systems and methods of masking during high-energy implantation when fabricating wide band gap semiconductor devices
US11056586B2 (en) 2018-09-28 2021-07-06 General Electric Company Techniques for fabricating charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) devices
CN113782416B (en) * 2021-09-13 2024-03-05 安徽光智科技有限公司 Tellurium-cadmium-mercury liquid phase epitaxial growth source substrate and preparation method thereof, and tellurium-cadmium-mercury liquid phase epitaxial growth method

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FR2336804A1 (en) * 1975-12-23 1977-07-22 Telecommunications Sa IMPROVEMENTS MADE TO SEMICONDUCTOR DEVICES, ESPECIALLY TO PHOTOVOLTAIC DETECTORS INCLUDING A SUBSTRATE BASED ON A CDXHG1-XTE ALLOY, AND PROCESS FOR MANUFACTURING SUCH A PERFECTED DEVICE
US6030853A (en) * 1993-08-13 2000-02-29 Drs Fpa, L.P. Method of producing intrinsic p-type HgCdTe using CdTe capping layer
CN101226971A (en) * 2008-02-01 2008-07-23 中国科学院上海技术物理研究所 Method for reducing ion implantation damage influence of mercury cadmium telluride photovoltaic device
CN101425552B (en) * 2008-10-20 2010-08-11 淮阴师范学院 Method for preparing high performance mercury cadmium telluride p-n junction by ion injection
CN102496559A (en) * 2011-11-25 2012-06-13 中国科学院微电子研究所 Three-layer composite ion implantation barrier layer and preparation and removal methods thereof

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