CN104576335A - Composite mask for high-energy ion implantation - Google Patents
Composite mask for high-energy ion implantation Download PDFInfo
- Publication number
- CN104576335A CN104576335A CN201510028930.2A CN201510028930A CN104576335A CN 104576335 A CN104576335 A CN 104576335A CN 201510028930 A CN201510028930 A CN 201510028930A CN 104576335 A CN104576335 A CN 104576335A
- Authority
- CN
- China
- Prior art keywords
- mask
- layer
- chip
- photoresist
- cadmium telluride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/42—Bombardment with radiation
- H01L21/423—Bombardment with radiation with high-energy radiation
- H01L21/425—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/426—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
Abstract
The invention discloses a composite mask for high-energy ion implantation. The mask is a composite photoresist mask of a three-layer structure. According to the mask, a photoresist mask pattern is manufactured between an implantation barrier layer dielectric film and a surface layer sacrifice dielectric film and used as a high-energy ion implantation mask. By the adoption of the composite mask, the problem of chapping denaturation of the photoresist mask under high-energy ion bombardment can be solved, the mask is removed without residues, the surface cleanness of a chip is guaranteed, and device performance is improved.
Description
Technical field
The present invention relates to the mask technique in microelectronic technique, specifically refer to a kind of compound mask structure injected for mercury cadmium telluride energetic ion.
Background technology
Infrared focal plane array seeker based on HgCdTe photodiode has been widely used in the fields such as military security, resource exploration, marine monitoring and space remote sensing.Divide by device architecture, HgCdTe photodiode can be divided into n-on-p type and p-on-n type.The technological accumulation that n-on-p technique goes through decades has been tending towards ripe, has had higher performance based on the short-wave infrared (SWIR) of this technique and medium-wave infrared (MWIR) HgCdTe FPA device.But, for long wave (LW) and very long wave (VLW) device, in order to obtain the spectral response of corresponding spectral coverage, the energy gap of HgCdTe base material must be reduced (< 90meV) further.Under energy gap narrow like this, the tunnelling current component in device dark electric current will become very remarkable.P-on-n type device significantly can suppress tunnelling current, reduces dark current and reduce the series resistance of light absorbing zone, has the incomparable advantage of n-on-p type device at long wave/very long wave and large area HgCdTe infrared focal plane detector array application aspect.Compared with plane pn knot technique in p-on-n type detector ties technique with table top pn, there is the advantage that technique easily realizes, surface passivation technology simple, device consistency is good.One of its core technology is exactly the ion implantation technique of p-type impurity, and dopant is V group element, the most conventional with arsenic element.The atomic mass of arsenic is large, diffusion coefficient is very little, and in order to arsenic ion being injected into the applicable degree of depth meeting device performance requirements, high-energy must be adopted to carry out ion implantation, and Implantation Energy is higher than 300KeV.Under high-octane like this heavy nucleus Ions Bombardment, not only mercury cadmium telluride top layer can produce damage defect, and conventional photoresist mask also cannot bear, and sex change can occur and chap, thus thoroughly cannot remove the problem of mask after causing technique failure and injection.
At present, in silicon-based semiconductor devices technique, the soft mask sex change under Ions Bombardment such in order to avoid photoresist and the problem easily remained, some semiconductor device manufacturer proposes hard mask scheme, namely using patterned hard dielectric film as injection mask.As, BOE science and technology proposes to prepare graphite film at substrate surface, by patterning processes formed graphite mask layer (list of references: a kind of method of ion implantation. Chinese invention patent, CN103972062A); China's power microelectronics proposes at substrat structure surface deposition amorphous state carbon-coating as injection masking layer, deposit hard mask layer thereon, cover photoresist again, by photoetching with repeatedly graphically etch, acquisition amorphous state carbon-coating mask (list of references: a kind of manufacture method of ion implantation barrier layer. Chinese invention patent, CN102683184A).Although hard mask avoids photoresist mask by bombardment sex change and easily residual problem, it needs to deposit extra deielectric-coating, and carries out multistep photoetching and etching, complex process.The reason that hard mask is not suitable for HgCdTe device is: 1) depositing temperature of hard mask layer far exceedes the temperature range (lower than 70 DEG C) that mercury cadmium telluride can bear, and the dielectric film of low-temperature epitaxy (< 100 DEG C) mostly is columnar-shaped polycrystalline structure, there is pin hole in surface, has a strong impact on the mask blocks effect of film; 2) the hard mask layer (SiO of existing technique employing
2, graphite, amorphous carbon etc.) there is larger lattice mismatch with mercury cadmium telluride, the tack of film is poor; 3) hard mask needs multistep photoetching and graphically etches, and the dimension of picture fabrication error of introducing is many, makes the pattern precision of small size injection region be difficult to ensure.Therefore, must consider that the energetic ion adopting the process program beyond prior art to solve mercury cadmium telluride injects preparation and the removal problem of mask.
Summary of the invention
The object of this invention is to provide a kind of compound mask structure injected for mercury cadmium telluride energetic ion.
In the present invention, mask comprises implant blocking layer 1, photoresist mask layer 2, sacrificial dielectric layer 3; Its structure is: the bottom of compound mask is implant blocking layer 1, and middle part is for having the photoresist mask layer 2 of mask pattern, and upper strata is sacrificial dielectric layer 3;
Described implant blocking layer 1 is the media coating that 20 ~ 200nm is thick, adopts the material less with mercury cadmium telluride lattice mismatch: tellurium zinc cadmium, zinc telluridse or cadmium telluride;
Described sacrificial dielectric layer 3 is the silicon dioxide or zinc sulfide film layer that 20 ~ 200nm is thick.
The preparation method of the compound mask structure described in the present invention refers to and obtain injection region mask pattern after growth has the mercury cadmium telluride chip surface of implant blocking layer deielectric-coating to adopt positive photoresist exposure photo-etching, adopt positive negative incidence deposition process in injection region, photoresist mask sidewalls and deposited atop sacrificial dielectric film, obtain compound and inject mask.The minimizing technology of the compound mask described in the present invention refers to and adopts the method for wet etching, exposure imaging, wet etching to remove sacrificial dielectric film, photoresist and implant blocking layer successively successively.
The processing step of the preparation method of mask is specific as follows:
1) chip depositing implant blocking layer deielectric-coating cleaned up and dry, at chip surface rotary coating one deck positive photoresist, with lithography mask version, exposure imaging and rear baking post bake are carried out to chip, prepare photoresist injection region mask pattern;
2) chip preparing mask pattern is loaded on sample stage, first with 0 ° of inclination angle specimen rotating holder, the sacrificial dielectric film of deposition gross thickness 20% ~ 80%; Again with ﹢ 20 ° ~ ﹢ 50 ° of inclination angle specimen rotating holders, the sacrificial dielectric film of deposition gross thickness 10% ~ 40%; Last with ﹣ 20 ° ~ ﹣ 50 ° of inclination angle specimen rotating holders, the sacrificial dielectric film of deposition gross thickness 10% ~ 40%; Final acquisition thickness is the sacrificial dielectric film of 20 ~ 200nm.
The processing step of the minimizing technology of mask is specific as follows:
1) chip after ion implantation is clean by washed with de-ionized water, then immerse in sacrificial dielectric layer 3 corrosive liquid and corrode, until sacrificial dielectric film is removed clean, use deionized water rinsed clean;
2) with ultraviolet lithography machine to chip maskless lithography 60 ~ 120 seconds, then soak 1 ~ 3 minute with developer solution, remove photoresist mask layer 2, then use deionized water rinsed clean;
3) chip is immersed in implant blocking layer 1 corrosive liquid and corrode, until implant blocking layer deielectric-coating is removed clean, use deionized water rinsed clean.
Tool of the present invention has the following advantages:
1. the sacrificial dielectric film of soft photoresist mask pattern by positive negative incidence deposition is protected by the compound mask that prepared by the present invention; effectively prevent photoresist mask surface; the particularly sex change of marginal portion under high-energy ion bombardment and the generation of crack, avoids the problem that the device technology failure that causes therefrom and mask easily remain.
2. photoresist mask adopts exposure imaging method to remove, and shortens the time of removing photoresist, and mask is removed completely, noresidue.
Accompanying drawing explanation
Fig. 1 is the structural representation of compound mask.
Fig. 2 is the preparation of compound mask and removes process chart.
Embodiment
Below in conjunction with accompanying drawing, with pixel dimension be 30 microns, array scale be 20 × 3 mercury cadmium telluride chip be that example elaborates to embodiments of the present invention:
Embodiments of the invention adopt the tellurium cadmium mercury epitaxial material chip having deposited cadmium telluride implant blocking layer to prepare the compound mask of sandwich structure.The preparation method of the compound mask described in the present invention refers to the implant blocking layer depositing specific thicknesses on tellurium cadmium mercury epitaxial material chip, then injection region mask pattern is obtained after utilizing positive photoresist exposure imaging, adopt positive negative incidence deposition process at top, injection region, photoresist mask sidewalls and deposited atop sacrificial dielectric film, obtain the compound mask with sandwich structure, as shown in Figure 1.
Embodiment 1:
Adopt the mask preparation method described in the present invention, carry out hydatogenesis, photoetching and positive negative incidence hydatogenesis at tellurium cadmium mercury epitaxial material chip surface, preparation technology's flow process as shown in Figure 2.First the cadmium telluride implant blocking layer that the tellurium cadmium mercury epitaxial material chip surface thermal evaporation deposition ~ 60nm after carrying out annealing in process and surface corrosion process is thick, chip is cleaned up, at the positive photoresist of chip surface rotary coating a layer thickness 2 ~ 3 micron thickness, by reticle, ultraviolet photoetching is carried out to chip, after developing and be fixing, obtain photoresist and inject mask.
The chip preparing mask pattern is loaded on the sample stage of high vacuum thermal evaporation apparatus, first with 0 ° of inclination angle specimen rotating holder, the zinc sulfide film that deposition ~ 20nm is thick; Again with 45 ° of inclination angle specimen rotating holders, the zinc sulfide film that deposition ~ 20nm is thick; Last with ﹣ 45 ° of inclination angle specimen rotating holders, the zinc sulfide film that deposition ~ 20nm is thick; Final acquisition thickness is ~ the zinc sulphide sacrificial dielectric film of 60nm, obtain the compound mask with sandwich structure.
The mercury cadmium telluride chip of this injection mask is had with the energy injection As of 300KeV to preparation
+ion.Carry out sediments microscope inspection to the chip after injecting, mask is intact, and mask sex change and crack do not occur.Adopt mask minimizing technology of the present invention, mercury cadmium telluride chip surface after ion implantation carries out wet etching, uv-exposure and development, and mask removes technological process as shown in Figure 2.Chip after ion implantation is clean by washed with de-ionized water, and dry up with nitrogen, then immerse in hcl corrosion liquid and corrode 3 ~ 4 seconds, until sacrificial dielectric film is removed clean, use deionized water rinsed clean, and dry up with nitrogen.
With ultraviolet lithography machine to chip maskless lithography 90 ~ 120 seconds, then soak 2 ~ 3 minutes with developer solution, remove photoresist mask layer, then use deionized water rinsed clean.Chip is immersed in the aqueous solution of SPA, hydrogen peroxide, corrode 4 ~ 5 seconds, until cadmium telluride barrier layer deielectric-coating is removed clean, use deionized water rinsed clean.Sediments microscope inspection is carried out to chip surface, remains without mask.
Embodiment 2:
Adopt the mask preparation method described in the present invention, carry out hydatogenesis, photoetching and positive negative incidence sputtering sedimentation at tellurium cadmium mercury epitaxial material chip surface, preparation technology's flow process as shown in Figure 2.First the cadmium telluride implant blocking layer that the tellurium cadmium mercury epitaxial material chip surface thermal evaporation deposition ~ 20nm after carrying out annealing in process and surface corrosion process is thick, chip is cleaned up, at the positive photoresist of chip surface rotary coating a layer thickness 2 ~ 3 micron thickness, by reticle, ultraviolet photoetching is carried out to chip, after developing and be fixing, obtain photoresist and inject mask.
The chip preparing mask pattern is loaded on the sample stage of magnetron sputtering apparatus, first with 0 ° of inclination angle specimen rotating holder, the silica membrane that sputtering ~ 10nm is thick; Again with 45 ° of inclination angle specimen rotating holders, the silica membrane that sputtering ~ 5nm is thick; Last with ﹣ 45 ° of inclination angle specimen rotating holders, the silica membrane that sputtering ~ 5nm is thick; Final acquisition thickness is ~ the silicon dioxide sacrificial dielectric film of 20nm, obtain the compound mask with sandwich structure.
The mercury cadmium telluride chip of this injection mask is had with the energy injection As of 300KeV to preparation
+ion.Carry out sediments microscope inspection to the chip after injecting, mask is intact, and mask sex change and crack do not occur.Adopt mask minimizing technology of the present invention, mercury cadmium telluride chip surface after ion implantation carries out wet etching, uv-exposure and development, and mask removes technological process as shown in Figure 2.Chip after ion implantation is clean by washed with de-ionized water, and dry up with nitrogen, then immerse in HF buffered etch liquid and corrode 6 ~ 8 seconds, until sacrificial dielectric film is removed clean, use deionized water rinsed clean.
With ultraviolet lithography machine to chip maskless lithography 90 ~ 120 seconds, then soak 2 ~ 3 minutes with developer solution, remove photoresist mask layer, then use deionized water rinsed clean.Chip is immersed in the aqueous solution of SPA, hydrogen peroxide, corrode 4 ~ 5 seconds, until cadmium telluride barrier layer deielectric-coating is removed clean, use deionized water rinsed clean.Sediments microscope inspection is carried out to chip surface, remains without mask.
Embodiment 3:
Adopt the mask preparation method described in the present invention, carry out hydatogenesis, photoetching and positive negative incidence hydatogenesis at tellurium cadmium mercury epitaxial material chip surface, preparation technology's flow process as shown in Figure 2.First the cadmium telluride implant blocking layer that the tellurium cadmium mercury epitaxial material chip surface thermal evaporation deposition ~ 200nm after carrying out annealing in process and surface corrosion process is thick, chip is cleaned up, at the positive photoresist of chip surface rotary coating a layer thickness 2 ~ 3 micron thickness, by reticle, ultraviolet photoetching is carried out to chip, after developing and be fixing, obtain photoresist and inject mask.
The chip preparing mask pattern is loaded on the sample stage of high vacuum thermal evaporation apparatus, first with 0 ° of inclination angle specimen rotating holder, the zinc sulfide film that deposition ~ 80nm is thick; Again with 45 ° of inclination angle specimen rotating holders, the zinc sulfide film that deposition ~ 60nm is thick; Last with ﹣ 45 ° of inclination angle specimen rotating holders, the zinc sulfide film that deposition ~ 60nm is thick; Final acquisition thickness is ~ the zinc sulphide sacrificial dielectric film of 200nm, obtain the compound mask with sandwich structure.
The mercury cadmium telluride chip of this injection mask is had with the energy injection As of 300KeV to preparation
+ion.Carry out sediments microscope inspection to the chip after injecting, mask is intact, and mask sex change and crack do not occur.Adopt mask minimizing technology of the present invention, mercury cadmium telluride chip surface after ion implantation carries out wet etching, uv-exposure and development, and mask removes technological process as shown in Figure 2.Chip after ion implantation is clean by washed with de-ionized water, and dry up with nitrogen, then immerse in hcl corrosion liquid and corrode 5 ~ 7 seconds, until sacrificial dielectric film is removed clean, use deionized water rinsed clean.
With ultraviolet lithography machine to chip maskless lithography 90 ~ 120 seconds, then soak 2 ~ 3 minutes with developer solution, remove photoresist mask layer, then use deionized water rinsed clean.Chip is immersed in the aqueous solution of SPA, hydrogen peroxide, corrode 4 ~ 5 seconds, until cadmium telluride barrier layer deielectric-coating is removed clean, use deionized water rinsed clean.Sediments microscope inspection is carried out to chip surface, remains without mask.
Claims (1)
1., for the compound mask that mercury cadmium telluride energetic ion injects, it comprises implant blocking layer (1), photoresist mask layer (2), sacrificial dielectric layer (3); It is characterized in that:
The bottom of described compound mask is implant blocking layer (1), and middle part is for having the photoresist mask layer (2) of mask pattern, and upper strata is sacrificial dielectric layer (3);
Described implant blocking layer (1) is the media coating that 20 ~ 200nm is thick, adopts the material less with mercury cadmium telluride lattice mismatch: tellurium zinc cadmium, zinc telluridse or cadmium telluride;
Described sacrificial dielectric layer (3) is the silicon dioxide or zinc sulfide film layer that 20 ~ 200nm is thick.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510028930.2A CN104576335A (en) | 2015-01-21 | 2015-01-21 | Composite mask for high-energy ion implantation |
| CN201510295752.XA CN104867837A (en) | 2015-01-21 | 2015-06-02 | Composite mask for high energy ion implantation |
| CN201520371989.7U CN204680649U (en) | 2015-01-21 | 2015-06-02 | For the compound mask that energetic ion injects |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510028930.2A CN104576335A (en) | 2015-01-21 | 2015-01-21 | Composite mask for high-energy ion implantation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104576335A true CN104576335A (en) | 2015-04-29 |
Family
ID=53092118
Family Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510028930.2A Pending CN104576335A (en) | 2015-01-21 | 2015-01-21 | Composite mask for high-energy ion implantation |
| CN201520371989.7U Active CN204680649U (en) | 2015-01-21 | 2015-06-02 | For the compound mask that energetic ion injects |
| CN201510295752.XA Pending CN104867837A (en) | 2015-01-21 | 2015-06-02 | Composite mask for high energy ion implantation |
Family Applications After (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520371989.7U Active CN204680649U (en) | 2015-01-21 | 2015-06-02 | For the compound mask that energetic ion injects |
| CN201510295752.XA Pending CN104867837A (en) | 2015-01-21 | 2015-06-02 | Composite mask for high energy ion implantation |
Country Status (1)
| Country | Link |
|---|---|
| CN (3) | CN104576335A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107622940A (en) * | 2017-09-01 | 2018-01-23 | 中国科学院上海技术物理研究所 | A kind of preparation method of the energetic ion injection layered mask easily to remove photoresist |
| US10937869B2 (en) | 2018-09-28 | 2021-03-02 | General Electric Company | Systems and methods of masking during high-energy implantation when fabricating wide band gap semiconductor devices |
| US11056586B2 (en) | 2018-09-28 | 2021-07-06 | General Electric Company | Techniques for fabricating charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) devices |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113782416B (en) * | 2021-09-13 | 2024-03-05 | 安徽光智科技有限公司 | Tellurium-cadmium-mercury liquid phase epitaxial growth source substrate and preparation method thereof, and tellurium-cadmium-mercury liquid phase epitaxial growth method |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2336804A1 (en) * | 1975-12-23 | 1977-07-22 | Telecommunications Sa | IMPROVEMENTS MADE TO SEMICONDUCTOR DEVICES, ESPECIALLY TO PHOTOVOLTAIC DETECTORS INCLUDING A SUBSTRATE BASED ON A CDXHG1-XTE ALLOY, AND PROCESS FOR MANUFACTURING SUCH A PERFECTED DEVICE |
| US6030853A (en) * | 1993-08-13 | 2000-02-29 | Drs Fpa, L.P. | Method of producing intrinsic p-type HgCdTe using CdTe capping layer |
| CN101226971A (en) * | 2008-02-01 | 2008-07-23 | 中国科学院上海技术物理研究所 | Method for reducing ion implantation damage influence of mercury cadmium telluride photovoltaic device |
| CN101425552B (en) * | 2008-10-20 | 2010-08-11 | 淮阴师范学院 | Method for preparing high performance mercury cadmium telluride p-n junction by ion injection |
| CN102496559A (en) * | 2011-11-25 | 2012-06-13 | 中国科学院微电子研究所 | Three-layer composite ion implantation barrier layer and preparation and removal method thereof |
-
2015
- 2015-01-21 CN CN201510028930.2A patent/CN104576335A/en active Pending
- 2015-06-02 CN CN201520371989.7U patent/CN204680649U/en active Active
- 2015-06-02 CN CN201510295752.XA patent/CN104867837A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107622940A (en) * | 2017-09-01 | 2018-01-23 | 中国科学院上海技术物理研究所 | A kind of preparation method of the energetic ion injection layered mask easily to remove photoresist |
| CN107622940B (en) * | 2017-09-01 | 2019-09-27 | 中国科学院上海技术物理研究所 | A kind of preparation method of the energetic ion injection layered mask easily to remove photoresist |
| US10937869B2 (en) | 2018-09-28 | 2021-03-02 | General Electric Company | Systems and methods of masking during high-energy implantation when fabricating wide band gap semiconductor devices |
| US11056586B2 (en) | 2018-09-28 | 2021-07-06 | General Electric Company | Techniques for fabricating charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) devices |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104867837A (en) | 2015-08-26 |
| CN204680649U (en) | 2015-09-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101991767B1 (en) | Solar cell having an emitter region with wide bandgap semiconductor material | |
| JP2020092269A (en) | Solar battery emitter region manufacture using ion implantation | |
| CN204680649U (en) | For the compound mask that energetic ion injects | |
| JP2017509142A (en) | Antireflective layer for backside illuminated sensors | |
| WO2014042114A1 (en) | Photoelectric conversion element and method for manufacturing photoelectric conversion element | |
| WO2009055778A1 (en) | Method for manufacturing lateral germanium detectors | |
| KR20110063546A (en) | Method for fabricating a solar cell using a direct-pattern pin-hole-free masking layer | |
| KR20160062004A (en) | Electro-polishing and porosification | |
| US20100029033A1 (en) | Method for Manufacturing Vertical Germanium Detectors | |
| US20120138139A1 (en) | Dry etching method of surface texture formation on silicon wafer | |
| CN109537049A (en) | Molecular beam epitaxy cadmium-zinc-teiluride substrate pre-treatment method | |
| CN104616974A (en) | Removal method of composite mask for injecting high-energy particles | |
| JP4319006B2 (en) | Method for manufacturing solar battery cell | |
| CN107507882B (en) | Mesa type silicon-doped arsenic-blocking impurity band detector and preparation method thereof | |
| US10861987B2 (en) | Method for manufacturing selective emitter using surface structure and solar cell including selective emitter using surface structure | |
| CN105762221B (en) | A kind of HgCdTe device buries knot technique | |
| CN104576832B (en) | Blocking impurity band detector manufacturing method based on SOI | |
| KR101161807B1 (en) | Method of manufacturing Back junction solar cell by using plasma doping and diffusion and the solar cell | |
| CN102244145A (en) | Excessive-plating prevention dual-layer thin film as well as preparation method and application thereof | |
| CN104599958A (en) | Preparation method of composite mask for high-energy ion implantation | |
| KR101652342B1 (en) | Texturing method of solar cell surface | |
| CN107622940B (en) | A kind of preparation method of the energetic ion injection layered mask easily to remove photoresist | |
| Kong et al. | Fabrication of silicon pyramid-nanocolumn structures with lowest reflectance by reactive ion etching method | |
| Liu | Low temperature pure boron layer deposition for silicon diode and micromachining applications | |
| CN108682622A (en) | The electrical contact hole lithographic method of HgCdTe device passivation layers |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150429 |