CN116544248A - Image sensor forming method and image sensor - Google Patents
Image sensor forming method and image sensor Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 74
- 239000004065 semiconductor Substances 0.000 claims abstract description 95
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- 229920005591 polysilicon Polymers 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 32
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- 230000001681 protective effect Effects 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 4
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- 230000005669 field effect Effects 0.000 claims description 3
- 238000004891 communication Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000003491 array Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
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- 239000003989 dielectric material Substances 0.000 description 2
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- 239000013078 crystal Substances 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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Abstract
The invention provides an image sensor forming method, which comprises the following steps: etching the semiconductor substrate according to a preset hard mask layer before the grid electrode is formed to form semiconductor island structures arranged in an array, wherein at least the upper parts of the semiconductor island structures are connected with at least one other semiconductor island structure through a connecting structure, and first grooves communicated with each other are formed between the semiconductor island structures; and filling polysilicon in the first groove to form a polysilicon grid electrode which is used as a pinning layer of the side wall of the semiconductor island-shaped structure. Compared with the existing image sensor forming scheme, the method has the advantages that the requirement of pixels on process quality can be obviously reduced on the premise that an additional photomask is not required to be added, the production yield is improved, the dark current level is greatly reduced, and better pixel reading capacity is provided.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to an image sensor and a method for forming an image sensor.
Background
With the development of semiconductor process nodes and the performance requirements of image sensors in the market, the sensor pixel size is forced to be increasingly reduced. On the other hand, the pixel signal-to-noise ratio is not required to decrease with decreasing pixel size, and is required to gradually increase. The contradiction between these two requirements forces the photodiode size to increase more and more over the pixel volume to increase signal strength; while requiring good pinning at the various interfaces of the silicon to reduce pixel dark current. Limited by the resolution of the photoresist, doping using ion implantation makes it impossible to achieve both requirements at the same time, and therefore it is necessary to use an epitaxial method to fabricate the photodiode.
There are presently known schemes for forming discrete photodiodes using N-type substrates by means of etching, a growth method of secondary epitaxy. In this scheme, the structure of the photodiode is defined by photolithography, so that complete and uniform inter-diode isolation is formed by self-alignment in the entire depth direction of the photodiode. The photodiode prepared by the scheme can provide higher capacitance in the whole depth direction due to the simultaneous formation of the epitaxial step in the whole depth direction of the photodiode, and the full-well capacity of the prepared photoelectric sensor is remarkably improved. But the epitaxial step requires the formation of a complete silicon substrate structure due to the surface transistor arrangement. The silicon crystal can cause stress in the process of epitaxially closing the isolation trench, bring about certain lattice defects and rapidly expand at high epitaxial temperature, and secondary epitaxy also has the risk of introducing silicon defects, thereby seriously affecting the dark current level of the photodiode. In addition, as the pixel size decreases, the volume ratio of the photodiode increases, but the area of the P-type heavily doped isolation region decreases rapidly, which may deteriorate the dark current that is serious, and simultaneously cause the depletion voltage of the photodiode to increase continuously, which affects the complete readout of the photoelectronic signal.
Disclosure of Invention
An object of the present invention is to provide a method of forming an image sensor, specifically, the method includes:
etching the semiconductor substrate according to a preset hard mask layer before the grid electrode is formed to form semiconductor island structures arranged in an array, wherein at least the upper parts of the semiconductor island structures are connected with at least one other semiconductor island structure through a connecting structure, and first grooves communicated with each other are formed between the semiconductor island structures;
and forming a gate dielectric layer in the first groove, filling polysilicon, and forming a polysilicon gate as a pinning layer of the side wall of the semiconductor island-shaped structure.
Further, when the etched semiconductor substrate forms semiconductor island structures arranged in an array, each four semiconductor island structures form a group of subarrays in a 2×2 array, in each group of subarrays, the semiconductor island structures are connected with each other through the connection structures in the centers of the subarrays, the adjacent semiconductor island structures are connected with each other through the connection structures at the edges of the subarrays, and each subarray is connected with other subarrays through the connection structures at four corners.
Further, when the semiconductor island-shaped structures are formed by etching, a second groove is reserved in the center of the connecting structure in the center of each subarray, and a gate dielectric layer is formed in the second groove and filled with polysilicon.
Further, in the subsequent process of preparing other transistors of the image sensor, floating diffusion regions are arranged at the connection structures in the center of each subarray.
Further, in the subsequent process of preparing other transistors of the image sensor, a source follower is arranged on the upper part of the connecting structure at the edge of each adjacent subarray, and the source follower adopts a fin field effect transistor.
Further, in the subsequent process of preparing other transistors of the image sensor, a transfer transistor is disposed on the upper portion of each semiconductor island.
Further, when the etched semiconductor substrate forms a semiconductor island-shaped structure arranged in an array, a contact groove is formed at the outermost periphery of the array formed by the semiconductor island-shaped structure, and the contact groove is communicated with the first groove;
and after the polysilicon gate is formed, forming metal contact in the center of the contact groove, and connecting an external potential to the polysilicon gate.
Further, a voltage is connected to the polysilicon in the second groove.
Further, after the forming of the semiconductor island-shaped structures arranged in an array, before filling the polysilicon in the first trench, the method further comprises the steps of:
forming a first epitaxial layer in the first groove through an epitaxial process, so that the first groove is closed;
forming a first dielectric layer on the surfaces of the first epitaxial layer and the hard mask layer;
and forming a side wall around the hard mask layer through a side wall process, etching the first epitaxial layer in a self-aligned mode, and opening the first groove.
Further, the first epitaxial layer is an intrinsic semiconductor layer;
after the opening of the first trench, further comprising:
and forming a second epitaxial layer on the surface of the first dielectric layer through an epitaxial process, wherein the doping type of the second epitaxial layer is opposite to that of the semiconductor substrate.
Further, the first epitaxial layer at least comprises a sub-epitaxial layer with the doping type opposite to that of the semiconductor substrate;
the forming a first epitaxial layer in the first trench through an epitaxial process includes:
forming a first sub-epitaxial layer on the surface of the first groove by an epitaxial process;
and epitaxially growing a semiconductor material with the opposite doping type to the semiconductor substrate on the surface of the first sub-epitaxial layer to form a second sub-epitaxial layer.
Further, etching the semiconductor substrate to form the semiconductor island-shaped structure arranged in an array according to the preset hard mask layer comprises:
etching the semiconductor substrate according to a preset hard mask layer to form a third groove;
forming a protective medium layer on the surface of the third groove;
continuing to etch the third groove to form the semiconductor island-shaped structures and the connection structures, and forming a fourth groove between the semiconductor island-shaped structures;
and etching and widening the fourth grooves towards two sides by isotropic etching to form the first grooves which are mutually communicated, and enabling the connecting structure to form a cantilever structure.
Further, after forming the first trench, the method further includes:
and removing the protective dielectric layer.
Further, when the polysilicon gate is formed, the filling rate is controlled, so that the opening of the first groove is rapidly closed, and a hollow gap is formed in the polysilicon gate.
The invention also provides an image sensor formed by the image sensor forming method.
Compared with the existing image sensor forming scheme, the method has the advantages that the requirement of pixels on process quality can be obviously reduced on the premise that an additional photomask is not required to be added, the production yield is improved, the dark current level is greatly reduced, and better pixel reading capacity is provided. Because the closed position is etched and opened again after the first step of epitaxial growth, the control of the epitaxial speed can be relaxed in the growth process, and the productivity is obviously improved; in the second step of epitaxial process, the scheme can select to keep the trench instead of pursuing to close the trench, and grow a dielectric layer (such as a gate oxide layer) and polysilicon therein, so that interface defects caused by stress and lattice mismatch when the semiconductor substrate is epitaxially closed are avoided. And then, negative pressure is applied to the polysilicon filled in the groove, so that the interface pinning effect is improved by means of an electric field, the doping concentration requirement on the P-type epitaxial layer is further reduced, the thickness of the P-type epitaxial layer is reduced, and the full-well capacitance of the photodiode is improved.
Drawings
Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments which follows, which is read in connection with the accompanying drawings.
FIGS. 1-5 are schematic cross-sectional views of FIGS. 11B-B' during an image sensor forming method according to an embodiment of the invention;
FIGS. 6-10 are schematic cross-sectional views of FIGS. 11A-A' during an image sensor forming method according to an embodiment of the present invention;
FIG. 11 is a top view of a structure during an image sensor forming method in accordance with one embodiment of the present invention;
fig. 12 is a top view of a structure of an image sensor forming method according to another embodiment of the present invention.
In the drawings, the same or similar reference numerals denote the same or similar devices (modules) or steps throughout the different drawings.
Detailed Description
An object of the present invention is to provide an image sensor forming method, specifically, the method includes the steps of:
before the gate is formed, etching the semiconductor substrate 100 according to a preset hard mask layer 200 to form semiconductor island structures 110 arranged in an array, wherein at least the upper parts of the semiconductor island structures 110 are connected with at least one other semiconductor island structure 110 through a connection structure 111, and first trenches 120 communicated with each other are formed between the semiconductor island structures 110;
a gate dielectric layer is formed in the first trench 120 and filled with polysilicon, forming a polysilicon gate 125 as a pinning layer for the sidewalls of the semiconductor island 110.
A gate dielectric layer (not shown) may be formed within the first trench 120 prior to filling the polysilicon to avoid shorting the polysilicon gate to the substrate or epitaxial layer of semiconductor material. The gate dielectric layer may be an oxide or other High-K dielectric material.
Specifically, in an alternative embodiment, according to the preset hard mask layer 200, etching the semiconductor substrate 100 to form the semiconductor island structures 110 arranged in an array may be achieved by:
step S110: etching the semiconductor substrate 100 to form a third trench 140 according to the preset hard mask layer 200, as shown in fig. 1, which is a cross-sectional view in the direction of fig. 11B-B';
step S120: forming a protective dielectric layer 141 on the surface of the third trench 140, as shown in fig. 2, which is a sectional view in the direction of fig. 11B-B';
step S130: continuing to etch the third trench 140 to form the semiconductor island structure 110 and the connection structure 111, and forming a fourth trench 150 between the semiconductor island structures 110, as shown in fig. 3, which is a cross-sectional view of fig. 11B-B';
step S140: and etching and widening the fourth grooves 150 to two sides by isotropic etching to form the first grooves 120 which are mutually communicated, and forming the connecting structure 111 into a cantilever structure. Because the protective dielectric layer 141 is present at a portion of the trench that is farther than the top, the bottom of the connection structure is completely etched into a cantilever structure after a certain distance of lateral etching, as shown in fig. 4, which is a sectional view in the direction of fig. 11B-B'.
Optionally, after step S140, the method further includes:
step S150: the protective dielectric layer 141 is removed.
On the basis of the foregoing alternative embodiment, the top protective dielectric layer 141 is removed for subsequent epitaxial growth processes.
Further, after the forming of the semiconductor island structures 110 arranged in an array, before filling the polysilicon in the first trenches 120, the method further includes the steps of:
step S210: forming a first epitaxial layer 121 in the first trench 120 through an epitaxial process, so that the first trench 120 is closed, as shown in fig. 5, which is a cross-sectional view in the direction of fig. 11 A-A';
step S220: forming a first dielectric layer 122 on the first epitaxial layer 121 and the hard mask layer 200, as shown in fig. 6, which is a cross-sectional view in the direction of fig. 11 A-A';
step S230: a sidewall is formed around the hard mask layer 200 by a sidewall process, the first epitaxial layer 121 is etched in a self-aligned manner, and the first trench 120 is opened, as shown in fig. 7, which is a cross-sectional view in the direction of fig. 11 A-A'.
In an alternative embodiment, the first epitaxial layer 121 is formed by using an intrinsic semiconductor epitaxy;
specifically, the intrinsic semiconductor layer with a certain thickness can be epitaxially grown by introducing a reaction source material gas into the etched trench to serve as a buffer layer (P-I-N junction) in the lateral PN junction of the photodiode. This step aims at closing the trench, so that no deliberate control of the growth rate is required, and the productivity of the whole process flow can be improved.
After the opening of the first trench 120, further comprising:
a second epitaxial layer is formed on the surface of the first dielectric layer 122 through an epitaxial process, where the doping type of the second epitaxial layer is opposite to that of the semiconductor substrate 100.
Further, the first epitaxial layer 121 includes at least a sub-epitaxial layer having a doping type opposite to that of the semiconductor substrate 100;
the forming the first epitaxial layer 121 in the first trench 120 through the epitaxial process includes:
forming a first sub-epitaxial layer 123 on the surface of the first trench 120 by an epitaxial process;
a second sub-epitaxial layer 124 is formed by epitaxially growing a semiconductor material of opposite doping type to the semiconductor substrate 100 on the surface of the first sub-epitaxial layer 123, as shown in fig. 8, which is a cross-sectional view in the direction of fig. 11 A-A'.
Further, before forming the polysilicon gate 125, a gate dielectric layer may be formed on the surface of the second sub-epi layer 124 to avoid shorting the polysilicon gate 125 with the epi layer, and when forming the polysilicon gate 125, the filling rate is controlled to quickly close the opening of the first trench 120, and a hollow gap 126 is formed in the polysilicon gate 125, as shown in fig. 9, which is a sectional view in the direction of fig. 11 A-A'.
Further, when the semiconductor substrate 100 is etched to form the semiconductor island structures 110 arranged in an array, each four semiconductor island structures 110 are formed into a group of sub-arrays in a 2×2 array, in each group of sub-arrays, the semiconductor island structures 110 are connected to each other through the connection structures 111 at the centers of the sub-arrays, the adjacent semiconductor island structures 110 are connected to each other through the connection structures 111 at the edges of the sub-arrays, and each sub-array is connected to other sub-arrays through the connection structures 111 at the four corners.
In such alternative embodiments, the fully symmetrical pixel trench design common in the prior art may be modified to an asymmetrical design. As shown in fig. 11, in this embodiment, a symmetrical periodic outer boundary is provided around the pixel cell area, and a longer first trench 1201 is provided; and a shorter first trench 1202 is provided at a position between the inner pixel units of the pixel design symmetry period. And the elongated connection structures 111 remain between all of the first trenches 120 to ensure lattice fixation of the etched silicon pillars in subsequent process steps. The connection 111 between the first trench 1201 with the longer outer period boundary and the first trench 1202 with the shorter inner period boundary will be parallel to the period boundary, so that the transistor channel can be designed thereon to improve the transistor performance.
Further, when the semiconductor substrate 100 is etched to form the semiconductor island-shaped structures 110 arranged in an array, a contact trench 300 is formed at the outermost periphery of the array formed by the semiconductor island-shaped structures 110, and the contact trench 300 is mutually communicated with the first trench 120;
after the polysilicon gate 125 is formed, a metal contact is formed in the center of the contact trench 300, and an external potential is connected to the polysilicon gate 125.
Further, in forming the semiconductor island structure 110 by etching, a second trench 130 is left in the center of the connection structure 111 in the center of each sub-array, and polysilicon is filled in the second trench 130, as shown in fig. 12. Preferably, a gate dielectric layer (not shown) may be formed within the second trench 130 prior to filling the polysilicon to avoid shorting the polysilicon gate to the substrate or epitaxial layer of semiconductor material. The gate dielectric layer may be an oxide or other High-K dielectric material. At this time, the polysilicon inside the trench does not participate in the photoelectric effect and charge collection of the photodiode itself, and the closing quality inside the polysilicon does not affect the final device performance. And the dielectric layer and the polysilicon have lower hardness than monocrystalline silicon, so that the photodiode has certain stress release capability, and dark current of the photodiode can be effectively reduced.
Preferably, a voltage may be applied to the polysilicon in the second trench 130.
In an alternative embodiment, the present invention completes the fabrication process of the entire image sensor by completing fabrication of all pixel structures on the planarized semiconductor substrate via conventional processes. A separate circuit is designed for the sensor circuit, and a negative bias voltage can be applied to the filled polysilicon. During the operation of the sensor, the negative voltage can help to pin the defects of the side wall of the pixel groove and reduce the depletion voltage of the photodiode, thereby reducing the dark current of the pixel and improving the readout capability of the pixel. In an alternative embodiment, the polysilicon is filled with a grid-like connection structure, as shown in the top view, so that the polysilicon can be connected at the outermost periphery of the pixel region by metal wires to provide electrical functions
Further, in the subsequent process of manufacturing other transistors of the image sensor, a Floating Diffusion (FD) is provided at the connection structure 111 at the center of each of the subarrays.
Further, in the subsequent process of manufacturing other transistors of the image sensor, a Source Follower (SF) is disposed on the upper portion of the connection structure 111 at the edge of each of the adjacent subarrays, and the Source Follower (SF) is a fin field effect transistor (FinFET).
Further, in the subsequent process of manufacturing other transistors of the image sensor, a transfer Transistor (TX) is disposed on the upper portion of each of the semiconductor islands 110.
The invention also provides an image sensor formed by the image sensor forming method.
Compared with the existing image sensor forming scheme, the method has the advantages that the requirement of pixels on process quality can be obviously reduced on the premise that an additional photomask is not required to be added, the production yield is improved, the dark current level is greatly reduced, and better pixel reading capacity is provided. Because the closed position is etched and opened again after the first step of epitaxial growth, the control of the epitaxial speed can be relaxed in the growth process, and the productivity is obviously improved; in the second step of epitaxial process, the scheme can select to keep the trench instead of pursuing to close the trench, and grow a dielectric layer (such as a gate oxide layer) and polysilicon therein, so that interface defects caused by stress and lattice mismatch when the semiconductor substrate is epitaxially closed are avoided. And then, negative pressure is applied to the polysilicon filled in the groove, so that the interface pinning effect is improved by means of an electric field, the doping concentration requirement on the P-type epitaxial layer is further reduced, the thickness of the P-type epitaxial layer is reduced, and the full-well capacitance of the photodiode is improved.
In order to obtain better effect, the shape of the epitaxial layer can be controlled by synchronous control of deposition and etching without special precision when the first epitaxial layer is grown, so that the proportion of etching atmosphere is greatly reduced in the step, the cycle times of deposition and etching are reduced, and the quality of the epitaxial layer interface can be improved. In addition, in order to manufacture a side wall with enough thickness in the groove, the hard mask used in the first etching can be properly thickened so as to ensure that the thickness of the side wall is enough to block the requirement of the subsequent second etching. In the scheme, the P-type heavily doped layer with thinner layer thickness and lower doping concentration is selected, so that the increase of the full-well capacitance is facilitated.
In this scheme, since the size of the whole pixel array is relatively large, the overall capacitance of polysilicon in the trench is also large, and thus the application process of the negative bias voltage is very long. In alternative embodiments, the doping concentration of the polysilicon may be increased to some extent or the cross-sectional area may be increased to thereby increase the loading rate of the negative pressure.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Thus, the embodiments should be considered in all respects as illustrative and not restrictive. Furthermore, it is evident that the word "comprising" does not exclude other elements or steps, and that the word "a" or "an" does not exclude a plurality. The elements recited in the apparatus claims may also be embodied by one element. The terms first, second, etc. are used to denote a name, but not any particular order.
Claims (15)
1. An image sensor forming method, comprising: etching the semiconductor substrate according to a preset hard mask layer before the grid electrode is formed to form semiconductor island structures arranged in an array, wherein at least the upper parts of the semiconductor island structures are connected with at least one other semiconductor island structure through a connecting structure, and first grooves communicated with each other are formed between the semiconductor island structures;
and forming a gate dielectric layer in the first groove, filling polysilicon, and forming a polysilicon gate as a pinning layer of the side wall of the semiconductor island-shaped structure.
2. The method of forming an image sensor according to claim 1, wherein when the etched semiconductor substrate forms semiconductor island structures arranged in an array, each four of the semiconductor island structures are formed in a 2 x 2 array to form a group of subarrays, and in each group of the subarrays, each of the semiconductor island structures is connected to each other by the connection structure at the center of the subarray, adjacent ones of the semiconductor island structures are connected to each other by the connection structures at the edges of the subarray, and each of the subarrays is connected to each other by the connection structures at four corners.
3. The method of forming an image sensor of claim 2, wherein a second trench is left in the center of the connection structure at the center of each sub-array, and a gate dielectric layer is formed in the second trench and filled with polysilicon when the semiconductor island structure is etched.
4. The method of forming an image sensor of claim 2, wherein a floating diffusion region is provided at the connection structure at the center of each sub-array during subsequent fabrication of other transistors of the image sensor.
5. The method of forming an image sensor of claim 2, wherein a source follower is disposed on top of the connection structure at the edge of each adjacent subarray during subsequent fabrication of other transistors of the image sensor, and the source follower is a fin field effect transistor.
6. The method of forming an image sensor of claim 2, wherein a transfer transistor is provided on an upper portion of each of the semiconductor islands during subsequent fabrication of other transistors of the image sensor.
7. The method of forming an image sensor according to claim 2, wherein when the etched semiconductor substrate forms an array-arranged semiconductor island structure, a contact trench is formed at an outermost periphery of the array formed by the semiconductor island structure, the contact trench being in communication with the first trench;
and after the polysilicon gate is formed, forming metal contact in the center of the contact groove, and connecting an external potential to the polysilicon gate.
8. The method of claim 3, wherein a voltage is applied to the polysilicon in the second trench.
9. The image sensor forming method according to claim 1, further comprising, after the forming of the semiconductor island structure of the array arrangement, before filling the polysilicon in the first trench, the steps of:
forming a first epitaxial layer in the first groove through an epitaxial process, so that the first groove is closed;
forming a first dielectric layer on the surfaces of the first epitaxial layer and the hard mask layer;
and forming a side wall around the hard mask layer through a side wall process, etching the first epitaxial layer in a self-aligned mode, and opening the first groove.
10. The image sensor forming method according to claim 9, wherein the first epitaxial layer is an intrinsic semiconductor layer;
after the opening of the first trench, further comprising:
and forming a second epitaxial layer on the surface of the first dielectric layer through an epitaxial process, wherein the doping type of the second epitaxial layer is opposite to that of the semiconductor substrate.
11. The image sensor forming method according to claim 1, wherein the first epitaxial layer includes at least a sub-epitaxial layer having a doping type opposite to that of the semiconductor substrate;
the forming a first epitaxial layer in the first trench through an epitaxial process includes:
forming a first sub-epitaxial layer on the surface of the first groove by an epitaxial process;
and epitaxially growing a semiconductor material with the opposite doping type to the semiconductor substrate on the surface of the first sub-epitaxial layer to form a second sub-epitaxial layer.
12. The method of forming an image sensor as claimed in claim 1, wherein etching the semiconductor substrate to form an array-arranged semiconductor island structure according to a predetermined hard mask layer comprises:
etching the semiconductor substrate according to a preset hard mask layer to form a third groove;
forming a protective medium layer on the surface of the third groove;
continuing to etch the third groove to form the semiconductor island-shaped structures and the connection structures, and forming a fourth groove between the semiconductor island-shaped structures;
and etching and widening the fourth grooves towards two sides by isotropic etching to form the first grooves which are mutually communicated, and enabling the connecting structure to form a cantilever structure.
13. The image sensor forming method of claim 12, further comprising, after forming the first trench:
and removing the protective dielectric layer.
14. The method of forming an image sensor of claim 1, wherein a filling rate is controlled to rapidly close an opening of the first trench and to form a hollow gap in the polysilicon gate when forming the polysilicon gate.
15. An image sensor formed by the image sensor forming method according to claim 1 to 14.
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