WO2022042030A1 - Image sensor structure - Google Patents

Abstract

An image sensor structure, comprising, from bottom to top, a substrate (1) and a dielectric layer (11). A first photosensitive device is arranged in the substrate (1), a metal interconnection layer (6) and a second photosensitive device are arranged in the dielectric layer (11), the second photosensitive device is arranged in a groove, the groove is located in the dielectric layer (11) above the first photosensitive device, and the second photosensitive device is coupled with the first photosensitive device by means of the groove and led out by means of the metal interconnection layer (6), wherein the second photosensitive device comprises a plurality of second pn junctions which are horizontally distributed and coupled with one another. The image sensor structure can effectively improve the efficiency of light absorption, and sensor performance, such as full well capacity, and can greatly improve the absorption efficiency of near-infrared light.

Description

An image sensor structure

cross reference

This application claims the priority of Chinese patent applications with application numbers 202010856292.4 and 202010856280.1 filed on August 24, 2020. The contents of the aforementioned applications are incorporated herein by reference.

technical field

The invention relates to the technical field of semiconductor integrated circuits and sensors, in particular to a high-performance CMOS image sensor structure with high absorption efficiency.

technical background

The photosensitive device of a conventional CMOS image sensor is usually a pn junction. Photosensitive pn junctions manufactured by conventional processes generally only have a strong absorption rate and quantum efficiency for visible light, and some light will pass through the photosensitive area and cause losses.

In addition, for near-infrared light, a depletion region with a thickness of several micrometers to ten micrometers or even thicker is required for effective absorption. However, it is difficult to realize this structure by the injection process of the existing CMOS process, or due to the increase of the depletion region. thick and lead to a problem of high depletion voltage.

Summary of Invention

The purpose of the present invention is to overcome the above-mentioned defects in the prior art and provide an image sensor structure.

For achieving the above object, technical scheme of the present invention is as follows:

An image sensor structure, from bottom to top, includes: a substrate and a medium layer; a first photosensitive device is arranged in the substrate, a metal interconnection layer and a second photosensitive device are arranged in the medium layer, and the The second photosensitive device is arranged in a trench, the trench is located in the dielectric layer above the first photosensitive device, and the second photosensitive device is coupled to the first photosensitive device through the trench The photosensitive device is led out through the metal interconnection layer; wherein, the second photosensitive device includes a plurality of second pn junctions distributed along the horizontal and coupled to each other.

Further, the first photosensitive device includes a plurality of first pn junctions distributed along the horizontal and coupled to each other.

Further, the first photosensitive device is alternately provided with a plurality of first N-type photosensitive regions and first P-type regions to form a plurality of first pn junctions, and each of the first N-type photosensitive regions is connected from its lower end, Surrounding the lower end of the first P-type region, each of the first P-type regions is connected from its upper end, and covers the surface of the first pn junction; inside the substrate on one side of the first pn junction A third P-type region is provided, the first P-type region in the first pn junction is a P-type doped region, and the first P-type region covering the surface of the first pn junction is P ⁺ type doped region, the first N-type photosensitive region is an N-type doped region; or, the first photosensitive device is provided with a first N-type photosensitive region, and the first N-type photosensitive region above The substrate is provided with a first P-type region;

The second photosensitive device is alternately provided with a plurality of second N-type photosensitive regions and second P-type regions to form a plurality of the second pn junctions, and each of the second N-type photosensitive regions is connected from its upper end, and Covering the surface of the second pn junction, each of the second P-type regions is connected from its lower end, and covers the bottom surface of the trench; wherein,

An isolation layer is arranged between the first photosensitive device and the second photosensitive device, and the second P-type region is connected to the first P-type region through the isolation layer; the first N-type region A third P-type region is arranged in the substrate on one side of the photosensitive region, and the first P-type region is a P ⁺ -type doped region.

Further, a shallow trench isolation is provided in the third P-type region for isolating the first N-type photosensitive region used for light-sensing from other external regions, and the second P-type region passes through the The isolation layer is connected to the third P-type region, and the third P-type region extends along the bottom and sidewalls of the shallow trench isolation to be connected to the first P-type region.

Further, a silicide region is provided on the third P-type region, and the third P-type region is connected to the metal interconnection layer through the silicide region.

Further, the second P-type region is connected to the third P-type region and the silicide region through an open region provided by the isolation layer.

Further, the surfaces of the second N-type photosensitive region and the dielectric layer are covered with a fourth P-type region, a fifth P-type region is provided on one side of the fourth P-type region, and the fifth P-type region is The lower end of the type region protrudes from the fourth P-type region and is connected to the metal interconnection layer in the dielectric layer.

Further, the fourth P-type region is covered with a dielectric protection layer.

Further, the substrate is a P ^- type doped substrate, the third P-type region and the fifth P-type region are P ⁺ -type doped regions, and the fourth P-type region is P ^- type a doped region, the second P-type region located in the second pn junction is a P-type doped region, the second P-type region located on the bottom surface of the trench is a P ⁺ -type doped region, The second N-type photosensitive region is an N-type doped region.

Further, the second P-type region also extends from the bottom of the trench to the sidewall of the trench, and extends from one sidewall of the trench to the surface of the dielectric layer. The fourth P-type region and the fifth P-type region are connected.

Further, the second N-type photosensitive region is connected to the first N-type photosensitive region through the second P-type region, the isolation layer and the first P-type region in sequence.

Further, a first transfer transistor is provided in the substrate, and the first photosensitive device is coupled to the first transfer transistor.

Further, the second N-type photosensitive region is separated from the first P-type region and the first N-type photosensitive region by the isolation layer.

Further, a first transfer transistor is provided in the substrate, the first photosensitive device is coupled to the first transfer transistor, a second transfer transistor is provided on the fourth P-type region, and the second light A sensitive device is coupled to the second pass transistor.

Further, the second transfer transistor is disposed on the other side of the fourth P-type region, and the second transfer transistor has a gate electrode formed on the dielectric protection layer outside the trench, and is located on the outer side of the trench. A drain is formed in the fourth P-type region, the second N-type photosensitive region extends outward from the upper end of the trench, and forms a partial overlap under the gate electrode to form the second transfer transistor The source of the second pass transistor, the fourth P-type region between the source and the drain forms the channel of the second pass transistor.

Further, the second pn junction completely fills the trench.

Further, the second pn junction partially fills the trench, and a recessed structure is formed on the surface of the second N-type photosensitive region located in the trench.

Further, the upper end of the fifth P-type region is drawn out from the surface of the dielectric protection layer through an electrode.

It can be seen from the above technical solutions that in the present invention, an additional light source including a plurality of second pn junctions is formed in the dielectric layer by trench filling above the photosensitive area (the first photosensitive device area) of the conventional image sensor structure. The absorption layer (the second photosensitive device) is coupled with the light absorption layer of the existing photosensitive device (the first photosensitive device), thereby effectively improving the efficiency of light absorption, and improving the sensor performance such as full well capacity, and can Greatly improve the absorption efficiency of near-infrared light. In addition, the light absorption layer can be formed by using a low-temperature amorphous silicon material, which will not affect the thermal budget of the existing device and effectively control the cost.

Description of drawings

FIG. 1 is a schematic structural diagram of an image sensor according to a preferred embodiment 1 of the present invention;

2 is a schematic structural diagram of an image sensor according to a second preferred embodiment of the present invention;

3 is a schematic structural diagram of an image sensor according to a preferred embodiment 3 of the present invention;

4 is a schematic structural diagram of an image sensor according to a fourth preferred embodiment of the present invention;

5 is a schematic structural diagram of an image sensor according to a fifth preferred embodiment of the present invention;

6 is a schematic structural diagram of an image sensor according to a sixth preferred embodiment of the present invention;

7 is a schematic structural diagram of an image sensor according to a seventh preferred embodiment of the present invention;

FIG. 8 is a schematic structural diagram of an image sensor according to an eighth preferred embodiment of the present invention.

SUMMARY OF THE INVENTION

The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

It should be noted that, in the following specific embodiments, when describing the embodiments of the present invention in detail, in order to clearly represent the structure of the present invention and facilitate the description, the structures in the accompanying drawings are not drawn according to the general scale, and the Partial enlargement, deformation and simplification of processing are shown, therefore, it should be avoided to interpret this as a limitation of the present invention.

In the following specific embodiments of the present invention, please refer to FIG. 1 and FIG. 2 , FIG. 1 is a schematic structural diagram of an image sensor according to a first preferred embodiment of the present invention, and FIG. 2 is a first preferred embodiment of the present invention. A schematic diagram of the structure of an image sensor. As shown in FIG. 1 and FIG. 2 , an image sensor structure of the present invention may adopt, for example, a backside illuminated (BSI) structure, including from bottom to top: a substrate 1 and a dielectric layer 11 , and incident light from the back of the substrate 1 The image sensor is irradiated in the direction (the lower surface of the substrate 1 is shown in the figure).

Please refer to Figure 1 and Figure 2. The substrate 1 can be, for example, a silicon substrate 1, but is not limited thereto. The substrate 1 can be a P ^- type doped substrate (P-(sub), a P ^- type lightly doped substrate, that is, a substrate lightly doped with a pentavalent impurity element) 1, and the front side of the substrate 1 is provided with a first light sensitive device. The dielectric layer 11 may be an interlayer dielectric layer 11, and the dielectric layer 11 is provided with a metal interconnection layer 6 and a second photosensitive device.

The dielectric layer 11 is provided with a trench, the trench is located in the dielectric layer 11 above the first photosensitive device, and the second photosensitive device is located in the trench. In addition, the second photosensitive device is coupled to the first photosensitive device through the trench, and at the same time, the second photosensitive device and the first photosensitive device are led out through the metal interconnection layer 6 .

Please refer to Figure 1. In the first embodiment, the first photosensitive device may be provided with a first N-type photosensitive region (PD) 18; the substrate 1 above the first N-type photosensitive region 18 may be provided with a first P-type region 17, A P-type region 17 may be a thin-layered P ⁺ -type doped region (P-type heavily doped region, ie, a heavily doped region with a pentavalent impurity element).

Referring to FIG. 2, in the second embodiment, the first photosensitive device and the second photosensitive device respectively include a plurality of pn junctions distributed and coupled along the horizontal, wherein the first photosensitive device includes a plurality of The horizontally distributed and coupled first pn junctions also include a plurality of horizontally distributed and coupled second pn junctions in the second photosensitive device. For example, the first photosensitive device may be alternately provided with a plurality of first N-type photosensitive regions 18 and first P-type regions 17 to form a plurality of first pn junctions, that is, the first P-type regions 17 serve as the p-type of the first pn junction. region, the first N-type photosensitive region 18 serves as the n region of the first pn junction. Wherein, each of the first N-type photosensitive regions 18 is connected from its lower end to surround the lower end of the first P-type region 17, and at the same time, each of the first P-type regions 17 is connected from its upper end, located on the surface of the substrate 1, and A plurality of comb-shaped first pn junction structures are formed by covering the surface of each first pn junction. The first P-type region 17 located in the first pn junction is a P-type doped region, and the first P-type region 17 located on the surface of the substrate 1 can be a thin-layered P ⁺ -type doped region. The first N-type photosensitive region 18 is an N-type doped region (ie, a doped region in a trivalent impurity element).

As shown in FIG. 1 and FIG. 2 , the second photosensitive device includes a plurality of second pn junctions distributed and coupled along the horizontal direction. For example, the second photosensitive device can be alternately provided with a plurality of second N-type photosensitive regions 9 and second P-type regions 15 to form a plurality of second pn junctions, that is, the second P-type regions 15 serve as the p-type of the second pn junction region, the second N-type photosensitive region 9 serves as the n region of the second pn junction. Wherein, each second N-type photosensitive region 9 is connected from its upper end and covers the upper surface of each second pn junction, and at the same time, each second P-type region 15 is connected from its lower end and is located on the lower surface of each second pn junction, and cover the bottom surface of the trench, thereby forming a plurality of comb-shaped second pn junction structures.

The second P-type region located at the second pn junction is a P-type doped region (ie, a doped region in a pentavalent impurity element), and the second N-type photosensitive region is an N-type doped region.

The second P-type region 15 on the bottom surface of the trench can be a thin-layered P ⁺ -type doped region, and can extend from the bottom of the trench to the sidewall of the trench to enclose the second pn junction in the trench.

The materials of the second N-type photosensitive region 9 and the second P-type region 15 may be amorphous silicon (amorphous-Si) or the like.

An isolation layer 16 is provided between the first photosensitive device and the second photosensitive device, that is, the isolation layer 16 is provided on the front surface of the substrate 1 . The isolation layer 16 can be made of conventional dielectric materials, such as silicon dioxide.

Please refer to Figure 1. In the first embodiment, the isolation layer 16 may be provided with two open regions 5 and 14 . Wherein, a second N-type photosensitive region 9 of a second pn junction can pass through the second P-type region 15 and an open region 14 on the isolation layer 16 in turn (as shown on the right side of the figure), and enter the substrate 1 downward. inside, and continue to connect to the first N-type photosensitive region 18 through the first P-type region 17 . In addition, under the open region 14, the first P-type region 17 should have an opening corresponding to the open region 14, so that the second N-type photosensitive region 9 passes through the first P-type region 17 and is connected to the first P-type region 17. Model area 17 is isolated.

The second N-type photosensitive regions 9 in the plurality of second pn junctions can also be introduced into the substrate 1 through different open regions in the above-mentioned manner and connected to the first N-type photosensitive regions 18 .

A third P-type region 2 is provided in the substrate 1 of the first N-type photosensitive region 18 (the left side of the figure), and a shallow trench isolation (STI) 3 is provided in the third P-type region 2 . Shallow trench isolation (STI) 3 is used to isolate the first N-type photosensitive region 18 for light-sensing from other regions. The third P-type region 2 may be a P ⁺ -type doped region. The lower end of the third P-type region 2 extends upward along the bottom and sidewalls of the shallow trench isolation 3 to connect with one end of the first P-type region 17 . The second P-type region 15 covering the trench bottom can pass through the trench bottom and an open region 5 of the isolation layer 16 in sequence (as shown on the left side of the figure), down into the substrate 1, and connect the second P-type region 15. The upper end of the triple P-type region 2.

The second P-type regions 15 in the plurality of second pn junctions can also be introduced into the substrate 1 through different open regions in the above-mentioned manner, and are connected to the third P-type regions 2 .

Further, a metal silicide region 4 may be provided on the third P-type region 2 , and the third P-type region 2 is connected to the lowermost metal of the metal interconnection layer 6 in the dielectric layer 11 through the metal silicide region 4 .

In addition, the second P-type region 15 can be connected to the third P-type region 2 through the open region 5 provided by the isolation layer 16 (the open region 5 is, for example, between the silicide region 4 and a shallow trench isolation 3 on the left side) and the silicide region 4 to realize the lead-out of the photosensitive device.

Please refer to Figure 1. As an optional embodiment, the second pn junction can completely fill the trench. At this time, the second N-type photosensitive regions 9 in each of the second pn junctions are connected from their upper ends, and extend out of the trenches from the upper ends of the trenches, and at least partially cover the surface of the dielectric layer 11 .

A fourth P-type region 10 may be further covered on the surface of the connected second N-type photosensitive region 9, and the fourth P-type region 10 may be a P ^- type doped region. The material of the fourth P-type region 10 can also be amorphous silicon or the like.

In the fourth P-type region 10, a fifth P-type region 7 may also be provided, and the fifth P-type region 7 may be a P ⁺ -type doped region. As shown in FIG. 1 , the lower end of the fifth P-type region 7 protrudes from the fourth P-type region 10 on the left, and is connected to the uppermost metal layer of the metal interconnection layer 6 in the dielectric layer 11 . In addition, the thin layer portion of the second P-type region 15 located on the bottom surface of the trench can also protrude from above the left sidewall of the trench and further extend to the surface of the dielectric layer 11 , that is, the extension of the second P-type region 15 The portion is interposed between the fifth P-type region 7 and the dielectric layer 11 , thereby forming a connection with the fourth P-type region 10 and the fifth P-type region 7 at the same time.

Please refer to FIG. 2 , the lateral first pn junction structure of the first photosensitive device disposed in the substrate 1 can be fabricated as follows: firstly, an integral N-type region is formed in the substrate 1 by implantation, which is used to form The first N-type photosensitive region 18 in the first pn junction; then, through implantation, a plurality of P-type regions are implanted in the vertical direction in the above-mentioned N-type region to form the first P-type region 17 of the first pn junction, And the bottom of the P-type region is higher than the bottom of the N-type region, thereby forming a first pn junction; then, a P ⁺ region on the substrate surface, that is, the first P-type region 17 on the substrate surface is formed by implantation.

Optionally, an N-type region can also be formed by implantation in the substrate 1 first; and then by etching, multiple slots in the vertical direction are formed in the above-mentioned N-type region, so that the bottom of the slot is located at the bottom of the N-type region. Above the bottom, a P-type region is formed in the socket by epitaxy and smoothed by chemical mechanical polishing; then, the P ⁺ region of the substrate surface is formed by implantation.

Alternatively, an N-type region can be formed by implantation in the substrate 1 first; and then by implantation, a plurality of P-type regions in the vertical direction are formed in the above-mentioned N-type region, and the bottom of the P-type region is higher than the N-type region. , forming the first layer of the first pn junction layer; then, epitaxial N-type region, and in the epitaxial N-type region by implantation to form a plurality of P-type regions in the vertical direction, and connected with the P-type region of the previous layer, forming The second layer is the first pn junction layer. And so on until the desired thickness. Finally, a P ⁺ region is formed on the surface of the substrate 1 by implantation.

Please refer to FIG. 1 and FIG. 2 in conjunction with the lateral second pn junction structure of the second photosensitive device, which can increase the junction depth of the depletion region and reduce the depletion voltage. It can be achieved by in-situ doping during film formation. This can be achieved by an ion implantation process. Among them, the activation of impurities after ion implantation can be realized in whole or in part by laser annealing.

In one embodiment, the method for manufacturing the second pn structure includes: firstly depositing p ⁺ amorphous silicon (ie, amorphous silicon heavily doped with pentavalent impurity elements) in the trench as the second P-type region 15 is located on the bottom surface of the trench; then N-type amorphous silicon is deposited; then, a p-type region in a vertical direction is formed by implantation, that is, a second p-type region 15 (p region) located in the second pn junction, and is connected with The P ⁺ region at the bottom of the trench is connected; then N-type amorphous silicon is deposited, so that the N-type amorphous silicon is connected as a whole from its upper end. Finally, lightly doped P-type amorphous silicon (ie, amorphous silicon lightly doped with pentavalent impurity elements) is deposited to form a P ^- type doped region, that is, the fourth P-type region 10 .

Optionally, p ⁺ amorphous silicon can also be deposited in the trench first, and then N-type amorphous silicon can be deposited; then, a through-trough is formed in the N-type amorphous silicon by etching; then, a through-trough is deposited p-type amorphous silicon is connected to the bottom P ⁺ amorphous silicon; then the excess p-type amorphous silicon on the surface of N-type amorphous silicon is etched away, and then N-type silicon crystalline silicon and lightly doped p-type amorphous silicon are deposited. crystalline silicon.

Optionally, p ⁺ amorphous silicon can be deposited in the trench first, and then a thinner N-type amorphous silicon layer can be deposited; The p ⁺ amorphous silicon is connected to form the first layer and the second pn junction layer; then, a thinner N-type amorphous silicon layer is deposited, and a p-type region in a vertical direction is formed by implantation, which is connected to the first layer below. The P-type regions in the second pn junction layer are connected to form a second second pn junction layer. And so on until the trenches are filled. Re-deposit N-type silicon crystalline silicon and lightly doped P-type amorphous silicon.

Further, a dielectric protection layer 8 may also be covered on the fourth P-type region 10 . The dielectric protective layer 8 can be made of conventional dielectric materials, such as silicon dioxide.

The upper end of the fifth P-type region 7 can be drawn out from the surface of the dielectric protection layer 8 through the electrode 21 .

Please refer to Figure 1 and Figure 2. In the substrate 1 on the right side of the illustration of the first N-type photosensitive region 18, a first transfer transistor (TX) and an N-type floating diffusion region (FD) 12 may also be provided. The gate (Gate) 13 of the first transfer transistor can also be made of amorphous silicon, and the floating diffusion region 12 can be an N ⁺ type doped region (N-type heavily doped region, that is, a heavily doped region with trivalent impurity elements). ). The first photosensitive device can be coupled to the source of the first pass transistor in a conventional manner.

In the above state, a fully connected structure is formed between the first photosensitive device located in the substrate 1 and the second photosensitive device located in the dielectric layer 11, so that the signals of the first photosensitive device and the second photosensitive device can be Output by sharing the first pass transistor and the N-type floating diffusion region 12 .

Shallow trench isolation (STI) may be provided on one side of the floating diffusion region 12 , as shown on the right side of FIG. 1 .

Please refer to Figure 3 and Figure 4. In another third embodiment and another fourth embodiment of the present invention, only one open area 5 is provided in the isolation layer 16 . In this state, only the second P-type region 15 is connected to the third P-type region 2 and the silicide region 4 through the open region 5 provided by the isolation layer 16 . The second N-type photosensitive region 9 is separated from the first P-type region 17 and the first N-type photosensitive region 18 by the isolation layer 16 . That is, an incomplete connection is formed between the first photosensitive device located in the substrate 1 and the second photosensitive device located in the dielectric layer 11, and only the signal of the first photosensitive device passes through the first transfer transistor and the N-type suspension. Diffusion region 12 output.

At this time, the signal in the second photosensitive device will be output through a second pass transistor alone.

Specifically, the second transfer transistor may be disposed on the other side of the fourth P-type region 10 and outside the trench.

As an optional implementation manner, the second transfer transistor may use the rightward extension of the dielectric protective layer 8 as the gate dielectric 81 , and form the gate electrode 19 on the dielectric protective layer outside the trench. The gate electrode 19 can be made of amorphous silicon. Also, the second pass transistor may use the extension of the fourth P-type region 10 to the right to form a channel 101 under the gate electrode 19 and in the extension of the fourth P-type region 10 to the right of the channel 101 An N ⁺ region 20 is formed by ion implantation, and the N ⁺ region 20 is partially overlapped under the gate electrode 19 to form the drain (suspended diffusion region) 20 of the second transfer transistor. At the same time, the second N-type photosensitive region 9 extends outward from the upper end of the trench to the right, and its extension 91 partially overlaps under the gate electrode 19 to form the source electrode 91 of the second transfer transistor.

Please refer to Figure 5, Figure 6, Figure 7 and Figure 8. As a further optional implementation manner, when a fully connected state ( FIG. 1 or FIG. 2 ), or an incomplete connection state ( FIG. 3 or FIG. 4 ) is formed between the first photosensitive device and the second photosensitive device , the second pn junction can also be partially filled (eg half-filled) in the trench, so that a recess 22 structure is formed on the surface of the second N-type photosensitive region 9 connected as a whole in the trench. In this state, the fourth P-type region 10 and the dielectric protection layer 8 will conformally cover the surface of the recess 22 of the second N-type photosensitive region 9 .

The advantage of the above implementation manner is that when the second photosensitive device structure is thick, a relatively large high voltage needs to be applied to form a depletion region, and the application of a high voltage requires special processes and devices, which increases complexity and cost.

Other aspects of the image sensor structure in the above-mentioned embodiments of FIGS. 3 , 5 and 7 may be the same as the image sensor structure in the embodiment of FIG. 1 and will not be repeated; the image sensor structures in the above-mentioned embodiments of FIGS. 4 , 6 and 8 Other aspects can be the same as the structure of the image sensor in the embodiment of FIG. 2 and will not be repeated.

The above are only the preferred embodiments of the present invention, and the embodiments are not intended to limit the protection scope of the present invention. Therefore, any equivalent structural changes made by using the contents of the description and drawings of the present invention should be included in the protection of the present invention. within the range.

Claims (18)

1. An image sensor structure is characterized in that, from bottom to top, it includes: a substrate and a dielectric layer; a first photosensitive device is arranged in the substrate, and a metal interconnection layer and a second optical layer are arranged in the medium layer. A sensitive device, the second photosensitive device is arranged in a trench, the trench is located in the dielectric layer above the first photosensitive device, and the second photosensitive device is coupled to the second photosensitive device through the trench. The first photosensitive device is led out through the metal interconnection layer; wherein, the second photosensitive device includes a plurality of second pn junctions distributed along the horizontal and coupled to each other.
2. 1. The image sensor structure according to claim 1, wherein the first photosensitive device comprises a plurality of first pn junctions distributed along the horizontal direction and coupled to each other.
3. The image sensor structure according to claim 1, wherein the first photosensitive device is alternately provided with a plurality of first N-type photosensitive regions and first P-type regions to form a plurality of first pn junctions, each of which is The first N-type photosensitive region is connected from its lower end, surrounds the lower end of the first P-type region, and each of the first P-type regions is connected from its upper end and covers the surface of the first pn junction; the A third P-type region is arranged in the substrate on one side of the first pn junction, and the first P-type region located in the first pn junction is a P-type doped region covering the first pn junction. The first P-type region on the junction surface is a P ⁺ -type doped region, and the first N-type photosensitive region is an N-type doped region; or, the first photosensitive device is provided with a first N-type photosensitive region A first P-type region is provided in the substrate above the first N-type photosensitive region;

   The second photosensitive device is alternately provided with a plurality of second N-type photosensitive regions and second P-type regions to form a plurality of the second pn junctions, and each of the second N-type photosensitive regions is connected from its upper end, and Covering the surface of the second pn junction, each of the second P-type regions is connected from its lower end, and covers the bottom surface of the trench; wherein,

   An isolation layer is arranged between the first photosensitive device and the second photosensitive device, and the second P-type region is connected to the first P-type region through the isolation layer; the first N-type region A third P-type region is arranged in the substrate on one side of the photosensitive region, and the first P-type region is a P ⁺ -type doped region.
4. The image sensor structure according to claim 3, wherein a shallow trench isolation is provided in the third P-type region for isolating the first N-type photosensitive region used for light-sensing from other external regions , the second P-type region is connected to the third P-type region through the isolation layer, and the third P-type region extends along the bottom and sidewalls of the shallow trench isolation to connect with the first P-type region districts are connected.
5. The image sensor structure according to claim 4, wherein a silicide region is provided on the third P-type region, and the third P-type region is connected to the metal interconnection layer through the silicide region.
6. 6. The image sensor structure according to claim 5, wherein the second P-type region is connected to the third P-type region and the silicide region through an open region provided by the isolation layer.
7. The image sensor structure according to claim 3, wherein the second N-type photosensitive region and the surface of the dielectric layer are covered with a fourth P-type region, and one side of the fourth P-type region is provided with There is a fifth P-type region, and the lower end of the fifth P-type region protrudes from the fourth P-type region and is connected to the metal interconnection layer in the dielectric layer.
8. The image sensor structure according to claim 7, wherein the fourth P-type region is covered with a dielectric protection layer.
9. The image sensor structure according to claim 7, wherein the substrate is a P ^- type doped substrate, and the third P-type region and the fifth P-type region are P ⁺ -type doped regions , the fourth P-type region is a P ^- type doped region, the second P-type region located in the second pn junction is a P-type doped region, and the first P-type region located on the bottom surface of the trench The two P-type regions are P ⁺ -type doped regions, and the second N-type photosensitive region is an N-type doped region.
10. 8. The image sensor structure of claim 7, wherein the second P-type region further extends from the bottom of the trench to the sidewall of the trench and from one side of the trench The wall extends to the surface of the dielectric layer and is connected to the fourth P-type region and the fifth P-type region.
11. 3. The image sensor structure according to claim 3, wherein the second N-type photosensitive region is connected to the first P-type region through the second P-type region, the isolation layer and the first P-type region in sequence. An N-type photosensitive region.
12. The image sensor structure according to claim 11, wherein a first transfer transistor is provided in the substrate, and the first photosensitive device is coupled to the first transfer transistor.
13. 8. The image sensor structure according to claim 8, wherein the second N-type photosensitive region is separated from the first P-type region and the first N-type photosensitive region by the isolation layer.
14. 14. The image sensor structure according to claim 13, wherein a first transfer transistor is arranged in the substrate, the first photosensitive device is coupled to the first transfer transistor, and the fourth P-type region is located on the A second pass transistor is provided, and the second photosensitive device is coupled to the second pass transistor.
15. 15. The image sensor structure according to claim 14, wherein the second pass transistor is disposed on the other side of the fourth P-type region, and the second pass transistor is disposed on the outer side of the trench. A gate electrode is formed on the dielectric protection layer, a drain is formed in the fourth P-type region, and the second N-type photosensitive region extends outward from the upper end of the trench and is formed under the gate electrode partially overlap to form a source of the second pass transistor, and the fourth P-type region between the source and drain forms a channel of the second pass transistor.
16. 3. The image sensor structure of claim 3, wherein the second pn junction completely fills the trench.
17. 3. The image sensor structure according to claim 3, wherein the second pn junction partially fills the trench, and a recessed structure is formed on the surface of the second N-type photosensitive region located in the trench. .
18. The image sensor structure according to claim 8, wherein the upper end of the fifth P-type region is drawn out from the surface of the dielectric protection layer through an electrode.

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