CN116540822B - Zero temperature coefficient voltage adjustable reference voltage circuit and chip - Google Patents

Zero temperature coefficient voltage adjustable reference voltage circuit and chip Download PDF

Info

Publication number
CN116540822B
CN116540822B CN202310601540.4A CN202310601540A CN116540822B CN 116540822 B CN116540822 B CN 116540822B CN 202310601540 A CN202310601540 A CN 202310601540A CN 116540822 B CN116540822 B CN 116540822B
Authority
CN
China
Prior art keywords
resistor
enhanced
electrically connected
temperature coefficient
tube
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202310601540.4A
Other languages
Chinese (zh)
Other versions
CN116540822A (en
Inventor
黄栋
马怀昌
梁静迎
潘俊男
周志奇
林丽
李琳
梅子
孙丽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Ruixing Microelectronics Technology Co ltd
Original Assignee
Shanghai Ruixing Microelectronics Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Ruixing Microelectronics Technology Co ltd filed Critical Shanghai Ruixing Microelectronics Technology Co ltd
Priority to CN202310601540.4A priority Critical patent/CN116540822B/en
Publication of CN116540822A publication Critical patent/CN116540822A/en
Application granted granted Critical
Publication of CN116540822B publication Critical patent/CN116540822B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation

Abstract

The application discloses a zero temperature coefficient voltage adjustable reference voltage circuit and a chip, wherein the reference voltage circuit comprises a depletion type NMOS tube and an enhancement type MOS tube, and further comprises a positive temperature regulator; the grid electrode of the depletion type NMOS tube is electrically connected with the source electrode, and the source electrode of the depletion type NMOS tube is a reference voltage output end; one end of the positive temperature regulator is electrically connected with the source electrode of the depletion type NMOS tube, and the other end of the positive temperature regulator is electrically connected with the enhancement type MOS tube; in the reference voltage output by the reference voltage output end, a third positive temperature coefficient item associated with the positive temperature regulator is added, and the third positive temperature coefficient item and the second positive temperature coefficient item are used for compensating the first negative temperature coefficient item, so that the reference voltage circuit can reach the required zero temperature coefficient voltage under the condition of keeping the temperature characteristic of the reference voltage unchanged.

Description

Zero temperature coefficient voltage adjustable reference voltage circuit and chip
Technical Field
The present application relates to the field of electronic circuits, and more particularly, to a zero temperature coefficient voltage adjustable reference voltage circuit and chip.
Background
In some applications, it is often necessary to detect the working voltage inside the chip, so as to ensure the chip to work normally, for example, to perform necessary protection during low voltage, calibration during ADC acquisition, etc., where the working voltage inside the chip fluctuates along with the fluctuation of the output voltage of the power supply, and in order to enable each functional module in the chip or on the periphery of the chip to still operate accurately, a reference voltage is set in the chip.
The circuit part outputting the reference voltage is generally designed and calibrated according to the parameters required by the chip when the chip is designed, and the reference voltage V obtained at the moment REF Exhibiting a parabolic voltage-temperature curve, the coordinates of which lieIn the system, the vertical axis represents a voltage component, and the horizontal axis represents a temperature component. The circuit for outputting the reference voltage can be formed by sequentially connecting and building a depletion type NMOS tube, an enhancement type PMOS tube and an enhancement type NMOS tube, wherein the connection point of the depletion type NMOS tube and the enhancement type PMOS tube is the output end of the reference voltage, one end of the depletion type NMOS tube, which is far away from the enhancement type PMOS tube, is connected with the working voltage, and one end of the enhancement type NMOS tube, which is far away from the enhancement type PMOS tube, is grounded.
However, in the case of actually applying the above circuit, if the reference voltage of the chip is 1.2v, only 1.25v is obtained after the circuit is built, a low dropout regulator (LDO) circuit is required to switch the reference voltage from 1.25v to 1.2v, so that the structure of the chip circuit is increased, and the cost of the chip is increased.
Disclosure of Invention
Aiming at the technical problem that the cost of a chip is increased because the existing chip needs to use a low-dropout voltage regulator for reference voltage collocation, the application provides a zero-temperature-coefficient voltage-adjustable reference voltage circuit and a chip.
In a first aspect, the present application provides a zero temperature coefficient voltage adjustable reference voltage circuit, which comprises the following technical schemes:
the reference voltage circuit with the adjustable zero temperature coefficient voltage comprises a depletion type NMOS tube, an enhancement type MOS tube and a positive temperature regulator, wherein the positive temperature regulator is provided with two electric connection ends;
the drain electrode of the depletion type NMOS tube is electrically connected with a first voltage end, the grid electrode of the depletion type NMOS tube is electrically connected with the source electrode of the depletion type NMOS tube, and the source electrode of the depletion type NMOS tube is a reference voltage output end;
one electric connection end of the positive temperature regulator is electrically connected with the source electrode of the depletion type NMOS tube, and the other electric connection end of the positive temperature regulator is electrically connected with a second voltage end through the enhancement type MOS tube;
among the reference voltages output from the reference voltage output terminals,
the enhanced MOS tube is associated with a first negative temperature coefficient item, and the first negative temperature coefficient item and the threshold voltage of the enhanced MOS tube are in linear relation;
the depletion type NMOS tube and the enhancement type MOS tube are associated with a second positive temperature coefficient item, and the second positive temperature coefficient item and the threshold voltage of the depletion type NMOS tube are in linear relation;
the positive temperature regulator is associated with the depletion type NMOS tube with a third positive temperature coefficient term, and the third positive temperature coefficient term is in square relation with the threshold voltage of the depletion type NMOS tube.
Through the technical scheme, the reference voltage comprises three temperature coefficient items, namely a first negative temperature coefficient item, a second positive temperature coefficient item and a third positive temperature coefficient item, wherein the first negative temperature coefficient item is related to the enhancement type MOS tube, the second positive temperature coefficient item is related to the depletion type NMOS tube and the enhancement type MOS tube, and the third positive temperature coefficient item is related to the depletion type NMOS tube and the positive temperature regulator;
after adding the positive temperature regulator, a third positive temperature coefficient term is generated in a square relationship, and the third positive temperature coefficient term is used for compensating the first negative temperature coefficient term together with the second positive temperature coefficient term in a linear relationship. Because of the different positive temperature characteristics of the second positive temperature coefficient item and the third positive temperature coefficient item, the parameters of the positive temperature regulator can be regulated in the opposite direction by regulating the proportional coefficient in front of the threshold voltage in the second positive temperature coefficient item, so that the reference voltage circuit can reach the required zero temperature coefficient voltage under the condition of keeping the temperature characteristic of the reference voltage unchanged, a low-voltage-difference voltage stabilizer is not required to be additionally arranged outside the circuit, the requirement of a chip can be met only by adding the positive temperature regulator, and the cost of the positive temperature regulator is lower than that of the low-voltage-difference voltage stabilizer, and the cost of the chip is reduced.
Preferably, the enhanced MOS tube is an enhanced PMOS tube;
the other electric connection end of the positive temperature regulator is electrically connected with the source electrode of the enhanced PMOS tube;
the grid electrode of the enhanced PMOS tube is electrically connected with the drain electrode of the enhanced PMOS tube, and the drain electrode of the enhanced PMOS tube is electrically connected with the second voltage end.
Preferably, the enhanced MOS tube is an enhanced NMOS tube;
the other electric connection end of the positive temperature regulator is electrically connected with the drain electrode of the enhanced NMOS tube;
the drain electrode of the enhanced NMOS tube is electrically connected with the grid electrode of the enhanced NMOS tube, and the source electrode of the enhanced NMOS tube is electrically connected with the second voltage end.
Preferably, the enhanced MOS tube is an enhanced PMOS tube and an enhanced NMOS tube;
the other electric connection end of the positive temperature regulator is electrically connected with the source electrode of the enhanced PMOS tube;
the grid electrode of the enhanced PMOS tube is electrically connected with the drain electrode of the enhanced PMOS tube, and the drain electrode of the enhanced PMOS tube is electrically connected with the drain electrode of the enhanced NMOS tube;
the drain electrode of the enhanced NMOS tube is electrically connected with the grid electrode of the enhanced NMOS tube, and the source electrode of the enhanced NMOS tube is electrically connected with a second voltage end.
Preferably, the positive temperature regulator includes a regulating resistor R0.
Through the technical scheme, the reference voltage circuit is arranged in the chip, the adjusting resistor R0 is required to be manufactured when the chip is manufactured, the manufacturing difficulty is reduced, meanwhile, the adjusting resistor R0 has only impedance, no additional influencing parameters such as additional capacitance resistance are avoided, the calculation complexity is simplified, and the method is most suitable for a positive temperature regulator.
Preferably, the positive temperature regulator includes a first resistor R1 and a second resistor R2 arranged in series, one end of the first resistor R1, which is not electrically connected to the second resistor R2, is the electrical connection end, and one end of the second resistor R2, which is not electrically connected to the first resistor R1, is the other electrical connection end.
Through the technical scheme, after the first resistor R1 and the second resistor R2 are connected in series, a more proper resistance value can be obtained, the manufacturing difficulty of the process is reduced, and the flexibility of distribution of the resistance value in the chip is improved.
Preferably, the positive temperature regulator includes a third resistor R3 and a fourth resistor R4 arranged in parallel, and two ends of the third resistor R3 are the electrical connection ends.
Through the technical scheme, the first resistor R1 and the second resistor R2 can be connected in parallel to obtain a more proper resistance value, and when one of the resistors is disconnected, the circuit can also output a calculable voltage for secondary use to form a reference voltage.
Preferably, the positive temperature regulator includes a first resistor R1, a second resistor R2, and a third resistor R3, the first resistor R1 and the second resistor R2 are arranged in series, and the second resistor R2 and the third resistor R3 are arranged in parallel;
one end of the first resistor R1, which is not electrically connected to the second resistor R2, is one of the electrical connection ends, and one end of the second resistor R2, which is not electrically connected to the first resistor R1, is the other of the electrical connection ends.
According to the technical scheme, after the series resistors and the parallel resistors are connected in series, the required resistance can be obtained, a more proper resistance can be obtained, the manufacturing difficulty of the process is reduced, and the flexibility of the distribution of the resistance in the chip is improved; meanwhile, when one of the second resistor R2 and the third resistor R3 is disconnected, the circuit can output a calculable voltage for secondary use as a reference voltage.
Preferably, the first voltage terminal is a working voltage terminal of the chip, and the second voltage terminal is a ground terminal.
Through the technical scheme, the working voltage end of the chip supplies power for the circuit, so that the reference voltage which can be directly used is provided for the chip.
In a second aspect, the present application provides a chip, which has the following technical scheme:
a chip comprises the zero temperature coefficient voltage adjustable reference voltage circuit.
In summary, the beneficial effects of the invention are as follows:
(1) By adding a positive temperature regulator, a third positive temperature coefficient term which is square with the threshold voltage of the depletion type NMOS tube is generated in the reference voltage, and the third positive temperature coefficient term and the second positive temperature coefficient term which are linear with the threshold voltage of the depletion type NMOS tube are used for compensating the first negative temperature coefficient term. Because of the different positive temperature characteristics of the second positive temperature coefficient item and the third positive temperature coefficient item, the parameter of the positive temperature regulator can be regulated in the opposite direction by regulating the proportional coefficient in front of the threshold voltage in the second positive temperature coefficient item, so that the reference voltage circuit can reach the required zero temperature coefficient voltage under the condition of keeping the temperature characteristic of the reference voltage unchanged.
(2) The positive temperature regulator adopts the regulating resistor R0, the regulating resistor R0 has only impedance, and no additional influencing parameters such as additional capacitive reactance are adopted, so that the calculation complexity is simplified, and the positive temperature regulator is suitable for the positive temperature regulator.
Drawings
FIG. 1 is a circuit diagram of the prior art;
FIG. 2 is a circuit diagram of an embodiment of the present application having a tuning resistor R0;
fig. 3 is a circuit diagram of a first resistor R1 in series with a second resistor R2 in an embodiment of the present application;
fig. 4 is a circuit diagram of a third resistor R3 in parallel with a fourth resistor R4 in an embodiment of the present application;
fig. 5 is a circuit diagram of the first resistor R1 and the second resistor R2 connected in series and the second resistor R2 and the third resistor R3 connected in parallel in the embodiment of the present application.
Detailed Description
The present application is described in detail below with reference to fig. 1-5 and examples.
In the prior art, as shown in fig. 1, the reference voltage circuit includes a depletion type NMOS transistor, an enhancement type PMOS transistor, and an enhancement type NMOS transistor. The drain electrode of the depletion type NMOS tube is electrically connected with the working voltage end of the chip, the grid electrode of the depletion type NMOS tube is electrically connected with the source electrode of the depletion type NMOS tube, and the source electrode of the depletion type NMOS tube is a reference voltage output end and is electrically connected with the source electrode of the enhancement type PMOS tube. The grid electrode of the enhanced PMOS tube is electrically connected with the drain electrode of the enhanced PMOS tube, the drain electrode of the enhanced PMOS tube is electrically connected with the drain electrode of the enhanced NMOS tube, the drain electrode of the enhanced NMOS tube is electrically connected with the grid electrode of the enhanced NMOS tube, and the source electrode of the enhanced NMOS tube is grounded. The working voltage end of the chip supplies power for the reference voltage circuit, so that the reference voltage which can be directly used is provided for the chip.
The reference voltage output by the reference voltage output end comprises two temperature coefficient items, namely a first negative temperature coefficient item and a second positive temperature coefficient item, wherein the first negative temperature coefficient item is related to the enhanced PMOS tube and the enhanced NMOS tube, and the second positive temperature coefficient item is related to the depletion type NMOS tube, the enhanced PMOS tube and the enhanced NMOS tube. The threshold voltages of the enhancement type PMOS tube and the enhancement type NMOS tube are in negative temperature coefficients, the threshold voltages of the depletion type NMOS tube are in positive temperature coefficients, and the threshold voltages of the enhancement type PMOS tube and the enhancement type NMOS tube are added with the threshold voltages of the depletion type NMOS tube according to a certain proportion coefficient, so that a reference voltage with a small temperature coefficient can be obtained. Under the conditions of selecting a process and the type of MOS tube devices, the zero temperature coefficient voltage of the reference voltage is constant and cannot be changed. Specifically, reference voltage V REF The formula of (2) is as follows:
wherein V is th_D Is negative;
V th_P +V th_N is a first negative temperature coefficient term;
is a second positive temperature coefficient term;
V th_D is the threshold voltage of the depletion type NMOS tube; mu (mu) D Electron mobility for depletion type NMOS; cox (Cox) D A unit area gate oxide capacitor which is a depletion type NMOS tube; w (W) D The width of the channel of the depletion type NMOS tube; l (L) D Is the length of the channel of the depletion type NMOS tube;
V th_P the threshold voltage of the enhanced PMOS tube; mu (mu) P Hole mobility of the enhanced PMOS tube; cox (Cox) P A unit area gate oxide capacitor for the enhanced PMOS tube; w (W) P The width of the channel of the enhanced PMOS tube is the width of the channel of the enhanced PMOS tube; l (L) P The length of the channel of the enhanced PMOS tube is;
V th_N is the threshold voltage of the enhanced NMOS transistor; mu (mu) N Electron mobility for the enhanced NMOS transistor; cox (Cox) N A unit area gate oxide capacitor of the enhanced NMOS transistor; w (W) N The width of the channel of the enhanced NMOS tube; l (L) N Is the length of the enhanced NMOS tube channel.
Both electron mobility and hole mobility have negative temperature coefficient terms, wherein,the negative temperature coefficient term between the electron mobility of the two NMOS tubes can have a certain counteracting effect; but->Although the effect of the temperature coefficient term between the NMOS tube and the PMOS tube can not be completely counteracted, the use of the circuit calculation result is not affected.
The embodiment discloses a zero temperature coefficient voltage adjustable reference voltage circuit, which is added with a positive temperature regulator, wherein the positive temperature regulator is provided with two electric connection ends, an adjusting resistor R0 can be adopted, one electric connection end of the adjusting resistor R0 is electrically connected with a source electrode of a depletion type NMOS tube, and the other electric connection end of the adjusting resistor R0 is electrically connected with an enhancement type MOS tube. The depletion type NMOS tube can adopt a Native-NMOS device, and the enhancement type MOS tube can adopt an enhancement type PMOS tube and/or an enhancement type NMOS tube.
Specifically, when the enhancement type MOS is an enhancement type PMOS tube, the other electric connection end of the positive temperature regulator is electrically connected with the source electrode of the enhancement type PMOS tube; the grid electrode of the enhanced PMOS tube is electrically connected with the drain electrode of the enhanced PMOS tube, and the drain electrode of the enhanced PMOS tube is electrically connected with the second voltage end. When the enhancement type MOS is an enhancement type NMOS tube, the other electric connection end of the positive temperature regulator is electrically connected with the drain electrode of the enhancement type NMOS tube; the drain electrode of the enhanced NMOS tube is electrically connected with the grid electrode of the enhanced NMOS tube, and the source electrode of the enhanced NMOS tube is electrically connected with the second voltage end. When the enhancement type MOS tube is an enhancement type PMOS tube and an enhancement type NMOS tube, the other electric connection end of the positive temperature regulator is electrically connected with the source electrode of the enhancement type PMOS tube; the grid electrode of the enhanced PMOS tube is electrically connected with the drain electrode of the enhanced PMOS tube, and the drain electrode of the enhanced PMOS tube is electrically connected with the drain electrode of the enhanced NMOS tube; the drain electrode of the enhanced NMOS tube is electrically connected with the grid electrode of the enhanced NMOS tube, and the source electrode of the enhanced NMOS tube is electrically connected with a second voltage end. The enhancement type MOS tube is taken as an enhancement type PMOS tube and the enhancement type NMOS tube is used for example analysis.
As shown in fig. 2, the reference voltage circuit is disposed in the chip, and the adjusting resistor R0 needs to be manufactured when the chip is manufactured, so that the manufacturing difficulty is reduced, and meanwhile, the adjusting resistor R0 has only impedance, has no additional influencing parameters such as additional capacitance, simplifies the calculation complexity, and is most suitable for a positive temperature regulator.
After the reference voltage circuit is added with the positive temperature regulator, the reference voltage comprises three temperature coefficient items, namely a first negative temperature coefficient item, a second positive temperature coefficient item and a third positive temperature coefficient item. Specifically, reference voltage V REF The formula of (2) is as follows:
wherein V is th_D Is negative;
V th_P +V th_N is a first negative temperature coefficient term;
is a second positive temperature coefficient term;
is a third positive temperature coefficient term, wherein R is the resistance value of the positive temperature regulator.
The first negative temperature coefficient term is associated with the enhanced PMOS tube and the enhanced NMOS tube. The second positive temperature coefficient term is related to the depletion type NMOS tube, the enhancement type PMOS tube and the enhancement type NMOS tube and is in linear relation with the threshold voltage of the depletion type NMOS. After the positive temperature regulator is added, a third positive temperature coefficient item is generated, wherein the third positive temperature coefficient item is related to the depletion type NMOS tube and the positive temperature regulator and is in square relation with the threshold voltage of the depletion type NMOS tube. The second positive temperature coefficient term and the third positive temperature coefficient term are used for compensating the first negative temperature coefficient term, and as the second positive temperature coefficient term and the threshold voltage of the depletion type NMOS tube are in linear relation, the third positive temperature coefficient term and the threshold voltage of the depletion type NMOS tube are in square relation, and the positive temperature coefficient terms of the second positive temperature coefficient term and the third positive temperature coefficient term are not the same. The positive temperature coefficient of proportionality of the second positive temperature coefficient term may be reduced, for example: the width-to-length ratio of the enhancement MOS tube can be increased, and meanwhile, the positive temperature proportionality coefficient of the third positive temperature coefficient item is increased, for example: the resistance value of the positive temperature regulator can be increased, and the reference voltage circuit can reach the required zero temperature coefficient voltage under the condition of keeping the temperature characteristic of the reference voltage unchanged; and vice versa. The low-dropout voltage regulator is not required to be additionally arranged outside the circuit, the requirement of the chip can be met only by adding the positive temperature regulator, the cost of the positive temperature regulator is lower than that of the low-dropout voltage regulator, and the cost of the chip is reduced.
Instead of using a single regulating resistor R0 as the positive temperature regulator, in another case, as shown in fig. 3, the positive temperature regulator may employ a first resistor R1 and a second resistor R2 disposed in series, one end of the first resistor R1, which is not electrically connected to the second resistor R2, being one electrical connection terminal, and one end of the second resistor R2, which is not electrically connected to the first resistor R1, being the other electrical connection terminal. After the first resistor R1 and the second resistor R2 are connected in series, a more proper resistance value can be obtained, the manufacturing difficulty of the process is reduced, and the flexibility of the distribution of the resistance value in the chip is improved.
In addition to using a plurality of resistors R connected in series as the positive temperature regulator, in another case, as shown in fig. 4, the positive temperature regulator may further employ a third resistor R3 and a fourth resistor R4 arranged in parallel, and both ends of the third resistor R3 are electrically connected. The first resistor R1 and the second resistor R2 can obtain more proper resistance after being connected in parallel, and when one of the resistors is disconnected, the circuit can also output a calculable voltage for secondary use to form a reference voltage.
In the case of the chip function, as shown in fig. 5, the positive temperature regulator may further employ a first resistor R1, a second resistor R2 and a third resistor R3, where the first resistor R1 and the second resistor R2 are disposed in series, and the second resistor R2 and the third resistor R3 are disposed in parallel. One end of the first resistor R1, which is not electrically connected to the second resistor R2, is an electrical connection end, and one end of the second resistor R2, which is not electrically connected to the first resistor R1, is another electrical connection end. The series resistors and the parallel resistors can obtain the required resistance after being connected in series, so that a more proper resistance can be obtained, the manufacturing difficulty of the process is reduced, and the flexibility of the distribution of the resistance in the chip is improved; meanwhile, when one of the second resistor R2 and the third resistor R3 is disconnected, the circuit can output a calculable voltage for secondary use as a reference voltage.
The embodiment also discloses a chip comprising the zero temperature coefficient voltage-adjustable reference voltage circuit.
The above description is only a preferred embodiment of the present invention, and the scope of the present application is not limited to the above examples, but all technical solutions belonging to the concept of the present application belong to the scope of the present application. It should be noted that modifications and adaptations to those skilled in the art without departing from the principles of the present application are intended to be comprehended within the scope of the present application.

Claims (9)

1. The utility model provides a zero temperature coefficient voltage adjustable reference voltage circuit, includes depletion type NMOS pipe and enhancement type MOS pipe, its characterized in that: the temperature regulator is provided with two electric connection ends;
the drain electrode of the depletion type NMOS tube is electrically connected with a first voltage end, the grid electrode of the depletion type NMOS tube is electrically connected with the source electrode of the depletion type NMOS tube, and the source electrode of the depletion type NMOS tube is a reference voltage output end;
one electric connection end of the positive temperature regulator is electrically connected with the source electrode of the depletion type NMOS tube, and the other electric connection end of the positive temperature regulator is electrically connected with a second voltage end through the enhancement type MOS tube;
among the reference voltages output from the reference voltage output terminals,
the enhanced MOS tube is associated with a first negative temperature coefficient item, and the first negative temperature coefficient item and the threshold voltage of the enhanced MOS tube are in linear relation;
the depletion type NMOS tube and the enhancement type MOS tube are associated with a second positive temperature coefficient item, and the second positive temperature coefficient item and the threshold voltage of the depletion type NMOS tube are in linear relation;
the positive temperature regulator is associated with the depletion type NMOS tube, and a third positive temperature coefficient item is in square relation with the threshold voltage of the depletion type NMOS tube;
the enhancement type MOS tube is an enhancement type PMOS tube;
the other electric connection end of the positive temperature regulator is electrically connected with the source electrode of the enhanced PMOS tube;
the grid electrode of the enhanced PMOS tube is electrically connected with the drain electrode of the enhanced PMOS tube, and the drain electrode of the enhanced PMOS tube is electrically connected with the second voltage end.
2. The zero temperature coefficient voltage adjustable reference voltage circuit of claim 1, wherein:
the enhanced MOS tube is an enhanced NMOS tube;
the other electric connection end of the positive temperature regulator is electrically connected with the drain electrode of the enhanced NMOS tube;
the drain electrode of the enhanced NMOS tube is electrically connected with the grid electrode of the enhanced NMOS tube, and the source electrode of the enhanced NMOS tube is electrically connected with the second voltage end.
3. The zero temperature coefficient voltage adjustable reference voltage circuit of claim 1, wherein:
the enhanced MOS tube is an enhanced PMOS tube and an enhanced NMOS tube;
the other electric connection end of the positive temperature regulator is electrically connected with the source electrode of the enhanced PMOS tube;
the grid electrode of the enhanced PMOS tube is electrically connected with the drain electrode of the enhanced PMOS tube, and the drain electrode of the enhanced PMOS tube is electrically connected with the drain electrode of the enhanced NMOS tube;
the drain electrode of the enhanced NMOS tube is electrically connected with the grid electrode of the enhanced NMOS tube, and the source electrode of the enhanced NMOS tube is electrically connected with a second voltage end.
4. The zero temperature coefficient voltage adjustable reference voltage circuit of claim 1, wherein: the positive temperature regulator includes a regulating resistor R0.
5. The zero temperature coefficient voltage adjustable reference voltage circuit of claim 1, wherein: the positive temperature regulator comprises a first resistor R1 and a second resistor R2 which are arranged in series, wherein one end of the first resistor R1, which is not electrically connected with the second resistor R2, is one electric connection end, and one end of the second resistor R2, which is not electrically connected with the first resistor R1, is the other electric connection end.
6. The zero temperature coefficient voltage adjustable reference voltage circuit of claim 1, wherein: the positive temperature regulator comprises a third resistor R3 and a fourth resistor R4 which are arranged in parallel, and two ends of the third resistor R3 are the electric connection ends.
7. The zero temperature coefficient voltage adjustable reference voltage circuit of claim 1, wherein: the positive temperature regulator comprises a first resistor R1, a second resistor R2 and a third resistor R3, wherein the first resistor R1 and the second resistor R2 are arranged in series, and the second resistor R2 and the third resistor R3 are arranged in parallel;
one end of the first resistor R1, which is not electrically connected to the second resistor R2, is one of the electrical connection ends, and one end of the second resistor R2, which is not electrically connected to the first resistor R1, is the other of the electrical connection ends.
8. The zero temperature coefficient voltage adjustable reference voltage circuit of claim 1, wherein: the first voltage end is a working voltage end of the chip, and the second voltage end is a grounding end.
9. A chip, characterized in that: a reference voltage circuit comprising a zero temperature coefficient voltage adjustable according to any one of claims 1-8.
CN202310601540.4A 2023-05-25 2023-05-25 Zero temperature coefficient voltage adjustable reference voltage circuit and chip Active CN116540822B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310601540.4A CN116540822B (en) 2023-05-25 2023-05-25 Zero temperature coefficient voltage adjustable reference voltage circuit and chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310601540.4A CN116540822B (en) 2023-05-25 2023-05-25 Zero temperature coefficient voltage adjustable reference voltage circuit and chip

Publications (2)

Publication Number Publication Date
CN116540822A CN116540822A (en) 2023-08-04
CN116540822B true CN116540822B (en) 2024-01-30

Family

ID=87454203

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310601540.4A Active CN116540822B (en) 2023-05-25 2023-05-25 Zero temperature coefficient voltage adjustable reference voltage circuit and chip

Country Status (1)

Country Link
CN (1) CN116540822B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201804292U (en) * 2010-04-23 2011-04-20 比亚迪股份有限公司 Reference voltage generating circuit
CN202433801U (en) * 2012-02-15 2012-09-12 上海新进半导体制造有限公司 Reference voltage circuit
JP2016092304A (en) * 2014-11-07 2016-05-23 富士電機株式会社 Semiconductor circuit device
CN115668093A (en) * 2020-05-27 2023-01-31 罗姆股份有限公司 Constant voltage generating circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9632521B2 (en) * 2013-03-13 2017-04-25 Analog Devices Global Voltage generator, a method of generating a voltage and a power-up reset circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201804292U (en) * 2010-04-23 2011-04-20 比亚迪股份有限公司 Reference voltage generating circuit
CN202433801U (en) * 2012-02-15 2012-09-12 上海新进半导体制造有限公司 Reference voltage circuit
JP2016092304A (en) * 2014-11-07 2016-05-23 富士電機株式会社 Semiconductor circuit device
CN115668093A (en) * 2020-05-27 2023-01-31 罗姆股份有限公司 Constant voltage generating circuit

Also Published As

Publication number Publication date
CN116540822A (en) 2023-08-04

Similar Documents

Publication Publication Date Title
TWI459173B (en) Reference voltage generation circuit and reference voltage generation method
CN1042269C (en) Reference voltage generator with cmos transistor
CN210691138U (en) Linear voltage regulator circuit
CN115145346B (en) Band gap reference circuit
CN116540822B (en) Zero temperature coefficient voltage adjustable reference voltage circuit and chip
CN114185390A (en) Band-gap reference voltage source circuit, integrated circuit and electronic equipment
CN115079762B (en) Low dropout linear voltage regulator circuit
CN113126683A (en) E/D NMOS reference voltage source and low dropout voltage regulator
CN113885649B (en) Low-dropout linear voltage regulator
CN214253044U (en) Current source circuit and electronic equipment
CN113031694B (en) Low-power-consumption low-dropout linear regulator and control circuit thereof
US20080030274A1 (en) Gate Bias Generator
CN112558680B (en) Linear regulator and control circuit thereof
CN113885639A (en) Reference circuit, integrated circuit, and electronic device
El Khadiri et al. A low noise, high PSR low-dropout regulator for low-cost portable electronics
CN205507607U (en) Double -purpose way electric current source generator
CN219958115U (en) Voltage stabilizer, chip and electronic equipment
CN220139527U (en) Active bias circuit, amplifier and radio frequency front-end module
CN115202427B (en) Voltage stabilizing circuit and power management chip
US11609591B2 (en) Reference circuit with temperature compensation
CN114895739B (en) LDO circuit
CN110716606B (en) Low-power-consumption anti-electromagnetic interference reference current source
CN111522385B (en) Low dropout regulator of PMOS output power tube
CN113904549A (en) LDO (low dropout regulator) without off-chip capacitor
CN220271785U (en) Electronic equipment

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant