CN116520935A

CN116520935A - Low-dropout linear voltage regulator

Info

Publication number: CN116520935A
Application number: CN202210065079.0A
Authority: CN
Inventors: 徐文伟
Original assignee: Glenfly Tech Co Ltd
Current assignee: Glenfly Tech Co Ltd
Priority date: 2022-01-20
Filing date: 2022-01-20
Publication date: 2023-08-01

Abstract

The invention discloses a low-dropout linear voltage stabilizing circuit which comprises a buffer module, a load current detection module, an error amplifier, a power tube, a first resistor and a second resistor, wherein the buffer module is connected with the load current detection module; the buffer module is used for improving the output voltage of the error amplifier; the load current detection module is used for detecting the magnitude of load current and changing the magnitude of current supplied to the buffer module according to the magnitude of the load current. The low dropout linear voltage regulator circuit provided by the invention is a low dropout linear voltage regulator of a push-pull stage, which has low static power consumption and large load current of the push-pull output stage, and does not increase static power consumption while increasing driving capability, and can effectively solve the problem of large power consumption of the low dropout linear voltage regulator of the push-pull output stage.

Description

Low-dropout linear voltage regulator

Technical Field

The present invention relates to a low dropout linear voltage regulator, and more particularly to a low dropout linear voltage regulator with low static power consumption and high load current for a push-pull output stage.

Background

With the rapid development of semiconductor technology, the power supply voltage of an integrated circuit is lower and lower, which puts higher and higher demands on the output voltage precision, response speed, noise performance and the like of an input voltage terminal. Therefore, the input voltage terminal management module plays an increasingly important role in the electronics industry. The low dropout linear regulator (Low Dropout Regulator, LDO) is used as an important input voltage terminal management module, and is widely applied to SoC chip (system on a chip) design due to the characteristics of low noise, low cost, rapid transient characteristics and the like.

Along with the wide application of electronic products, the requirements of people on power consumption are higher and higher, and especially the requirements on static power consumption of portable products and long-term standby products are more severe, so that on the way that designers continuously pursue ultra-low power consumption, the problem of higher static power consumption of LDO (low dropout regulator) brings non-negligible influence to circuits. In the conventional LDO structure, there is a push-pull output, which generally increases the size of the output tube in order to increase the driving capability of the LDO, but this increases the static power consumption of the LDO. In view of this, the present invention provides a low-static power consumption and high load current low dropout linear voltage regulator for a push-pull output stage, which can effectively solve the problem of high power consumption of the low dropout linear voltage regulator for the push-pull output stage.

Disclosure of Invention

In a preferred embodiment, the present invention provides a low static power consumption, high load current low dropout linear regulator of a push-pull output stage, comprising: the error amplifier comprises a first buffer module, a second buffer module, a first detection module, a second detection module, a P-type metal oxide field effect power tube, an N-type metal oxide field effect power tube, a first resistor, a second resistor and a capacitor.

In some embodiments, the inverting input of the error amplifier is configured to receive a feedback voltage VFB and the non-inverting input is configured to receive a reference voltage VREF; the other first input terminal is coupled to a high power voltage VDD and the other second input terminal is coupled to a low power voltage VSS.

In some embodiments, the inputs of the first and second buffer modules are coupled to the output of the error amplifier; the other input end of the first buffer module is coupled to a high power voltage VDD, and the other input end of the second buffer module is coupled to a low power voltage VSS.

In some embodiments, the input of the first detection module is coupled to the output of the first buffer module, and the input of the second detection module is coupled to the output of the second buffer module; the other input end of the first detection module is coupled to a high power voltage VDD, and the other input end of the second detection module is coupled to a low power voltage VSS.

In some embodiments, the gates of the P-type mosfet MP and the N-type mosfet MN are coupled to the output ends of the first detection module and the second detection module, respectively; the source electrode of the P-type metal oxide field effect power tube MP is coupled to the high power supply voltage VDD, and the source electrode of the N-type metal oxide field effect power tube MN is coupled to the low power supply voltage VSS; the drain electrode of the P-type metal oxide field effect power tube MP is connected with the drain electrode of the N-type metal oxide field effect power tube MN.

In some embodiments, one end of the first resistor is coupled to a first node, and the other end is coupled to a second node. One end of the second resistor is coupled to the second node, and the other end of the second resistor is grounded. The capacitor CL is coupled between the third node and the fourth node.

In some embodiments, the first buffer module includes a first P-type metal oxide field effect transistor and a second P-type metal oxide field effect transistor; the second buffer module comprises a sixth N-type metal oxide field effect transistor and a seventh N-type metal oxide field effect transistor.

In some embodiments, the first detection module includes a third N-type metal oxide field effect transistor, a fourth P-type metal oxide field effect transistor, and a fifth P-type metal oxide field effect transistor; the second detection module comprises an eighth P-type metal oxide field effect transistor, a ninth N-type metal oxide field effect transistor and a tenth N-type metal oxide field effect transistor.

In some embodiments, the buffer module is configured to increase an output voltage of the error amplifier;

in some embodiments, the detection module (or referred to as a load current detection module) is configured to detect a magnitude of the load current and change a magnitude of the current provided to the buffer module according to the magnitude of the load current.

In some embodiments, the greater the load current, the less current is provided to the buffer module; the smaller the load current, the greater the current provided to the buffer module.

In some embodiments, the first buffer module and the second buffer module are identical or different in structure, and/or the first load current detection module and the second load current detection module are identical or different in structure.

Drawings

FIG. 1 is a schematic diagram of a LDO according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a LDO according to another embodiment of the present invention.

FIG. 3 is a schematic diagram of a LDO according to another embodiment of the present invention.

Detailed Description

The following detailed description of the invention refers to the accompanying drawings, which illustrate specific embodiments of the invention.

Certain terms are used throughout the description and claims to refer to particular components. Those of ordinary skill in the art will appreciate that a hardware manufacturer may refer to the same element by different names. The description and claims do not take the form of an element differentiated by name, but rather by functional differences. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. In addition, the term "coupled" as used herein includes any direct or indirect electrical connection. Accordingly, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

The terms first, second, third and the like in the description and in the claims, are used for indicating identical or different elements. However, it will be appreciated by those skilled in the art that the terms of first order, such as those described above, are used without a sequential order therebetween, and are merely for convenience in description of the present invention in order to distinguish between two elements having the same name, rather than in order to define a manner or order of coupling the elements.

FIG. 1 is a schematic diagram of a LDO according to an embodiment of the present invention. As shown in fig. 1, the low dropout linear regulator includes an error amplifier EA, a pmos MP, an nmos MN, a first resistor R1, a second resistor R2, and a capacitor CL.

The error amplifier EA has an inverting input terminal for receiving the feedback voltage VFB and a non-inverting input terminal for receiving the reference voltage VREF (as shown in fig. 1, the inverting input terminal is denoted by "-" and the non-inverting input terminal is denoted by "+"), and the voltages of the two input terminals are virtually short, i.e., the reference voltage VREF is equal to the feedback voltage VFB. The error amplifier EA has another first input coupled to a high power voltage VDD (e.g., 5V) and another second input coupled to a low power voltage VSS (e.g., 0V).

The gates of the P-type mosfet MP and the N-type mosfet MN are coupled to the output end of the error amplifier EA (as shown in fig. 1, the gate voltage VGP of the P-type mosfet MP and the gate voltage VGN of the N-type mosfet MN); the source electrode of the P-type metal oxide field effect power tube MP is coupled to the high power supply voltage VDD, and the source electrode of the N-type metal oxide field effect power tube MN is coupled to the low power supply voltage VSS; the drain electrode of the P-type metal oxide field effect power tube MP is connected with the drain electrode of the N-type metal oxide field effect power tube MN.

One end of the first resistor R1 is coupled to the first node N1, and the other end is coupled to the second node N2. One end of the second resistor R2 is coupled to the second node N2, and the other end is grounded. The capacitor CL is coupled between the third node N3 and the fourth node N4. The first resistor R1, the second resistor R2 and the capacitor CL are used for introducing frequency compensation to maintain the stability of the LDO; the first resistor R1, the second resistor R2 and the capacitor CL are used to form a dynamic frequency compensation network. Those skilled in the art will appreciate that the frequency compensation network may be comprised of other circuits within a variable range. The technical content of this section should be the common general knowledge of the person skilled in the art, and the present invention is not limited thereto.

The output voltage vout=vref (r1+r2)/R2 of the LDO. In order to increase the driving capability of the LDO, the sizes of the P-type metal oxide field effect power transistor MP and the N-type metal oxide field effect power transistor MN need to be increased, but the static power consumption of the LDO is increased, and the larger the area of the power transistor, the larger the capacitance, the more the generated pole is close to the main pole, which is not beneficial to frequency compensation.

FIG. 2 is a schematic diagram of a LDO according to another embodiment of the present invention. As shown in fig. 2, the low dropout linear regulator includes an error amplifier EA, a first buffer module, a second buffer module, a first detection module, a second detection module, a P-type mosfet MP, an N-type mosfet MN, a first resistor R1, a second resistor R2, and a capacitor CL.

The error amplifier EA has an inverting input for receiving the feedback voltage VFB and a non-inverting input (as shown in fig. 2, the inverting input is denoted by "-" and the non-inverting input is denoted by "+") for receiving the reference voltage VREF. The error amplifier EA has another first input coupled to a high power voltage VDD (e.g., 5V) and another second input coupled to a low power voltage VSS (e.g., 0V).

The input ends of the first buffer module and the second buffer module are coupled to the output end of the error amplifier EA (as shown in fig. 2, the input end of the first buffer module is coupled to the VGU of the output end of the error amplifier EA, and the input end of the second buffer module is coupled to the VGD of the output end of the error amplifier EA); the other input terminal of the first buffer module is coupled to a high power voltage VDD (e.g., may be 5V), and the other input terminal of the second buffer module is coupled to a low power voltage VSS (e.g., may be 0V).

The input end of the first detection module is coupled to the output end of the first buffer module, and the input end of the second detection module is coupled to the output end of the second buffer module; the other input terminal of the first detection module is coupled to a high power voltage VDD (e.g., may be 5V), and the other input terminal of the second detection module is coupled to a low power voltage VSS (e.g., may be 0V).

The gates of the P-type metal oxide field effect power transistor MP and the N-type metal oxide field effect power transistor MN are respectively coupled to the output ends of the first detection module and the second detection module (as shown in fig. 2, the gate voltage VGP of the P-type metal oxide field effect power transistor MP and the gate voltage VGN of the N-type metal oxide field effect power transistor MN); the source electrode of the P-type metal oxide field effect power tube MP is coupled to the high power supply voltage VDD, and the source electrode of the N-type metal oxide field effect power tube MN is coupled to the low power supply voltage VSS; the drain electrode of the P-type metal oxide field effect power tube MP is connected with the drain electrode of the N-type metal oxide field effect power tube MN.

The coupling manner of the first resistor R1, the second resistor R2 and the capacitor CL is the same as that of fig. 1, and the detailed coupling manner is described with reference to the relevant portion of fig. 1, and is not repeated here.

The buffer module is used for improving the output voltage of the error amplifier; the detection module is used for detecting the magnitude of the load current and changing the magnitude of the current supplied to the buffer module according to the magnitude of the load current.

According to a preferred embodiment of the invention, the larger the load current, the smaller the current supplied to the buffer module; the smaller the load current, the greater the current provided to the buffer module.

Here, the first buffer module and the second buffer module may have the same or different structures, and/or the first detection module and the second detection module may have the same or different structures.

According to an embodiment of the present invention, the first buffer module and the second buffer module are different in structure, and the first detection module and the second detection module are different in structure.

For a schematic circuit structure of the first buffer module, the second buffer module, the first detection module and the second detection module, please refer to fig. 3 for a description, and detailed descriptions thereof are omitted.

FIG. 3 is a schematic diagram of a LDO according to another embodiment of the present invention. As shown in fig. 3, the low dropout linear regulator includes an error amplifier EA, a first pmos fet M1, a second pmos fet M2, a third pmos fet M3, a fourth pmos fet M4, a fifth pmos fet M5, a sixth nmos fet M6, a seventh nmos fet M7, an eighth pmos fet M8, a ninth nmos fet M9, a tenth nmos fet M10, a pmos fet MP, an nmos fet MN, a first resistor R1, a second resistor R2 and a capacitor CL.

As shown in fig. 2, the first buffer module includes a first P-type metal oxide field effect transistor M1 and a second P-type metal oxide field effect transistor M2; the second buffer module includes a sixth N-type metal oxide field effect transistor M6 and a seventh N-type metal oxide field effect transistor M7 (as shown in fig. 3, the first buffer module and the second buffer module are represented by dashed boxes 1).

As shown in fig. 2, the first detection module includes a third N-type metal oxide field effect transistor M3, a fourth P-type metal oxide field effect transistor M4 and a fifth P-type metal oxide field effect transistor M5; the second detection module includes an eighth pmos fet M8, a ninth nmos fet M9, and a tenth nmos fet M10 (as shown in fig. 3, the first detection module and the second detection module are indicated by dashed boxes 2).

The sources of the second P-type metal oxide field effect transistor M2, the fourth P-type metal oxide field effect transistor M4 and the fifth P-type metal oxide field effect transistor M5 are coupled to a high power voltage VDD (e.g., may be 5V); the drain of the second P-type metal oxide field effect transistor M2 is coupled to the source of the first P-type metal oxide field effect transistor M1 through the fifth node N5 (or is connected to the drain of the fifth P-type metal oxide field effect transistor M5 through the fifth node N5 and the seventh node N7, or is connected to the gate of the third N-type metal oxide field effect transistor M3 through the fifth node N5, the seventh node N7 and the eighth node N8, or is connected to the gate of the P-type metal oxide field effect transistor MP through the fifth node N5, the seventh node N7 and the eighth node N8), and the gate is coupled to the bias voltage VBP (VBP is herein the gate voltage coupled to the second P-type metal oxide field effect transistor M2, which may be multiplexed with the reference voltage VREF of the error amplifier EA, but the present application is not limited thereto). The drain electrode of the fourth P-type metal oxide field effect transistor M4 is connected with the drain electrode of the third N-type metal oxide field effect transistor M3 through a sixth node N6, and the grid electrode is connected with the grid electrode of the fifth P-type metal oxide field effect transistor M5 through a ninth node N9. The drain electrode of the fifth P-type metal oxide field effect transistor M5 is connected to the source electrode of the first P-type metal oxide field effect transistor M1 through the seventh node N7 and the fifth node N5 (or connected to the gate electrode of the third N-type metal oxide field effect transistor M3 through the seventh node N7 and the eighth node N8, or connected to the gate electrode of the P-type metal oxide field effect transistor MP through the seventh node N7 and the eighth node N8, or connected to the drain electrode of the second P-type metal oxide field effect transistor M2 through the seventh node N7 and the fifth node N5); the gate is connected to the gate of the fourth pmos M4 through the ninth node N9 (or to the drain of the fourth pmos M4 through the ninth node N9 and the sixth node N6).

The sixth node N6 is electrically connected to the ninth node N9.

The source electrode of the first P-type metal oxide field effect transistor M1 is connected to the drain electrode of the second P-type metal oxide field effect transistor M2 through a fifth node N5 (or connected to the drain electrode of the fifth P-type metal oxide field effect transistor M5 through a fifth node N5 and a seventh node N7; or connected to the gate electrode of the third N-type metal oxide field effect transistor M3 through a fifth node N5, a seventh node N7 and an eighth node N8; or connected to the gate electrode of the third N-type metal oxide field effect transistor MP through a fifth node N5, a seventh node N7 and an eighth node N8); the drain electrode is coupled to a low power supply voltage VSS; the gate is coupled to the output of the error amplifier EA (the gate voltage VGU shown in fig. 3).

The drain electrode of the third N-type metal oxide field effect transistor M3 is connected to the drain electrode of the fourth P-type metal oxide field effect transistor M4 through a sixth node N6 (or coupled to the gate electrode of the fourth P-type metal oxide field effect transistor M4 through a sixth node N6 and a ninth node N9; or coupled to the gate electrode of the fifth P-type metal oxide field effect transistor M5 through a sixth node N6 and a ninth node N9); the gate is connected to the drain of the fifth pmos M5 through the eighth node N8 and the seventh node N7 (or to the source of the first pmos M1 through the eighth node N8, the seventh node N7 and the fifth node N5, or to the drain of the second pmos M2 through the eighth node N8, the seventh node N7 and the fifth node N5, or to the gate of the pmos MP through the eighth node N8), and the source is coupled to a low power supply voltage VSS.

The drain of the sixth N-type mosfet M6 is coupled to a high power voltage VDD, the gate is coupled to the output terminal (gate voltage VGD as shown in fig. 3) of the error amplifier EA, the source is coupled to the drain of the seventh N-type mosfet M7 through the tenth node N10 (or to the drain of the tenth N-type mosfet M10 through the tenth node N10 and the eleventh node N11), or to the gate of the eighth P-type mosfet M8 through the tenth node N10, the eleventh node N11 and the twelfth node N12), or to the gate of the N-type mosfet MN through the tenth node N10, the eleventh node N11 and the twelfth node N12.

The eighth P-type metal oxide field effect transistor M8 has a source coupled to a high power voltage VDD, a drain coupled to the drain of the ninth N-type metal oxide field effect transistor M9 through a thirteenth node N13 (or coupled to the gate of the ninth N-type metal oxide field effect transistor M9 through thirteenth and fourteenth nodes N13 and N14), a gate coupled to the gate of the N-type metal oxide field effect transistor MN through twelfth node N12 (or coupled to the drain of the tenth N-type metal oxide field effect transistor M10 through twelfth and eleventh nodes N12 and N11), or coupled to the source of the sixth N-type metal oxide field effect transistor M6 through twelfth and N12, eleventh and tenth nodes N11, or coupled to the drain of the seventh N-type metal oxide field effect transistor M7 through twelfth and tenth nodes N12 and N11).

The sources of the seventh N-type metal oxide field effect transistor M7, the tenth N-type metal oxide field effect transistor M10 and the ninth N-type metal oxide field effect transistor M9 are coupled to a low power voltage VSS; the gate of the seventh N-type metal oxide field effect transistor M7 is coupled to the bias voltage VBN (VBN is a gate voltage coupled to the seventh N-type metal oxide field effect transistor M7, and the voltage can be multiplexed with the reference voltage VREF of the error amplifier EA, but the application is not limited thereto); the drain is connected to the source of the sixth N-type metal oxide field effect transistor M6 through the tenth node N10 (or to the drain of the tenth N-type metal oxide field effect transistor M10 through the tenth node N10 and the eleventh node N11, or to the gate of the eighth P-type metal oxide field effect transistor M8 through the tenth node N10, the eleventh node N11 and the twelfth node N12, or to the gate of the N-type metal oxide field effect transistor MN through the tenth node N10, the eleventh node N11 and the twelfth node N12). The drain of the tenth N-type metal oxide field effect transistor M10 is connected with the drain of the seventh N-type metal oxide field effect transistor M7 through an eleventh node N11 and a tenth node N10 (or is connected with the source of the sixth N-type metal oxide field effect transistor M6 through the eleventh node N11 and the tenth node N10, or is connected with the gate of the eighth P-type metal oxide field effect transistor M8 through the eleventh node N11 and the twelfth node N12, or is connected with the gate of the N-type metal oxide field effect transistor MN through the eleventh node N11 and the twelfth node N12); the gate is connected to the gate of the ninth N-type metal oxide field effect transistor M9 through the fourteenth node N14 (or to the drain of the ninth N-type metal oxide field effect transistor M9 through the fourteenth node N14 and the thirteenth node N13; or to the drain of the eighth P-type metal oxide field effect transistor M8 through the fourteenth node N14 and the thirteenth node N13). The drain electrode of the ninth N-type metal oxide field effect transistor M9 is connected with the drain electrode of the eighth P-type metal oxide field effect transistor M8 through a thirteenth node N13; the gate is connected to the gate of the tenth N-type mosfet M10 through the fourteenth node N14.

The thirteenth node N13 is electrically connected to the fourteenth node N14.

The source electrode of the P-type metal oxide field effect power tube MP is coupled to a high power supply voltage VDD; the drain electrode is connected with the drain electrode of the N-type metal oxide field effect power tube MN; the gate is connected to the gate of the third N-type metal oxide field effect transistor M3 through the eighth node N8 (or to the drain of the fifth P-type metal oxide field effect transistor M5 through the eighth node N8 and the seventh node N7; or to the drain of the second P-type metal oxide field effect transistor M2 through the eighth node N8, the seventh node N7 and the fifth node N5; or to the source of the first P-type metal oxide field effect transistor M1 through the eighth node N8, the seventh node N7 and the fifth node N5).

The source of the N-type metal oxide field effect power transistor MN is coupled to a low power supply voltage VSS; the drain electrode is connected with the drain electrode of the P-type metal oxide field effect power tube MP; the gate is connected to the gate of the eighth P-type metal oxide field effect transistor M8 through the twelfth node N12 (or to the drain of the tenth N-type metal oxide field effect transistor M10 through the twelfth node N12 and the eleventh node N11; or to the drain of the seventh N-type metal oxide field effect transistor M7 through the twelfth node N12, the eleventh node N11 and the tenth node N10; or to the source of the sixth N-type metal oxide field effect transistor M6 through the twelfth node N12, the eleventh node N11 and the tenth node N10).

The coupling manner of the first resistor R1, the second resistor R2 and the capacitor CL is the same as that of fig. 1 and 2, and the detailed coupling manner is described with reference to the relevant portion of fig. 1 and is not repeated here.

Hereinafter, the operation principle thereof will be briefly described with reference to the LDO as shown in fig. 3.

The LDO circuit shown in fig. 3, wherein the buffer modules (the first buffer module and the second buffer module) have two functions: the impedance of grid points of the P-type metal oxide field effect power tube MP and the N-type metal oxide field effect power tube MN is reduced, the pole position is reduced, and the stability is facilitated; and secondly, raising the output voltage of the error amplifier by one Vgs, wherein Vgs is the voltage of a grid electrode relative to a source electrode, and reducing the static power consumption of the power tube.

The first detection module and the second detection module (or referred to as a first load current detection module and a second load current detection module) can change the current magnitude provided to the buffer module (the first buffer module and the second buffer module) according to the magnitude of the load current, so as to change Vgs of a source follower transistor (Source Follower Transistor, for example, a first P-type metal oxide field effect transistor M1 and a sixth N-type metal oxide field effect transistor M6 as shown in fig. 3) in the buffer module, thereby reducing the output current of power in a static state and providing better driving capability under a heavy load condition.

The first P-type metal oxide field effect transistor M1, the second P-type metal oxide field effect transistor M2, the third N-type metal oxide field effect transistor M3, the fourth P-type metal oxide field effect transistor M4 and the fifth P-type metal oxide field effect transistor M5 are used for providing the power transistor MP; a sixth N-type metal oxide field effect transistor M6, a seventh N-type metal oxide field effect transistor M7, an eighth P-type metal oxide field effect transistor M8, a ninth N-type metal oxide field effect transistor M9, a tenth N-type metal oxide field effect transistor M10; the power transistor MN is provided with the same functions, and the following description is given only of the working principles of the first pmos fet M1, the second pmos fet M2, the third nmos fet M3, the fourth pmos fet M4, and the fifth pmos fet M5:

in the static state (i.e., no load current), the current of the third N-type metal oxide field effect transistor M3 is represented by the formulaDetermination of beta _m3 For the process parameter M3, vthn is the threshold voltage of the N-type transistor, and VGP is the gate voltage of the power transistor MP. The current flowing through the fourth P-type mosfet M4 is Im3, and is transmitted to the fifth P-type mosfet M5 through the current mirror, and then to the buffer stage (i.e., the first buffer module). The buffer stage has a second P-type metal oxide field effect transistor M2 with a fixed current source, and assuming that the current is I1, the total current flowing through the source follower transistor M1 in the buffer stage is I1+Im3, according to the current formula->Wherein beta is _m1 As the process parameter of the transistor M1, vthp is the threshold voltage of the P-type transistor, vgs is the voltage difference between the gate and the source of the transistor M1, so that +.>At this time, VGP is VGU+Vgs, wherein VGU is the voltage output by the error amplifier, the gate voltage VGP of the power tube MP is larger, and the current formula is usedThe current is smaller, and the static power consumption is reduced.

When there is a current load (i.e. the power transistor MP needs to provide a larger load current), the gate voltage VGP of the power transistor MP will be reduced in the LDO feedback circuit to provide a large load current, and the current Im3 of the transistor M3 will be reduced, so that the current provided to the current source transistor M5 of the buffer stage is reduced. According to the current formula of the transistor M1, vgs thereof is reduced when the current is reduced, so that a lower gate voltage can be provided to the power transistor at this time as compared with a static VGU voltage, thereby improving driving capability.

The output impedance of the output point of the push-pull stage is reduced to 1/gm by the buffer stage, wherein gm is the transconductance of the transistor M1 in the buffer module, and is smaller, so that the size of the power tube is increased, and the parasitic capacitance of the point is increased, but the generated pole is smaller due to lower impedance and is far away from the main output pole, thereby being beneficial to frequency compensation and being more stable.

The invention provides a low-dropout linear voltage regulator circuit, in particular to a low-dropout linear voltage regulator of a push-pull output stage, which has low static power consumption and high load current, increases driving capability and does not increase static power consumption, and can effectively solve the problem of high power consumption of the low-dropout linear voltage regulator of the push-pull output stage. More specifically, the buffer stage and the load current detection module are included, the load current detection module increases or decreases the current supplied to the buffer stage according to the detected load current, the current of the buffer stage is changed by detecting the load current, so that low static power consumption and high load current are realized, and meanwhile, the frequency compensation can be better performed by the buffer stage.

The embodiment of the present invention uses a Metal-Oxide-semiconductor field effect transistor (MOSFET) as an example, but the present invention is not limited thereto, and those skilled in the art may use other kinds of transistors, for example: bipolar junction transistors (Bipolar Junction Transistor, BJT), junction field effect transistors (Junction Gate Field Effect Transistor, JFET) or fin field effect transistors (Fin Field Effect Transistor, finFET), and the like.

While the invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A low dropout linear voltage regulator circuit, comprising:

an error amplifier having an inverting input for receiving the feedback voltage and a non-inverting input for receiving the reference voltage;

the input end of the first buffer module is coupled to the output end of the error amplifier;

the first detection module and the second detection module are respectively coupled to the output ends of the first buffer module and the second buffer module;

the grid electrodes of the P-type power tube and the N-type power tube are respectively coupled to the output ends of the first detection module and the second detection module; the source electrode of the P-type power tube is coupled to the high power supply voltage, and the source electrode of the N-type power tube is coupled to the low power supply voltage; the drain electrode of the P-type power tube is connected with the drain electrode of the N-type power tube;

the buffer module is used for increasing the output voltage of the amplifier;

the load current detection module is used for detecting the magnitude of load current and changing the magnitude of current supplied to the buffer module according to the magnitude of the load current.

2. The low dropout linear regulator circuit according to claim 1, wherein the larger the load current, the smaller the current provided to the buffer module; the smaller the load current, the greater the current provided to the buffer module.

3. The low dropout linear voltage regulator circuit of claim 1, wherein said first buffer module comprises a first pmos and a second pmos.

4. The low dropout linear voltage regulator circuit of claim 1, wherein said second buffer module comprises a sixth N-type metal oxide field effect transistor and a seventh N-type metal oxide field effect transistor.

5. The low dropout linear voltage regulator circuit according to claim 1, wherein said first detecting module comprises a third N-type metal oxide field effect transistor, a fourth P-type metal oxide field effect transistor and a fifth P-type metal oxide field effect transistor.

6. The low dropout linear voltage regulator circuit according to claim 1, wherein said second detecting module comprises an eighth pmos fet, a ninth nmos fet and a tenth nmos fet.

7. The low dropout linear voltage regulator circuit according to claim 3, wherein a source of said first pmos is connected to a drain of said second pmos through a fifth node; the drain electrode is coupled to a low power voltage; the grid electrode is coupled to the output end of the error amplifier.

8. The low dropout linear regulator circuit according to claim 3, wherein a source of said second P-type metal oxide field effect transistor is coupled to a high supply voltage; the drain electrode is coupled to the source electrode of the first P-type metal oxide field effect transistor through a fifth node; the gate is coupled to a bias voltage.

9. The low dropout linear regulator of claim 4, wherein the sixth nmos has a drain coupled to the high supply voltage VDD, a gate coupled to the output of the error amplifier, and a source coupled to the drain of the seventh nmos through a tenth node.

10. The low dropout linear regulator circuit according to claim 4, wherein a source of said seventh N-type metal oxide field effect transistor is coupled to a low supply voltage; the grid electrode is coupled to the bias voltage; the drain is connected to the source of the sixth N-type metal oxide field effect transistor through a tenth node.

11. The low dropout linear voltage regulator circuit according to claim 5, wherein a drain of said third N-type metal oxide field effect transistor is connected to a drain of a fourth P-type metal oxide field effect transistor M4 through a sixth node; the gate is connected to the drain of the fifth P-type mosfet M5 through the eighth node and the seventh node, and the source is coupled to a low power voltage.

12. The low dropout linear regulator circuit according to claim 5, wherein a source of said fourth pmos is coupled to a high supply voltage; the drain electrode is connected with the drain electrode of the third N-type metal oxide field effect transistor through the sixth node, and the grid electrode is connected with the grid electrode of the fifth P-type metal oxide field effect transistor through the ninth node.

13. The low dropout linear regulator circuit according to claim 5, wherein a source of said fifth pmos is coupled to a high supply voltage; the drain electrode is connected with the source electrode of the first P-type metal oxide field effect transistor through a seventh node and a fifth node; the gate is connected to the gate of the fourth P-type mosfet M4 through the ninth node N9.

14. The low dropout linear regulator circuit according to claim 6, wherein the eighth pmos has a source coupled to the high power supply voltage VDD, a drain coupled to the drain of the ninth nmos through a thirteenth node, and a gate coupled to the gate of the nmos through a twelfth node.

15. The low dropout linear regulator circuit according to claim 6, wherein a source of said ninth N-type metal oxide field effect transistor is coupled to a low supply voltage; the drain electrode is connected with the drain electrode of the eighth P-type metal oxide field effect transistor through a thirteenth node; the grid electrode is connected with the grid electrode of the tenth N-type metal oxide field effect transistor through a fourteenth node.

16. The low dropout linear regulator circuit according to claim 6, wherein a source of said tenth nmos is coupled to a low supply voltage; the drain electrode is connected with the drain electrode of the seventh N-type metal oxide field effect transistor through an eleventh node and a tenth node; the grid electrode is connected with the grid electrode of the ninth N-type metal oxide field effect transistor through a fourteenth node.

17. The low dropout linear voltage regulator circuit according to claim 12, wherein the drain and the gate of the fourth pmos are electrically connected to the ninth node through a sixth node.

18. The low dropout linear voltage regulator circuit according to claim 15, wherein the drain and the gate of the ninth N-type mosfet are electrically connected to the fourteenth node through a thirteenth node.

19. The low dropout linear voltage regulator circuit according to claim 1, wherein the first buffer module and the second buffer module have the same or different structures, and/or the first load current detection module and the second load current detection module have the same or different structures.